GAISLER

IEEE-STD-754 Floating Point Unit
GRFPU Lite / GRFPU-FT Lite
CompanionCore Data Sheet
GAISLER
Features
Description
• IEEE Std 754 compliant, supporting all
rounding modes and exceptions
• Operations: add, subtract, multiply, divide,
square-root, convert, compare, move, abs,
negate
• Single and double precision (32- and 64-bit
floats) data formats
• Supports all SPARC V8 floating-point
instructions
• Fault-tolerant (FT) version available
• Actel CompanionCore
• Support for Fusion, IGLOO, ProASIC3/E,
Axcelerator and RTAX-S Product Families
The GRFPU Lite is an IEEE Std 754 compliant
floating-point unit, supporting both single and
double precision operands. All operations are
IEEE Std 754 compliant, with the exception of
denormalized numbers which are flushed to zero.
The specified four rounding modes and the
detection of exception conditions is fully
supported.
GRFPU
Lite
clk
reset
opcode
operand1
ctrl_out
Unpack
Iteration unit
(Add/Sub/Mul/Div)
operand2
Pack
result
except
cc
round
ctrl_in
Control
unit
Applications
The GRFPU Lite floating point unit is designed
for embedded applications, combining high
performance with low complexity and low power
consumption. The GRFPU Lite has been
designed to interface with the LEON3 SPARC
processor.
The fault-tolerant version of the GRFPU Lite in
combination with the radiation tolerant Actel
RTAX2000S FPGA gives a total immunity to
radiation effects. This makes it ideally suited for
space and other high-rel applications.
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1
Introduction
1.1
Overview
GRFPU Lite / GRFPU-FT Lite
GRFPU Lite is a Floating Point Unit implementing floating-point operations as defined in IEEE Standard for Binary Floating-Point Arithmetic (IEEE Std 754) and SPARC V8 standard (IEEE Std 1754).
Supported formats are single and double precision floating-point numbers.
The GRFPU Lite interfaces the LEON3 SPARC V8 integer unit via the GRFPU Lite Control Unit
(GRFPC Lite), as shown in figure 1.
Register File
LEON3
Integer Unit
GRFPC Lite
GRFPU Lite
Figure 1. GRFPU Lite intergrated with the LEON3 processor via GRFPC Lite Control Unit
The Fault-Tolerant (FT) version of the GRFPU Lite and GRFPC Lite include SEU protection by
design. The FPU register file is protected using (32, 7) BCH coding, while all other registers are protected with TMR.
1.2
Signal overview
The combined GRFPU / GRFPC Lite signals are shown in figure 2 and are directly compatible with
the LEON3 processor core. Note that the interface signals are implemented as VHDL records and are
not shown in detail.
clk
rst
Clock & Reset
holdn
fpci
Integer Unit
Interface
fpco
rfo1
Register File
Interface
rfi1
rfo2
rfi2
Figure 2. Signal overview
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December 2008, Version 1.0.4
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1.3
3
GRFPU Lite / GRFPU-FT Lite
Implementation characteristics
The GRFPU / GRFPC Lite core is inherently portable and can be implemented on most FPGA and
ASIC technologies. Table 1 shows the approximate cell count and frequency for different example
configurations on Actel RTAX and ProASIC3.
Table 1. Implementation characteristics (Cells / RAM blocks / AHB MHz)
Core configuration
RTAX2000S-1
ProASIC3
GRFPU/GRFPC Lite
7000 / 4 / 20 MHz
12000 / 4 / 30 MHz
GRFPU/GRFPC-FT Lite
7100 / 4 / 20 MHz
13000 / 4 / 30 MHz
The GRFPU Lite and GRFPU-FT Lite cores are available as pre-synthesized netlists only. The
GRFPU Lite is only avialable bundled with the GRFPC Lite interface.
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GRFPU Lite / GRFPU-FT Lite
2
GRFPU Lite - IEEE-754 Floating-Point Unit
2.1
Overview
The GRFPU Lite floating-point unit implements floating-point operations as defined in IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754) and SPARC V8 standard (IEEE-1754).
Supported formats are single and double precision floating-point numbers. The floating-point unit is
not pipelined and executes one floating-point operation at a time.
GRFPU
Lite
clk
reset
ctrl_out
Unpack
opcode
operand1
Iteration unit
(Add/Sub/Mul/Div)
operand2
Pack
result
except
cc
round
ctrl_in
Control
unit
2.2
Functional Description
2.2.1
Floating-point number formats
The floating-point unit handles floating-point numbers in single or double precision format as defined
in IEEE-754 standard.
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2.2.2
5
GRFPU Lite / GRFPU-FT Lite
FP operations
The floating-point unit supports four types of floating-point operations: arithmetic, compare, convert
and move. The operations implement all FP instructions specified by SPARC V8 instruction set. All
operations are summarized in the table below.
Table 2. :Floating-point operations
Operation
Op1
Op2
Result
Exceptions
Description
Arithmetic operations
FADDS
FADDD
SP
DP
SP
DP
SP
DP
NV, OF, UF, NX
Addition
FSUBS
FSUBD
SP
DP
SP
DP
SP
DP
NV, OF, UF, NX
Subtraction
FMULS
FMULD
FSMULD
SP
DP
SP
SP
DP
SP
SP
DP
DP
NV, OF, UF, NX
Multiplication
FDIVS
FDIVD
SP
DP
SP
DP
SP
DP
NV, OF, UF, NX
Division
FSQRTS
FSQRTD
-
SP
DP
SP
DP
NV, NX
Square-root
NV, OF, UF, NX
NV,OF, UF
Conversion operations
FITOS
FITOD
-
INT
SP
DP
NX
-
Integer to floating-point conversion
FSTOI
FDTOI
-
SP
DP
INT
NV, NX
Floating-point to integer conversion. The result is
rounded in round-to-zero mode.
FSTOD
FDTOS
-
SP
DP
DP
SP
NV
NV, OF, UF, NX
Conversion between floating-point formats
Comparison operations
FCMPS
FCMPD
SP
DP
SP
DP
CC
NV
Floating-point compare. Invalid exception is generated if either operand is a signaling NaN.
FCMPES
FCMPED
SP
DP
SP
DP
CC
NV
Floating point compare. Invalid exception is generated if either operand is a NaN (quiet or signaling).
Negate, Absolute value and Move
FABSS
-
SP
SP
-
Absolute value.
FNEGS
-
SP
SP
-
Negate.
FMOVS
SP
SP
-
Move. Copies operand to result output.
SP - single precision floating-point number
CC - condition codes
NV, OF, UF, NX - floating-point exceptions, see section 2.2.3
DP - double precision
floating-point number
INT - 32 bit integer
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GRFPU Lite / GRFPU-FT Lite
Below is a table of worst-case throughput of the floating point unit.
Table 3. Worst-case instruction timing
Instruction
Throughput
Latency
FADDS, FADDD, FSUBS, FSUBD,FMULS, FMULD, FSMULD, FITOS,
FITOD, FSTOI, FDTOI, FSTOD, FDTOS, FCMPS, FCMPD, FCMPES.
FCMPED
8
8
FDIVS
31
31
FDIVD
57
57
FSQRTS
46
46
FSQRTD
65
65
2.2.3
Exceptions
The floating-point unit detects all exceptions defined by the IEEE-754 standard. This includes detection of Invalid Operation (NV), Overflow (OF), Underflow (UF), Division-by-Zero (DZ) and Inexact
(NX) exception conditions. Generation of special results such as NaNs and infinity is also implemented.
2.2.4
Rounding
All four rounding modes defined in the IEEE-754 standard are supported: round-to-nearest, round-to+inf, round-to--inf and round-to-zero.
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3
GRLFPC - GRFPU Lite Floating-point unit Controller
3.1
Overview
GRFPU Lite / GRFPU-FT Lite
The GRFPU Lite Floating-Point Unit Controller (GRLFPC) is used to attach the GRFPU Lite floating-point unit (FPU) to the LEON integer unit (IU). It performs decoding and dispatching of the floating-point (FP) operations to the floating-point unit as well as managing the floating-point register file,
the floating-point state register (FSR) and the floating-point deferred-trap queue (FQ).
The GRFPU Lite floating-point unit is not pipelined and executes only one instruction at a time. To
improve performance, the controller (GRLFPC) allows the GRFPU Lite floating-point unit to execute
in parallel with the processor pipeline as long as no new floating-point instructions are pending.
3.2
Floating-Point register file
The floating-point register file contains 32 32-bit floating-point registers (%f0-%f31). The register
file is accessed by floating-point load and store instructions (LDF, LDDF, STD, STDF) and floatingpoint operate instructions (FPop).
In the FT-version, the floating-point register file is protected using 4-bit parity per 32-bit word. The
controller is capable of detecting and correcting one bit error per byte. Errors are corrected using the
instruction restart function in the IU.
3.3
Floating-Point State Register (FSR)
The controller manages the floating-point state register (FSR) containing FPU mode and status information. All fields of the FSR register as defined in SPARC V8 specification are implemented and
managed by the controller conform to the SPARC V8 specification and IEEE-754 standard.
The non-standard bit of the FSR register is not used, all floating-point operations are performed in
standard IEEE-compliant mode.
Following floating-point trap types never occur and are therefore never set in the ftt field:
- unimplemented_FPop: all FPop operations are implemented
- unfinished_FPop: all FPop operation complete with valid result
- invalid_fp_register: no check that double-precision register is 0 mod 2 is performed
The controller implements the qne bit of the FSR register which reads 0 if the floating-point deferredqueue (FQ) is empty and 1 otherwise. The FSR is accessed using LDFSR and STFSR instructions.
3.4
Floating-Point Exceptions and Floating-Point Deferred-Queue
The floating-point unit implements the SPARC deferred trap model for floating-point exceptions
(fp_exception). A floating-point exception is caused by a floating-point instruction performing an
operation resulting in one of following conditions:
•
an operation raises IEEE floating-point exception (ftt = IEEE_754_exception) e.g. executing
invalid operation such as 0/0 while the NVM bit of the TEM field id set (invalid exception
enabled).
•
sequence error: abnormal error condition in the FPU due to the erroneous use of the floatingpoint instructions in the supervisor software.
•
hardware_error: uncorrectable parity error is detected in the FP register file
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GRFPU Lite / GRFPU-FT Lite
The trap is deferred to the next floating-point instruction (FPop, FP load/store, FP branch) following
the trap-inducing instruction. When the trap is taken the floating-point deferred-queue (FQ) contains
the trap-inducing instruction.
After the trap is taken the qne bit of the FSR is set and remains set until the FQ is emptied. STDFQ
instruction reads a double-word from the floating-point deferred queue, the first word is the address of
the instruction and the second word is the instruction code.
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GRFPU Lite / GRFPU-FT Lite
Reference documents
[AMBA]
AMBA Specification, Rev 2.0, ARM IHI 0011A, 13 May 1999, Issue A, first
release, ARM Limited
[GRLIB]
GRLIB IP Library User's Manual, Aeroflex Gaisler, www.aeroflex.com/gaisler
[GRIP]
GRLIB IP Core User's Manual, Aeroflex Gaisler, www.aeroflex.com/gaisler
[SPARC]
The SPARC Architecture Manual, Version 8, Revision SAV080SI9308, SPARC
International Inc.
[IEEE]
IEEE Standard for Binary Floating-Point Arithmetic, IEEE Std 754-1985
Ordering information
Ordering information is provided in table 4 and a legend is provided in table 5.
Table 4. Ordering information
Product
Source code
Netlist
Technology
GRFPU/GRFPC Lite
N/A
EDIF/VHDL
Any
GRFPU/GRFPC-FT Lite
N/A
EDIF/VHDL
RTAX
Option
Description
GRFPU/GRFPC Lite
Floating Point Unit and Control Unit
GRFPU/GRFCP-FT Lite
Fault-Tolerant Floating Point Unit and Control Unit
EDIF
EDIF gate-level netlist
VHDL
VHDL gate-level netlist
AX
Axcelerator
Table 5. Ordering legend
Designator
Product
Netlist
Technology
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RTAX
Fault-Tolerant Axcelerator
PROASIC3
ProASIC3
PROASICE
ProASICE
FUSION
Fusion
IGLOO
IGLOO
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GRFPU Lite / GRFPU-FT Lite
Table of contents
1
Introduction.............................................................................................................................. 2
1.1
1.2
1.3
2
GRFPU Lite - IEEE-754 Floating-Point Unit.......................................................................... 4
2.1
2.2
3
Overview ................................................................................................................................................. 2
Signal overview ....................................................................................................................................... 2
Implementation characteristics................................................................................................................ 3
Overview ................................................................................................................................................. 4
Functional Description ............................................................................................................................ 4
2.2.1
Floating-point number formats ................................................................................................. 4
2.2.2
FP operations ............................................................................................................................ 5
2.2.3
Exceptions................................................................................................................................. 6
2.2.4
Rounding................................................................................................................................... 6
GRLFPC - GRFPU Lite Floating-point unit Controller .......................................................... 7
3.1
3.2
3.3
3.4
Overview ................................................................................................................................................. 7
Floating-Point register file....................................................................................................................... 7
Floating-Point State Register (FSR)........................................................................................................ 7
Floating-Point Exceptions and Floating-Point Deferred-Queue ............................................................. 7
4
Reference documents ............................................................................................................... 9
5
Ordering information ............................................................................................................... 9
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GRFPU Lite / GRFPU-FT Lite
Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable.
However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB.
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GAISLER
Copyright © December 2008 Aeroflex Gaisler AB.
All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither
implicit nor explicit.
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December 2008, Version 1.0.4