IGLOO2 Evaluation Kit Webinar

Power Matters.
IGLOO2 Evaluation Kit Webinar
Jamie Freed
[email protected]
August 29, 2013
© 2013 Microsemi Corporation. COMPANY PROPRIETARY
Overview
M2GL010TFG484
$99*
LPDDR
10/100/1G
Ethernet
SERDES
SMAs
USB UART
Small Form
Factor
Available
Demos
PCI Express
x1
* Limited Quantity
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Power Matters.
2
Agenda
 Quick overview of IGLOO2
 Feature Set of the HPMS
 Feature Set of the Board
•
•
•
•
Interfaces
Memory
Expansion
Power
 Kit contents
 Demos
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Power Matters.
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IGLOO2 Block Diagram
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Power Matters.
4
Microsemi IGLOO2 Family
Logic / DSP
Features
Maximum Logic Elements
(4LUT+DFF)
Math Blocks (18x18)
M2GL005
M2GL010
M2GL025
M2GL050
M2GL090
M2GL100
M2GL150
6,060
12,084
27,696
56,340
86,316
99,512
146,124
11
22
34
72
84
160
240
PLLs and CCCs
2
SPI/HPDMA/PDMA
Memory
AES256, SHA256, RNG
AES256, SHA256, RNG, ECC, PUF
eNVM (K Bytes)
128
LSRAM 18K Blocks
10
21
31
69
109
160
236
uSRAM1K Blocks
11
22
34
72
112
160
240
256
1826
2586
3553
5000
2x36
1x18
8
4
eSRAM (K Bytes)
Total RAM (K bits)
High
Speed
8
1 each
Security
User I/Os
6
512
64
703
DDR Controllers
912
1104
1x18
SERDES Lanes
0
4
PCIe End Points
0
1
2x36
8
2
16
4
MSIO (3.3V)
115
123
157
139
306
292
292
MSIOD (2.5V)
28
40
40
62
40
106
106
DDRIO (2.5V)
66
70
70
176
66
176
176
Total User I/O
209
233
267
377
412
574
574
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Power Matters.
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High Performance Memory Subsystem
 Reduces your design effort, power, and cost
 Embedded memories
 eNVM - Flash


Storage of User Information, Keys, Ethernet MAC ID’s, System configuration
data
Secure Boot of external application processors
 Embedded SRAM’s (2.6Gbps of bandwidth)



Local zero wait state memory for video / graphics applications
Predictable latency for time critical embedded applications
Largest monolithic memory blocks in the industry
 Built-in support for managing embedded memories
 2 DMA Engines to move data efficiently in and out of the
device



Video Frame Buffers
TCP/IP Buffers
PCIe Packets
 DDR bridge – 2 port memory cache

Lowers power and increases system throughput
Embedded Memories with Commonly Used Functions in Serial
Protocol Implementations Saves 18K LEs!
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Power Matters.
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Multi Protocol 5Gb/s SERDES
 Physical Media Attachment (PMA) Features
• Up to 16 lanes at up to 5Gbps
• Dual based reference clocks with single-lane rate granularity
– Reference clock is shared per groups of two lanes
• Transmitter Features
– Programmable Pre/Post-Emphasis
– Programmable Impedance
– Programmable Amplitude
• Receiver Features
– Programmable Termination
– Programmable Linear Equalization
• Built-In System Debug Features
– PRBS Gen/Chk
– Constant Patterns
– Loopbacks
IGLOO2 Eye Diagram
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Power Matters.
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SERDES / Hard IP architecture
PMA - Multi-Protocol 5G transceiver
Organized in blocks of x4
4 blocks max for 16 lanes
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Power Matters.
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PCI Express
 Embedded PCIe Solution
• GEN1 (2.5Gbps) and GEN2 (5.0Gbps)
• x1, x2, x4 Link Widths
• Full Protocol Stack
–
–
–
–
Physical Layer
Data Link Layer
Transaction Layer
AXI4 or AHB32Lite FPGA Interface
• Endpoint topology
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Power Matters.
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IGLOO2 Evaluation Kit
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Power Matters.
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SERDES Interfaces
PCIe
• x1 5.0Gbps Edge Fingers
• Control Plane Demo is pre-loaded
• Small Form-Factor PCIe Compliant
Ethernet
• 10/100/1000BASE-T
• RJ45 Connector
• Marvel PHY with SGMII to SERDES
– SmartFusion2 embedded MAC
– IGLOO2 soft IP MAC
SERDES
• Full-Duplex Pair of SMAs with SMA REFCLK
• Built-In SERDES Tx-Rx loopback in board traces
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Power Matters.
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Memory
Low-Power DDR
•
•
•
•
512MB
16-bit Interface to IGLOO2 using MDDR pins
No ECC (Would require 2 devices)
Operational up to 400Mbps (6.4Gbps aggregate)
SPI Flash
• 64Mbit
• Connected to SPI_0 of HPMS (Configuration)
• Useful for In-Application Programming
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Power Matters.
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Expansion Interfaces
GPIO Header
• 3.3V 64-bit
• 64-bit Single-Ended
• 32 pairs of LVDS
USB-UART
• FTDI USB-UART Device Interface
• Standard interface for demo control
SmartFusion2 Interfaces
• USB-OTG
• I2C Header
– Expansion or Loopback
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Power Matters.
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Power Sources
12V Wall-Mount Power Supply
• Standard On/Off Switch
PCIe Edge Fingers
• 12V Power is provided through the PCIe slot
• Allows demonstration of PCIe power-up
• Standard On/Off Switch
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Power Matters.
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Microsemi DC/DC
Part
Iout
Vin
Fsw
(Mhz)
Vout (V)
Package
LX8240
0.8A
1 - 5.5
LDO
0.5-2.0
DFN 3x2
LX13043
1A
4.5 - 10
LDO
3.3
DFN 3x3
LX7186A
1A
2.5-6
1.4
0.6-3.3
TSOT-5
LX7167
2.4A
3 - 5.5
3.0
0.8-3.3
DFN 2x2
LX7175
3A
3 - 5.5
1.4
0.6-3.3
DFN 3x3
LX7165
5A
3 - 5.5
1.9
0.6-3.3
CSP 1.6x2
NX9548
8A
4.5 – 24
0.8
0.75-5
DFN 5x5
12V
NX9548
8A Buck
 All Regulators 2.4A to 8A w/Hysteretic Control
Ultra-Fast Transient Response
Constant Frequency - Patented
Less Components
Smaller Output Filter
More Efficient at Light Loads
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5V
LX13043
1A LDO
3.3V
LX13043
1A LDO
3.3V
LX7165
5A Buck
w/I2C
1.2V
LX7167
2.4A Buck
Reg
1.8V
LX7175 3A
Buck Reg
2.5V
LX7186A 1A
Buck Reg
1.0V
LX7165
5A Buck Reg
w/I2C
LX8240
0.8A LDO
2.5V
3.3V
Power Matters.
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Power Measurement
VDD 1.2V Rail
• Two different measurement circuits and test points
– Normal Operation 100mA – 2A
– Flash*Freeze 2mA – 10mA
• Enabled by a jumper
• Uses opamp gain to allow for hand-held voltmeter to measure both
Normal and Flash*Freeze current.
LPDDR Interface and Device 1.8V Rail
• Same scheme as the VDD 1.2V Rail
• Supports both Normal Operation and Flash*Freeze circuits
SERDES LDO Power
• Sense resistor measurement
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Power Matters.
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PCIe Small Form-Factor
ExpressCard Slot of Laptop
w/ Adapter
PCIe x4 Slot of Desktop
Direct Plug-In
Note: A x1 PCIe card can
work in any size PCIe slot
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Power Matters.
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Kit Contents
 IGLOO2 Evaluation Board
• 12K LE M2GL010T-1FGG484
 12V Wall-Mounted Power Supply
 FlashPro4 Programmer
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Power Matters.
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Available Demos
 PCI Express
• Control Plane Tutorial - Preloaded
• Data Plane Demo – Fall 2013
• In-Application Programming Demo – Fall 2013
 SERDES
• 1-5Gbps SERDES Demo
– EPCS Based SERESIF
– GUI Application for Demo Control
– Eye Diagram and/or FPGA based PRBS pattern gen/chk
• 500Mbps SERDES Demo
– Oversampling technique for less than 1Gbps applications
 DSP
• Adaptive FIR Demo
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Power Matters.
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IGLOO2 PCIe Control Plane Demo
IGLOO2
 Plugs into any PCIe slot
• Any available slot since a x1 is required for PCIe compliance
• ExpressCard for laptops also supported with adapter card
 From Host PC GUI
•
•
•
•
•
Wiggle LEDs and Read status of DIP Switches
R/W to the eSRAM
Capture a PCIe interrupt sent from the Evaluation Kit
Read the Device Serial Number of the device
Store eNVM data to be read back
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Power Matters.
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PCIe Tutorial
 This is a Libero PCIe tutorial as well as a silicon demo
 User builds the entire design
•
•
•
•
Libero Project with System Builder
Configure the SERDESIF
Import a user Verilog file
Make connections in SmartDesign
• Simulate with the PCIe BFM
• Download STAPL file
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Power Matters.
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IGLOO2 PCIe Control Plane Demo
IGLOO2
IGLOO2
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Power Matters.
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IGLOO2 PCIe Data Plane Demo
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Power Matters.
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SERDES Demos
SERDES Demo
 Two SERDES Demos
• 1Gbps – 5Gbps Demo
• 500Mbps Demo (Oversampling)
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Power Matters.
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Ordering
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Power Matters.
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