The fido1100®

fido5x00 Real-time Ethernet Multi-protocol (REM) Switch
Preliminary Datasheet
February 5, 2014
fido5x00
Real-time Ethernet Multi-protocol (REM)
Switch
Preliminary Datasheet
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fido5x00 Real-time Ethernet Multi-protocol (REM) Switch
Preliminary Datasheet
Copyright
February 5, 2014
2014 by Innovasic, Inc.
Published by Innovasic, Inc.
5635 Jefferson St. NE, Suite A, Albuquerque, New Mexico 87109 USA
RapID Platform, PriorityChannel®, fido®, fido1100®, are trademarks and register
marks of Innovasic, Inc.
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Preliminary Datasheet
February 5, 2014
TABLE OF CONTENTS
Conventions .....................................................................................................................................6
Acronyms and Abbreviations ..........................................................................................................7
1.
Introduction ............................................................................................................................8
1.1 General Description ......................................................................................................9
1.2 Features .......................................................................................................................11
2.
Packages, Pin Assignments, and Physical Dimensions........................................................12
2.1 324-Pin Ultra-fine Ball Grid Array (UBGA) Package ...............................................12
2.1.1 Pin Assignments and Signal Descriptions ......................................................12
2.1.2 Package Dimensions .......................................................................................27
2.2 8-Pin V-PDFN-8 Package...........................................................................................28
2.2.1 Pinout Definition ............................................................................................28
2.2.2 Package Dimensions .......................................................................................29
3.
Design Considerations..........................................................................................................29
3.1 Power Considerations .................................................................................................29
3.2 Reset ...........................................................................................................................30
3.3 PHYs ...........................................................................................................................30
3.3.1 Clocking ..........................................................................................................30
3.3.2 MDIO ..............................................................................................................30
3.4 Board Layout ..............................................................................................................32
4.
Device Interfaces ..................................................................................................................32
4.1 Oscillator.....................................................................................................................32
4.2 Reset ...........................................................................................................................33
4.3 Timers .........................................................................................................................33
4.3.1 Timer0 – Timer3 .............................................................................................33
4.3.2 Timer4 – Timer7 .............................................................................................33
4.4 Host Interface..............................................................................................................34
4.4.1 Multiplex Bus Select.......................................................................................34
4.4.2 Data Bus Width...............................................................................................34
4.4.3 Endianness ......................................................................................................34
4.4.4 Address/Data Bus Operation ..........................................................................34
4.4.4.1 Non-Multiplexed Address Data Bus ..............................................34
4.4.4.2 Multiplexed Address Data Bus ......................................................34
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Preliminary Datasheet
4.5
4.6
February 5, 2014
4.4.5 Register and Data Access ...............................................................................38
4.4.6 Interrupts .........................................................................................................39
Ethernet Interface........................................................................................................39
4.5.1 Connections ....................................................................................................39
4.5.2 Link Status and Activity .................................................................................39
REM Switch Memory .................................................................................................42
5.
Absolute Ratings and Operating Conditions ........................................................................43
5.1 REM Switch................................................................................................................43
5.2 REM Switch Memory .................................................................................................44
6.
DC Specifications .................................................................................................................44
6.1 REM Switch................................................................................................................44
6.2 Pin Capacitance ..........................................................................................................44
6.3 Leakage Current..........................................................................................................45
7.
AC Specifications .................................................................................................................45
7.1 Bus Hold Parameters ..................................................................................................45
8.
Revision History ...................................................................................................................46
9.
For Additional Information ..................................................................................................46
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Preliminary Datasheet
February 5, 2014
LIST OF FIGURES
Figure 1 – Example application for the REM Switch ......................................................................9
Figure 2 – REM Switch Top Level I/O Definition ........................................................................10
Figure 3 – REM Switch UBGA Ball Grid Definition....................................................................12
Figure 4 – REM Switch Northwest Quadrant Signal Assignments ...............................................13
Figure 5 – REM Switch Northeast Quadrant Signal Assignments ................................................14
Figure 6 – REM Switch Southeast Quadrant Signal Assignments ................................................15
Figure 7 – REM Switch Southwest Quadrant Signal Assignments ...............................................16
Figure 8 – REM Switch Package Dimensions ...............................................................................27
Figure 9 – REM Switch Memory Signal Assignments ..................................................................28
Figure 10 – REM Switch Memory Package Dimensions ..............................................................29
Figure 11 – Example Oscillator Clock Source Circuit ..................................................................32
Figure 12 – REM Switch Non-Multiplexed Address/Data Bus Read Timing...............................35
Figure 13 – REM Switch Non-Multiplexed Address/Data Bus Write Timing ..............................35
Figure 14 – REM Switch Multiplexed Address/Data Bus Read Timing .......................................37
Figure 15 – REM Switch Multiplexed Address/Data Bus Write Timing ......................................37
Figure 16 – REM Switch configured for RMII Interface ..............................................................41
Figure 17 – REM Switch configured for MII Interface .................................................................41
Figure 18 – REM Switch configured for GMII Interface ..............................................................42
LIST OF TABLES
Table 1 – Part Number Definition for the REM Switch ..................................................................8
Table 2 – Cross Reference for the REM Switch Driver User’s Guide ............................................8
Table 3 – Power Signal Names and Descriptions ..........................................................................17
Table 4 – CPU Signal Names and Descriptions ............................................................................18
Table 5 – Memory Signal Names and Descriptions ......................................................................22
Table 6 – Port 1 and Port 2 Signal Names and Descriptions .........................................................22
Table 7 – Bus and Data Configuration Signal Names and Descriptions .......................................25
Table 8 – Configuration Signal Names and Descriptions ..............................................................25
Table 9 – No Connect Signal Names and Descriptions .................................................................26
Table 10 – Memory Signal Descriptions .......................................................................................28
Table 11 – PHY Selection Guide ...................................................................................................31
Table 12 – Non-Multiplexed Address Data Bus, Read and Write Cycle Timing Parameters .......36
Table 13 – Multiplexed Address Data Bus, Read and Write Cycle Timing Parameters ...............38
Table 14 – Register Definitions .....................................................................................................40
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CONVENTIONS
Arial Bold
Designates headings, figure captions, and table captions.
Blue
Designates hyperlinks (PDF copy only).
Italics
Designates emphasis or caution related to nearby information. Italics is also
used to designate variables, refer to related documents, and to differentiate
terms from other common words (e.g., “During refresh cycles, the a and ad
buses may not have the same address during the address phase of the ad bus
cycle.” “The hold latency time [time between the hold and hlda] depends on
the current processor activity when the hold is received.”).
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Preliminary Datasheet
February 5, 2014
ACRONYMS AND ABBREVIATIONS
API
DCP
DHCP
DLR
GMII
HSR
I
I/O
IEEE
IGMP
PRP
LED
LLDP
MII
MRP
MRPD
O
PCB
PLL
REM
RoHS
RMII
RSTP
VLAN
UBGA
Application Programming Interface
Discovery Configuration Protocol
Dynamic Host Configuration Protocol
Device Level Ring
Gigabit Media Independent Interface
High Availability Seamless Redundancy
Input
Input/Output
Institute of Electrical and Electronics Engineers
Internet Group Management Protocol
Parallel Redundancy Protocol
Light Emitting Diode
Link Layer Discovery Protocol
Media Independent Interface
Media Redundancy Protocol
Media Redundancy for Planned Duplication
Output
Printed Circuit Board
Phase Locked-Loop
Real-time Ethernet Multi-protocol
Restriction of Hazardous Substance
Reduced Media Independent Interface
Rapid Spanning Tree Protocol
Virtual Local Area Network
Ultra Fineline Ball Grid Array
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1.
February 5, 2014
Introduction
The fido5x00 is a 10/100/1000 Ethernet switch that can be programmed to support virtually any
Layer 2 or Layer 3 protocol. The switch is personalized to support the desired protocol by
firmware that is downloaded from a host processor. The firmware is contained in the REM
Switch driver, and is downloaded at power-up. The REM Switch can be ready for network
operation in less than 350ms in order to support Fast Start-Up and Quick Connect-type network
functionality. All fido5x00 devices have the same signal assignments as defined in this
datasheet. Table 1 defines the fido5x00 part numbers for the associated protocols.
Table 1 – Part Number Definition for the REM Switch
Part Number
Protocol Supported
fido5100
PROFINET RT and IRT
EtherNet/IP with and without DLR,
ModbusTCP, SERCOS III, POWERLINK
fido5200
EtherCAT, plus all protocols defined for the fido5100
The REM Switch driver for each protocol is provided as object code with headers. Table 2
defines the User’s Guides for each protocol. These guides describe each protocol’s driver and
how to integrate it into a host processor.
Table 2 – Cross Reference for the REM Switch Driver User’s Guide
Protocol
Document Title
Document #
Status
PROFINET RT
and IRT
PROFINET RT and IRT
REM Switch Driver User’s Guide
ENG321130521-00
Drafting
EtherNet/IP with
and without DLR
EtherNet/IP with and without DLR
REM Switch Driver User’s Guide
ENGxxxxxxxxx-00
Future
ModbusTCP
ModbusTCP REM Switch Driver
User’s Guide
ENGxxxxxxxxx-00
Future
SERCOS III
SERCOS III REM Switch Driver
User’s Guide
ENGxxxxxxxxx-00
Future
POWERLINK
POWERLINK REM Switch Driver
User’s Guide
ENGxxxxxxxxx-00
Future
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Preliminary Datasheet
February 5, 2014
This datasheet provides all of the hardware information to design the REM Switch into a circuit
board and is organized into the following sections:
Packaging, Pin Descriptions, and Physical Dimensions
Device Architecture
Maximum Ratings, Thermal Characteristics and DC Parameters
AC Specifications
1.1
General Description
The REM Switch is intended for use with a host processor. Network operation is handled using
the functions and services provided in the REM Switch driver. The host processor may
implement any protocol stack by integrating it with the REM Switch driver. An example
application is shown in Figure 1 below.
Figure 1 – Example application for the REM Switch
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A top level definition of the I/O for the REM Switch is shown in Figure 2.
Figure 2 – REM Switch Top Level I/O Definition
The basic REM Switch hardware is identified as the fido5000 and REM Switch memory is
identified as the fido0x00 where the x indicates the memory version for the supported protocols.
The fido0100 is for the following protocols:
PROFINET RT and IRT
EtherNet/IP with and without DLR
ModbusTCP
SERCOS III
POWERLINK
The fido0200 is for the following protocols:
EtherCAT, plus all protocols defined for the fido0100
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1.2
February 5, 2014
Features
The basic features of the REM Switch are listed below. Please refer to the applicable driver
user’s guide for protocol-specific features.
324-lead UBGA RoHS-Compliant Package
-40 to +85C Industrial Temperature Range Rating
3.3V I/O
IEEE 802.3, 10/100/1000 Mb/s, Half and Full Duplex, IPv6 and IPv4 Communication
2 independent ports – 1 RMII and 1 GMII interface per port
Support for All Industrial Protocols:
o PROFINET Class B and C with Fast Start-Up (version 2.3)
o EtherNet/IP with QuickConnect, CIPSync, and CIPMotion
o ModbusTCP
o EtherCAT
o SERCOS III
o Powerlink
Host Interface Transfer Rate of 32-bits every 20 ns – Supports EtherCAT cycle times
down to 12.5 us and PROFINET cycle times down to 31.25 us
PI Net Load Class III Capable
DLR (supervisor and node, announce and beacon-based), MRPD, HSR, PRP, Shared
Device, Controller Redundancy
IEEE 1588 v2 – Ordinary clock; both peer-to-peer and end-to-end transparent clocks; raw
frames and UDP
Eight independent timer signals synchronized with the IEEE 1588 v2 clock source
o Four timer signals are independently programmable as either timer capture events
or timer output events
o Four timer signals are provided to create programmable periodic waveforms
synchronized to the 1588 clock
DCP, LLDP, DHCP, RSTP, VLAN, IGMP Snooping support
Forwarding table with aging and learning
Ability to drive LEDs for link activity
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2.
February 5, 2014
Packages, Pin Assignments, and Physical Dimensions
The fido5000 REM Switch is available in a 324-pin Ultra-fine Ball Grid Array (UBGA)
package. Its companion memories, the fido0100 and fido0200, are available in a V-PDFN-8
package. The following sections define the pin assignments, signal descriptions and package
dimensions for each device.
2.1
324-Pin Ultra-fine Ball Grid Array (UBGA) Package
2.1.1
Pin Assignments and Signal Descriptions
The fido5000 UBGA ball grid is shown in Figure 3 and is color coded to define the different
types of I/O, power, and ground connections. The grid is further divided into four quadrants,
Northwest, Northeast, Southeast, and Southwest, to clearly define the pin assignments and signal
names. The Northwest Quadrant is shown in Figure 4, the Northeast Quadrant in Figure 5, the
Southeast Quadrant in Figure 6, and the Southwest Quadrant in Figure 7.
NW Quadrant
1
2
NE Quadrant
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
T
T
U
U
V
V
1
2
3
4
5
6
7
8
9
VCC+1V1
VCC+3V3
VCC+2V5A
VCC+2V5D
GND
IO
Configuration
DNU
10 11 12 13 14 15 16 17 18
SW Quadrant
SE Quadrant
Figure 3 – REM Switch UBGA Ball Grid Definition
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NW Quadrant
A
1
2
V_REF
_TTL
DNU
B
DNU
D29
D30
D14
C
D15
D
D31
E
Timer0
Timer1
F
Timer3
Timer4
G
Int0
J
Int1
4
5
6
7
D28
D12
D11
D26
D13
D27
+2V5D
CF_
Config_n
Timer6
H
3
Timer2
D10
CF_
Done_n
Timer5
D24
D25
CF_Stat_n
D09
DNU
DNU
Reset_n
9
DNU
CF_CE_n
DNU
8
DNU
DNU
XTAL0
CS_n
Timer7
Int2
DNU
CF_Msel0
Figure 4 – REM Switch Northwest Quadrant Signal Assignments
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NE Quadrant
10
11
12
D08
D23
D07
D22
DNU
DNU
14
15
16
17
D06
D19
D02
D17
D01
D21
D03
D18
D05
DNU
13
D20
DNU
D04
D00
B
P2_Link_
Status_n
P2_
Activity_n
C
P2_RXD7
P2_RXD6
D
P2_RXD5
E
DNU
DNU
DNU
P2_RXD4
DNU
XTAL1
P2_RXCL
K
DNU
P2_TXCL
K
DNU
DNU
DNU
P2_RXD2
DNU
DNU
A
D16
DNU
DNU
18
P2_RXD0
P2_CRS
F
P2_RXDV P2_RXD3
G
P2_RXD1
CLKOUT
H
DNU
J
Figure 5 – REM Switch Northeast Quadrant Signal Assignments
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MBS
DNU
Endianness
DNU
DNU
DNU
P2_TXD5
P2_TXD6
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
P1_TXD7
10
DNU
February 5, 2014
11
Size_32
DNU
P1_RXCL
K
DNU
DNU
P1_RXD1
P1_TXCL
K
P1_RXD0
DNU
P1_COL
12
13
DNU
DNU
P2_TXD3
DNU
P2_TXD1
DNU
P1_RXD7
P1_RXD2 P1_RXDV
14
P2_TXEN
P1_RXD5
P1_RXD3
P1_CRS
P1_RXD4
15
16
17
P2_TXD7
K
L
P2_TXD4
M
P2_COL
N
P2_TXD2
P
P2_TXD0
R
T
P1_RXD6
U
V
18
SE Quadrant
Figure 6 – REM Switch Southeast Quadrant Signal Assignments
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K
A03
A02/ALE
L
A05
A04
DNU
DNU
N
DNU
DNU
DNU
R
WE_n
DNU
T
OE_n
DNU
V
DNU
DNU
DNU
PGM_
Data3
CF_TDI
PGM_
CS_n
DNU
DNU
DNU
PGM_
Data1
PGM_
Data2
PGM_
Data0
P1_Link_
Status_n
P1_
Activity_n
1
2
3
U
PGM_
DCLK
DNU
M
P
February 5, 2014
DNU
DNU
DNU
DNU
DNU
CF_TMS
DNU
CF_
User_Clk
DNU
DNU
P1_TXD1
P1_TXD3
DNU
P1_TXEN
P1_TXD0
P1_TXD2
DNU
RMII_CLK P1_TXD6
4
5
P1_TXD4
P1_TXD5
GMII_
TXCLK
6
7
8
9
SW Quadrant
Figure 7 – REM Switch Southwest Quadrant Signal Assignments
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The REM Switch signal names corresponding to each ball are defined in the following tables.
Each table details a specific functional area in the part. Within each table, the pins are listed
alphabetically by pin name.
Table 3 – Power Signal Names and Descriptions
Signal Name
GND
Ball
Direction
-
-
Description
Ground – located at:
A3, A8, A18, B1, B11, C4, D2, D3, D5, D7, D12, D15,
D17, E5, E10, F3, F8, F13, G1, G5, G7, G9, G11, H6,
H8. H10, H12, H14, J7, J9, J11, J17, K5, K8, K10, K12,
L6, L7, L9, L11, L18, M1, M6, M12, M13, N4, N9,
N14, P7, P12, P17, R10, T3, T13, U1, V4, V14, V18
Must be pulled to GND through 2.0kΩ +/- 1% resistor
V_REF_TTL
A1
I
VCC+1V1
-
-
1.1V Power Supply located at:
G8, G10, G12, H7, H9, H11, J8, J10, J12, K7, K9, K11,
L8, L10, L12 and M11
VCC+2V5A
-
-
2.5V Analog Power Supply located at:
C10, D14, E6, F5, F15, H3, N5, N15, R6, R14, T10
VCC+2V5D
C5
-
2.5V Digital Power Supply
-
3.3V Power Supply located at:
A13, B6, B13, B16, C7, C9, C14, D8, E7, E13, E15,
E17, F18, G4, G16, H4, H5, H15, J2, J5, K4, K14, K15,
L3, M15, M16, M17, N1, P2, R5, R7, R8, R12, R15,
T6, T8, T18, U6, U10, U11, U16, V5, V9, V11
VCC+3V3
-
The trace from this pin to the pull down resistor should
be routed to avoid any aggressor signals.
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Table 4 – CPU Signal Names and Descriptions
Signal Name
Ball
Direction
Description
Address line 02 when MBS = 0 for Non-Multiplexed
Address Data Bus – bit 2 of the address bus (LSB).
A02/ALE
K2
I
Address Latch Enable when MBS = 1 for Multiplexed
Address Data Bus.
All address lines (A02 through A05) are sampled on the
falling edge of CS_n. The addresses are 32-bit
aligned/addressable.
Address line 03 when MBS = 0 for Non-Multiplexed
Address Data Bus – bit 3 of the address bus
A03/Unused
K1
I
Unused when MBS = 1 for Multiplexed Address Data
Bus.
Address line 04 when MBS = 0 for Non-Multiplexed
Address Data Bus – bit 4 of the address bus
A04/Unused
L2
I
Unused when MBS = 1 for Multiplexed Address Data
Bus.
Address line 05 when MBS = 0 for Non-Multiplexed
Address Data Bus – bit 5 of the address bus
A05/Unused
L1
I
Unused when MBS = 1 for Multiplexed Address Data
Bus.
Data bus bit 00 to/from the REM Switch
D00
B18
I/O
D01
A17
I/O
For all data bits 00 through 31, data is input to the
device when CS_n and WR_n are both low (write
cycle). Data is output from the device when both CS_n
and OE_n are low (read cycle).
Data bus bit 01 to/from the REM Switch
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Signal Name
Ball
Direction
February 5, 2014
Description
Data bus bit 02 to/from the REM Switch when
MBS = 0 for Non-Multiplexed Address Data Bus.
D02/AD02
A15
I/O
AD02 when MBS = 1 for Multiplexed Address Data
Bus – bit 02 of the address (LSB), bit 02 of the data.
Data bus bit 03 to/from the REM Switch when
MBS = 0 for Non-Multiplexed Address Data Bus.
D03/AD03
B14
I/O
AD05 when MBS = 1 for Multiplexed Address Data
Bus – bit 03 of the address, bit 03 of the data.
Data bus bit 04 to/from the REM Switch when
MBS = 0 for Non-Multiplexed Address Data Bus.
D04/AD04
D13
I/O
AD04 when MBS = 1 for Multiplexed Address Data
Bus – bit 04 of the address, bit 04 of the data.
Data bus bit 05 to/from the REM Switch when
MBS = 0 for Non-Multiplexed Address Data Bus.
D05/AD05
C12
I/O
AD05 when MBS = 1 for Multiplexed Address Data
Bus – bit 05 of the address, bit 05 of the data.
D06
A12
I/O
Data bus bit 06 to/from the REM Switch
D07
B10
I/O
Data bus bit 07 to/from the REM Switch
D08
A10
I/O
Data bus bit 08 to/from the REM Switch
D09
B9
I/O
Data bus bit 09 to/from the REM Switch
D10
B7
I/O
Data bus bit 10 to/from the REM Switch
D11
A6
I/O
Data bus bit 11 to/from the REM Switch
D12
A5
I/O
Data bus bit 12 to/from the REM Switch
D13
B4
I/O
Data bus bit 13 to/from the REM Switch
D14
C3
I/O
Data bus bit 14 to/from the REM Switch
D15
C1
I/O
Data bus bit 15 to/from the REM Switch
D16
B17
I/O
Data bus bit 16 to/from the REM Switch
D17
A16
I/O
Data bus bit 17 to/from the REM Switch
D18
B15
I/O
Data bus bit 18 to/from the REM Switch
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Signal Name
Ball
Direction
D19
A14
I/O
Data bus bit 19 to/from the REM Switch
D20
C13
I/O
Data bus bit 20 to/from the REM Switch
D21
B12
I/O
Data bus bit 21 to/from the REM Switch
D22
C11
I/O
Data bus bit 22 to/from the REM Switch
D23
A11
I/O
Data bus bit 23 to/from the REM Switch
D24
A9
I/O
Data bus bit 24 to/from the REM Switch
D25
B8
I/O
Data bus bit 25 to/from the REM Switch
D26
A7
I/O
Data bus bit 26 to/from the REM Switch
D27
B5
I/O
Data bus bit 27 to/from the REM Switch
D28
A4
I/O
Data bus bit 28 to/from the REM Switch
D29
B3
I/O
Data bus bit 29 to/from the REM Switch
D30
C2
I/O
Data bus bit 30 to/from the REM Switch
D31
D1
I/O
Data bus bit 31 to/from the REM Switch
Int0
H1
O
Interrupt 0 output to host processor – can be configured
to respond to one or more internal events
Int1
J1
O
Interrupt 1 output to host processor – can be configured
to respond to one or more internal events
Int2
J3
O
Interrupt 2 output to host processor – can be configured
to respond to one or more internal events
OE_n
T1
I
Output Enable – allows REM Switch to drive data lines
when asserted low
I
Reset – all internal registers are initialized and bus
configuration pins are enabled for sampling when
asserted low
Reset_n
Timer0
F6
E1
I/O
Description
When configured as an input, a low-to-high edge
captures the 1588v2 time.
When configured as an output, the output will toggle
when the 1588v2 time reaches a programmable value.
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Signal Name
Timer1
Timer2
Ball
Direction
E2
E3
I/O
I/O
February 5, 2014
Description
When configured as an input, a low-to-high edge
captures the 1588v2 time.
When configured as an output, the output will toggle
when the 1588v2 time reaches a programmable value.
When configured as an input, a low-to-high edge
captures the 1588v2 time.
When configured as an output, the output will toggle
when the 1588v2 time reaches a programmable value.
When configured as an input, a low-to-high edge
captures the 1588v2 time.
Timer3
F1
I/O
Timer4
F2
O
1588v2-clock-synchronized, programmable pulsewidth-modulated output
Timer5
G3
O
1588v2-clock-synchronized, programmable pulsewidth-modulated output
Timer6
G2
O
1588v2-clock-synchronized, programmable pulsewidth-modulated output
Timer7
H2
O
1588v2-clock-synchronized, programmable pulsewidth-modulated output
WE_n
R1
I
Write Enable – write if set low, read if set high
XTAL0
F9
I
Clock input
XTAL1
F12
O
Clock output – only connected if using a crystal
When configured as an output, the output will toggle
when the 1588v2 time reaches a programmable value.
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Table 5 – Memory Signal Names and Descriptions
Signal Name
Ball
Direction
Description
Address Bus Chip Select – address bus is sampled on
the falling edge of CS_n
CS_n
G6
I
A rising edge on CS_n will terminate the current read
or write cycle.
PGM_CS_n
P3
O
Chip Select from REM Switch to REM Switch memory
– REM Switch Memory is selected when asserted low
PGM_Data0
V1
I
Data bit 0 from REM Switch memory
PGM_Data1
U2
I
Data bit 1 from REM Switch memory
PGM_Data2
U3
I
Data bit 2 from REM Switch memory
PGM_Data3
M5
I
Data bit 3 from REM Switch memory
PGM_DCLK
K6
O
Data clock to receive data from REM Switch memory
Table 6 – Port 1 and Port 2 Signal Names and Descriptions
Signal Name
Ball
Direction
Description
CLKOUT
H18
O
Output clock – same frequency as XTAL0
frequency
GMII_TXCLK
V8
O
125 MHz Transmit clock for GMII Port 1 and 2
P1_Activity_n
V3
O
Port 1 activity LED output driver - LED is on
when asserted low
P1_COL
V13
I
Port 1 MII Collision – a collision has occurred on
port 1 when asserted high
P1_CRS
V16
I
Port 1 MII Carrier Sense – a carrier has been
sensed on Port 1 when asserted high
P1_Link_Status_n
V2
I
Port 1 link status from PHY – when asserted low,
the link on Port 1 is active
P1_RXCLK
T12
I
Port 1 MII Receive Clock from PHY
P1_RXD0
U13
I
Receive data input bit 0 for Port 1 MII/RMII/GMII
P1_RXD1
T14
I
Receive data input bit 1 for Port 1 MII/RMII/GMII
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Signal Name
Ball
Direction
Description
P1_RXD2
U14
I
Receive data input bit 2 for Port 1 MII/GMII
P1_RXD3
V15
I
Receive data input bit 3 for Port 1 MII/GMII
P1_RXD4
V17
I
Receive data input bit 4 for Port 1 GMII
P1_RXD5
U17
I
Receive data input bit 5 for Port 1 GMII
P1_RXD6
U18
I
Receive data input bit 6 for Port 1 GMII
P1_RXD7
T17
I
Receive data input bit 7 for Port 1 GMII
P1_RXDV
U15
I
Port 1 MII Received Data Valid – data from Port 1
PHY is valid when asserted high (used as
CRS/RXDV in RMII mode)
P1_TXCLK
U12
I
Port 1 MII Transmit Clock from PHY
P1_TXD0
U4
O
Transmit data output bit 0 for Port 1
MII/RMII/GMII
P1_TXD1
T4
O
Transmit data output bit 1 for Port 1
MII/RMII/GMII
P1_TXD2
U5
O
Transmit data output bit 2 for Port 1 MII/GMII
P1_TXD3
T5
O
Transmit data output bit 3 for Port 1 MII/GMII
P1_TXD4
V6
O
Transmit data output bit 4 for Port 1 GMII
P1_TXD5
V7
O
Transmit data output bit 5 for Port 1 GMII
P1_TXD6
U9
O
Transmit data output bit 6 for Port 1 GMII
P1_TXD7
V10
O
Transmit data output bit 7 for Port 1 GMII
P1_TXEN
T9
O
Port 1 MII Transmit Enable – transmit is enabled
on Port 1 when high
P2_Activity_n
C18
O
Port 2 activity LED output driver - LED is on
when asserted low
P2_COL
N18
I
Port 2 MII Collision – a collision has occurred on
port 2 when asserted high
P2_CRS
F17
I
Port 2 MII Carrier Sense – a carrier has been
sensed on Port 2 when asserted high
P2_Link_Status_n
C17
I
Port 2 link status from PHY – when asserted low,
the link on Port 2 is active
P2_RXCLK
F14
I
Port 2 MII Receive Clock from PHY
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Signal Name
Ball
Direction
Description
P2_RXD0
J16
I
Receive data input bit 0 for Port 2 MII/RMII/GMII
P2_RXD1
H17
I
Receive data input bit 1 for Port 2 MII/RMII/GMII
P2_RXD2
H16
I
Receive data input bit 2 for Port 2 MII/GMII
P2_RXD3
G18
I
Receive data input bit 3 for Port 2 MII/GMII
P2_RXD4
E16
I
Receive data input bit 4 for Port 2 GMII
P2_RXD5
E18
I
Receive data input bit 5 for Port 2 GMII
P2_RXD6
D18
I
Receive data input bit 6 for Port 2 GMII
P2_RXD7
D16
I
Receive data input bit 7 for Port 2 GMII
P2_RXDV
G17
I
Port 2 MII Received Data Valid – data from Port 2
PHY is valid when asserted high (used as
CRS/RXDV in RMII mode)
P2_TXCLK
G14
I
Port 2 MII Transmit Clock from PHY
P2_TXD0
R18
O
Transmit data output bit 0 for Port 2
MII/RMII/GMII
P2_TXD1
R17
O
Transmit data output bit 1 for Port 2
MII/RMII/GMII
P2_TXD2
P18
O
Transmit data output bit 2 for Port 2 MII/GMII
P2_TXD3
P16
O
Transmit data output bit 3 for Port 2 MII/GMII
P2_TXD4
M18
O
Transmit data output bit 4 for Port 2 GMII
P2_TXD5
L16
O
Transmit data output bit 5 for Port 2 GMII
P2_TXD6
L17
O
Transmit data output bit 6 for Port 2 GMII
P2_TXD7
K18
O
Transmit data output bit 7 for Port 2 GMII
P2_TXEN
N17
O
Port 2 MII Transmit Enable – transmit is enabled
on Port 2 when high
RMII_CLK
U8
O
50 MHz RMII transmit and receive clock for
Port 1 and Port 2
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Table 7 – Bus and Data Configuration Signal Names and Descriptions
Signal Name
Endianness
Ball
Direction
L13
I
Description
System Endianness – Little Endian data format if set
high, Big Endian data format if set low
Value will be captured on rising edge of Reset_n.
MBS
K13
I
Multiplex Bus Select – Host interface bus operates as a
multiplexed bus if set high and a non-multiplexed bus if
set low
Value will be captured on rising edge of Reset_n.
Data Bus Size – 32-bit if set high, 16-bit if set low.
Size_32
N12
I
Value will be captured on rising edge of Reset_n.
Table 8 – Configuration Signal Names and Descriptions
These signals must be connected as described for the REM Switch to operate correctly.
Signal Name
Ball
Direction
Description
CF_CE_n
E4
I
Must be pulled to GND through 10 kΩ resistor
CF_Config_n
D4
I
Must be pulled to VCC+3V3 through 10kΩ resistor
CF_Done_n
C6
I
Must be pulled to VCC+3V3 through 10kΩ resistor
CF_Msel0
J6
I
Must be tied directly to GND
CF_Stat_n
D6
I
Must be pulled to VCC+3V3 through 1kΩ resistor
CF_TDI
N6
I
Must be pulled to VCC+3V3 through 10kΩ resistor
CF_TMS
P6
I
Must be pulled to VCC+3V3 through 10kΩ resistor
CF_User_Clk
M9
I
Must be pulled to GND through 10 kΩ resistor
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Table 9 – No Connect Signal Names and Descriptions
Signal Name
DNU
Ball
Direction
-
-
Description
Do Not Use – located at:
A2, B2, C8, C15, C16, D9, D10, D11, E8, E9, E11,
E12, E14, F4, F7, F10, F11, F16, G13, G15, H13, J4,
J13, J14, J15, J18, K3, K16, K17, L4, L5, L14, L15,
M2, M3, M4, M7, M8, M10, M14, N2, N3, N7, N8,
N10, N11, N13, N16, P1, P4, P5, P8, P9, P10, P11,
P13, P14, P15, R2, R3, R4, R9, R11, R13, R16, T2, T7,
T11, T15, T16, U7, V12
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2.1.2
February 5, 2014
Package Dimensions
The package dimensions are provided in Figure 8. All dimensions are given in millimeters.
Figure 8 – REM Switch Package Dimensions
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2.2
8-Pin V-PDFN-8 Package
2.2.1
Pinout Definition
February 5, 2014
The pin assignments for the REM Switch Memory signals are as shown in Figure 9.
Figure 9 – REM Switch Memory Signal Assignments
The fido0100 and fido0200 REM Switch Memory signal names corresponding to each pin are
defined in Table 10.
Table 10 – Memory Signal Descriptions
Signal Name
PGM_CS_n
Pin
1
Direction Description
I
Chip Select to select REM Switch memory for read
cycle
REM Switch memory is selected when asserted low.
PGM_Data0
5
O
Data bit 0 from REM Switch memory
PGM_Data1
2
O
Data bit 1 from REM Switch memory
PGM_Data2
3
O
Data bit 2 from REM Switch memory
PGM_Data3
7
O
Data bit 3 from REM Switch memory
PGM_DCLK
6
I
Data clock to transmit data from REM Switch
memory
VCC
8
-
+3.3V Power
VSS
4
-
Ground
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2.2.2
February 5, 2014
Package Dimensions
The package dimensions are provided in Figure 10. All dimensions are given in millimeters.
Figure 10 – REM Switch Memory Package Dimensions
3.
Design Considerations
3.1
Power Considerations
The fido5000 requires a 1.1V and a 2.5V power supply. The 1.1V power supply should have its
own power plane on the PCB. The use of a low-noise switching power supply rated to at least
500mA is recommended due the current draw of the REM Switch during programming. Also, it
is recommended to use 0.1 µF bypass capacitors on the REM Switch power pins - one capacitor
for every 2 or 3 power pins.
The 2.5V power supply circuit output must be split into a 2.5V analog power supply and a 2.5V
digital supply. These power supplies should also use a low-noise switching power supply. It is
recommended to isolate these digital and analog power signals with a proper filter and place
them on separate power planes. The planes can be on the same PCB layer but they should be
properly isolated from each other. The 2.5V power supply circuit must be able to supply 200mA
peak at power up.
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The fido0100 and fido0200 require a 3.3V (+/- 10%) power supply with a minimum supply
current of 20 mA. There are no special power considerations for the fido0100 or fido0200
device.
3.2
Reset
The Reset_n signal is typically driven by the host microprocessor that is paired with the REM
Switch. Reset_n is an active low signal and should be pulled high as power becomes valid.
3.3
PHYs
The REM Switch was specifically designed without PHYs because of the different requirements
on PHY performance. EtherCAT and PROFINET IRT have much tighter latency and jitter
requirements than standard Ethernet. For EtherCAT and PROFINET IRT, it is recommended to
use the Renesas UPD60620AGK-0110GAK-SSA-AX PHY. Please refer to the Renesas
Application Note associated with this part number for layout considerations for this PHY.
There are other PHYs that are compatible. Please refer to Table 10 for PHY selection criteria.
3.3.1
Clocking
Most PHYs allow the user to clock the PHY with a crystal oscillator or a separate clock source
when using an MII interface. It is recommended to use the CLKOUT signal from the REM
Switch as the clock source for the PHYs. This approach minimizes jitter as much as possible.
CLKOUT from the REM Switch is a 25 MHz clock signal generated from the 25 MHz input
clock to the REM Switch using the REM Switch’s internal PLL. The PHY uses the 25 MHz
CLKOUT signal to generate the MII RX and TX clock inputs (P1_RXCLK, P1_TXCLK,
P2_RXCLK, P2_TXCLK) to the REM Switch.
For RMII and GMII, the REM Switch generates the required 50 MHz clock for the RMII
interface and the 125 MHz for the GMII interface. These clocks are generated from the 25 MHz
input clock to the REM Switch using the REM Switch’s internal PLL.
As with all clock signals, care should be taken when routing these signals in order to minimize
noise and loading effects.
3.3.2
MDIO
All PHYs require configuration and can provide some type of status information in return. Each
PHY is different, but most PHYs use an MDIO interface to communicate this configuration and
status. The REM Switch does not provide separate communication to the PHYs. The host
processor paired with the REM Switch is required to provide this PHY communication.
Please contact Innovasic technical support if there are questions regarding PHY settings or the
MDIO interface.
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Table 11 – PHY Selection Guide
Protocol
PHY
Requirement
REM
Switch
PHY Device
Broadcom
BCM5221
Renasas
UPD60620
Micrel
KSZ8051
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Auto-Negotiation Suppression
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Auto MDI/MDIX Crossover
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Low transmit latency
Note 1
Note 1
Note 1
<100ns
100ns
37ns
Unknown
Low receive latency
Note 1
Note 1
Note 1
<200ns
165ns
170ns
Unknown
No
Yes
Yes
Yes
Yes
Yes
No
Note 2
Note 2
Note 2
Yes
Yes
Yes
Yes
3.3V I/O
Not specified
Not specified
Not specified
Yes
Yes
Yes
Yes
Industrial temp
Not specified
Not specified
Not specified
Yes
Yes
Yes
Yes
Extended cable length
Not specified
Not specified
Not specified
No
Yes
Yes
No
Cable diagnostics
Not specified
Not specified
Not specified
No
Yes
Yes
Yes
PROFINET
IRT
EtherCAT
SERCOS
III
Link output
Yes
Yes
Yes
100 BaseTX
Yes
Yes
100 BaseFX
No
Auto-Negotiation
Fast link loss detection
MII interface
Note 1:
Latency times are not directly specified in the individual protocol specifications. For high performance systems, it is implied that PHYs should
be chosen with latency times that are as fast as possible. The total latency should be <300ns with the transmit side being <100ns and the
receive side being <200ns.
Note 2:
Use of an MII interface is implied for high performance systems.
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3.4
February 5, 2014
Board Layout
It is recommended to use the following guidelines for board layout with the REM Switch:
Power planes for each of the three supplies should be individual polygons. There should
be at least 0.2 mm of isolation between them.
Clock signals should be isolated from the other traces, and should be as short as possible.
Use equal length traces to the two external PHYs to reduce latency.
A minimum clearance around the REM Switch of 3mm is required to facilitate heat
dissipation.
If the Renesas PHY is used, its internal power supply requires additional board space for
a switching diode and conductor. It is recommended to use a filtering capacitor for the
internal supply with an ESR of 300 milliohms or less.
4.
Device Interfaces
4.1
Oscillator
The REM Switch requires an oscillator as a clocking source. The device does not accept a
crystal as a clock source. The recommended circuit for the 3.3V 25MHz oscillator is shown in
Figure 11 below.
Figure 11 – Example Oscillator Clock Source Circuit
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This clock source is routed to an internal Phase Locked-Loop (PLL) to create the following clock
sources:
25 MHz for CLKOUT reference clock
50 MHz for the RMII reference clock
125 MHz for the GMII reference clock
125 and 250 MHz (internal for the core logic, MACs, and UICs)
4.2
Reset
The timing requirements for Reset_n depend on how the REM Switch is configured to operate
on the Ethernet network. If the REM Switch is configured to run in a 10 Mbit Ethernet network,
the minimum low (active) time for Reset_n is 500 ns. If the REM Switch is configured to run in
a 100 Mbit Ethernet network, the minimum low (active) time for Reset_n is 50ns.
4.3
Timers
4.3.1
Timer0 – Timer3
Timers 0 – 3 can be configured to either timestamp an input event or time-trigger an output
event. When configured to timestamp an input event, the value of the synchronized 1588v2
clock is captured in a 64-bit register when the Timer signal transitions from low to high.
Software can read this register and use the value to timestamp an associated event. For example,
when the Timer0 signal transitions from low to high, the value of the 1588V2 clock is stored in
Timer0’s 64-bit register. The same is true when Timer 1, Timer2, or Timer3 are configured to
timestamp input events. Software can then use the generated timestamp to associate the time
stored in the 64-bit register with a particular event.
When configured to time-trigger an output event, the Timer signal will toggle when the 1588v2
timer reaches the value stored in the 64-bit register. The process of time-triggering an output
event looks like this: host processor software stores a value in Timer0’s 64-bit register, the
1588v2 timer reaches that value, Timer0 toggles from high to low or low to high (depending on
its state when the 64-bit register was loaded). The same process is followed when Timer 1,
Timer2, or Timer3 are configured to time-trigger output events.
4.3.2
Timer4 – Timer7
Timers 4 – 7 can be configured to output independent, 1588v2-clock-synchronized,
programmable pulse-width-modulated signals. Each one of these timers has a resolution of 1ns.
Each Timer can have its own pulse width modulation program that allows 32 rising and falling
edges that repeat on a programmable interval. The software drivers for the REM Switch provide
the capability to define the rising and falling edges for each Timer output.
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4.4
Host Interface
4.4.1
Multiplex Bus Select
February 5, 2014
The Host Interface supports a separate address bus and data bus. In the future, the Host Interface
will support a multiplexed address/data bus. The selection between the two types of busses is
provided by the MBS signal which is sampled on the rising edge of Reset_n. Table 7 provides
the pin description for the MBS signal.
4.4.2
Data Bus Width
The Host Interface supports either a 16-bit or 32-bit wide data bus. The data bus width is
determined by the Size_32 signal which is sampled on the rising edge of Reset_n. Table 7
provides the pin description for the Size_32 signal.
4.4.3
Endianness
The Host Interface will present data on the data bus in either big endian or little endian format.
The endianness of the data is determined by the Endianness signal which is sampled on the rising
edge of the Reset_n signal. Table 7 provides the pin description for the Endianness signal.
4.4.4
Address/Data Bus Operation
The Host Interface address/data bus connects to the CPU’s address/data bus. There are 4-bits of
address for the address bus and either 16-bits or 32-bits of data for the data bus. Each REM
Switch address is 32-bit aligned, meaning that each address provides 32-bits of data. When the
data bus is 32-bits, all 32-bits can be read or written for each address. When the data bus is 16bits, two reads or two writes must be performed for each address.
4.4.4.1 Non-Multiplexed Address Data Bus
When MBS = 0, the non-multiplexed address data bus configuration is selected. The read and
write cycle timing are defined in Figure 12. Table 12 provides the read and write cycle timing
parameters.
4.4.4.2 Multiplexed Address Data Bus
When MBS = 1, the multiplexed address data bus configuration is selected. The read and write
cycle and its timing are defined in Figure 14. Table 13 provides the read and write cycle timing
parameters.
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Figure 12 – REM Switch Non-Multiplexed Address/Data Bus Read Timing
Figure 13 – REM Switch Non-Multiplexed Address/Data Bus Write Timing
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Table 12 – Non-Multiplexed Address Data Bus, Read and Write Cycle Timing Parameters
Symbol
Parameter
Min
tas
Address setup time
0
ns
tah
Address hold time
5
ns
tcdv
Chip select to data valid time
tcsh
Chip select high time
8
ns
teoe
Chip select to output enable time
0
ns
tdo
Output enable to output drive time
1
ns
tdhz
Output disable to high Z time
1
ns
twes
Chip select to write enable
0
ns
twewc
Write enable to write complete
16
ns
twecsi
Write enable high to chip select high
0
ns
twes
Write enable setup time
0
ns
tdh
Data hold time
0
ns
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Max
16
Unit
ns
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Figure 14 – REM Switch Multiplexed Address/Data Bus Read Timing
Figure 15 – REM Switch Multiplexed Address/Data Bus Write Timing
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Table 13 – Multiplexed Address Data Bus, Read and Write Cycle Timing Parameters
4.4.5
Symbol
Parameter
Min
Max
Unit
tLHLL
ALE High Time
8
ns
tLLLH
ALE Low Time
16
ns
tAVLL
Address Valid to ALE Low
2
ns
tLLAX
Address Hold after ALE Low
2
ns
tRLDV
OE_n Low to Data Valid
16
ns
tRHDZ
Data Float after OE_n high
4
ns
tCLLL
CS_n Low to ALE Low
4
ns
tLLRL
ALE Low to OE_n Low
0
ns
tRLRH
Read Pulse Width
16
ns
tWHCH
WR_n High to CS_n High
0
ns
tWLWH
WR_n Pulse Width
16
ns
tWHLH
WR_n High to Next ALE High
0
ns
tOVWH
Data Setup to WR_n High
2
ns
tWHOX
Input Data Hold After WR_n High
2
ns
Register and Data Access
The 4-bits of address provide direct access to 16 registers. A read cycle or a write cycle gets or
sets the data in these registers. Access to additional registers is performed using the Host
Indirect Address Register. The register definitions are provided in Table 14.
The REM Switch software driver provides the necessary Application Programming Interface
(API) functions to access these registers and manage all aspects of the switch for a specific
protocol. Ethernet packets are received and transmitted directly through the Queue 0, Queue 1,
Queue 2, and Queue 3 ead and Write Registers depending on the protocol.
Ethernet protocol control and switch management are performed by the software driver API
through the Host Read Queue Data Register, Host Write Queue Data Head, and the Host Write
Queue Completion Register. Interrupt management is performed by the software driver API
using the three interrupt lines in conjunction with the Queue Status Register, Timer Status
Register, UIC Interrupt Status Register, and the Composite Interrupt Status Register.
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Interrupts
There are three interrupt lines that are outputs from the REM Switch. These three lines are
labeled Int0, Int1 and Int2. Int0 is low priority, Int1 is medium priority, and Int2 is high priority.
Each of these interrupt lines must be mapped accordingly to a processor’s interrupt inputs. Int2
should be given the highest priority in the processor’s priority scheme and should not be disabled
in order to ensure the best protocol performance.
The interrupt lines are mapped to the events defined by the Queue Status Register, Timer Status
Register, UIC Interrupt Status Register, and Composite Interrupt Status Register for each
protocol. It is the responsibility of the software driver API to provide the appropriate interrupt
service routine for the mapped event. Please refer to the REM Switch Driver User’s Guide listed
in Table 2 for technical details on handling REM Switch interrupts for a specific Industrial
Ethernet protocol.
When an interrupt event defined in the appropriate status registers occurs, the associated REM
Switch interrupt output line will become active (logic “1”) and will remain active until the
register is cleared. If multiple events are mapped to the same REM Switch interrupt output and
more than one becomes active, the associated interrupt line will remain in the active (logic “1”)
state until all active interrupt source registers are cleared.
4.5
Ethernet Interface
There are 2 Ethernet ports on the REM Switch. Each port is capable of being configured to
support RMII, MII, or GMII. Each port also has an input for Link Status from the PHY and an
output for a link activity LED.
4.5.1
Connections
The signals associated with the RMII, MII, and GMII interfaces are defined in Table 6. The
RMII interface is a seven signal interface for each port and is detailed in Figure 16 This
interface uses a 50 MHz reference clock (RMII_CLK) provided by the REM Switch to the PHY.
The MII interface is a 14-signal interface for each port and is detailed in Figure 17. The REM
Switch provides the base clock to the PHYs using the synchronized 25 MHz CLKOUT signal.
The PHYs then provide a receive and transmit clock (RX_CLK and TX_CLK) for each port.
The GMII interface is a 21-signal interface for each port and is detailed in Figure 18. This
interface uses a 125 MHz reference clock (GMII_TXCLK) provided by the REM Switch to the
PHY.
4.5.2
Link Status and Activity
The Link_Status signal in an input to the REM Switch from the selected PHY and is used to
determine the Link Up or Link Down state.
The Link_Activity signal is an output from the REM Switch and is typically used to drive an
LED to indicate a link is valid.
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Table 14 – Register Definitions
Register Name
Register
Width
Address
Detail
Reset Value
Queue 0 Read Register
16/32
0x00
Read-only
0x00000000
Queue 0 Write Register
16/32
0x00
Write-only
N/A
Queue 1 Read Register
16/32
0x01
Read-only
0x00000000
Queue 1 Write Register
16/32
0x01
Write-only
N/A
Queue 2 Read Register
16/32
0x02
Read-only
0x00000000
Queue 2 Write Register
16/32
0x02
Write-only
N/A
Queue 3 Read Register
16/32
0x03
Read-only
0x00000000
Queue 3 Write Register
16/32
0x03
Write-only
N/A
Reserved
0x04 - 0x06
Host Read Queue Data Register
16/32
0x07
Read-only
0x00000000
Host Write Queue Data Head
16/32
0x07
Write-only
N/A
Queue Status Register
16
0x08
Read-only
0x7F00
Timer Status Register
16
0x09
Read/Write
0x0000
UIC Interrupt Status Register
16
0x0a
Read/Write
0x0000
Composite Interrupt Status Register
16
0x0b
Read-only
0x0000
Host Indirect Address Register
16
0x0c
Read/Write
0x0000
Host Indirect Read Data Register
16
0x0d
Read-only
N/A
Host Indirect Write Data Register
16
0x0d
Write-only
N/A
Host Write Queue Completion Register
16
0x0e
read-only
0x0000
Reserved
0x0f
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Figure 16 – REM Switch configured for RMII Interface
Figure 17 – REM Switch configured for MII Interface
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Figure 18 – REM Switch configured for GMII Interface
4.6
REM Switch Memory
The REM Switch memory stores the hardware configuration for the REM Switch. It comes preprogrammed according to the part number ordered. All that is required is to connect the 6 signal
lines to the REM Switch as defined in this datasheet and a 3.3V, +/- 10% power supply with a
minimum supply current of 20 mA. Innovasic recommends using a 0.1 µF bypass capacitor
from VCC to ground located as close as possible to the REM Switch memory.
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5.
Absolute Ratings and Operating Conditions
5.1
REM Switch
Absolute Ratings
Parameter
Min
Max
Units
Core voltage and periphery circuitry power supply
–0.5
1.35
V
Configuration pins power supply
–0.5
3.75
V
Auxiliary supply
–0.5
3.75
V
I/O pre-driver power supply
–0.5
3.75
V
I/O power supply
–0.5
3.9
V
PLL analog power supply
–0.5
3.75
V
DC input voltage
–0.5
3.70
V
DC output current per pin
–25
40
mA
Operating junction temperature
–55
125
°C
Storage temperature (No bias)
–65
150
°C
Operating Conditions
Parameter
Min
Typ
Max
Units
Core voltage
1.07
1.1
1.13
V
Auxiliary supply
2.375
2.5
2.625
V
I/O buffers (3.3 V) power supply
3.135
3.3
3.465
V
PLL analog voltage regulator power supply
2.375
2.5
2.625
V
DC input voltage
–0.5
—
3.6
V
0
—
3.465
V
–40
—
100
°C
Output voltage
Operating junction temperature – Industrial
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REM Switch Memory
Absolute Ratings
Parameter
Min
Max
Units
Storage temperature
–65
150
°C
–
See note 1
°C
VCC Supply voltage
–0.6
4.0
V
Input/output voltage with respect to ground
–0.6
VCC + 0.6
V
–2000
2000
V
Lead temperature during soldering
Electrostatic discharge voltage (human body model)
Note 1 – Compliant with JEDEC Standard J-STD-020C (for small-body, Sn-Pb or Pb assembly), RoHS,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Operating Conditions
Parameter
Min
Max
Units
Supply voltage
2.7
3.6
V
Ambient operating temperature
–40
85
°C
6.
DC Specifications
6.1
REM Switch
I/O
Standard
3.3V
LVCMOS
6.2
VCCIO (V)
VIL (V)
VIH (V)
VOL
(V)
VOH
(V)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
3.135
3.3
3.465
-0.3
0.8
1.7
3.6
0.2
3.1
IOL
(mA)
IOH
(mA)
2
-2
Pin Capacitance
Description
Value
Unit
Input capacitance on top and bottom I/O pins
5.5
pF
Input capacitance on left and right I/O pins
5.5
pF
Input capacitance on dual-purpose clock output and feedback pins
5.5
pF
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Leakage Current
Description
Conditions
Min
Typ
Max
Unit
Input pin
VI = 0V to VCCIOMAX
-30
--
30
µA
Tri-stated I/O pin
VO = 0V to VCCIOMAX
-30
--
30
µA
7.
AC Specifications
7.1
Bus Hold Parameters
Parameter
Conditions
Min
Max
Units
Bus-hold, low, sustaining current
VIN > VIL (max)
70
--
µA
Bus-hold, high, sustaining current
VIN < VIH (min)
-70
--
µA
Bus-hold, low, overdrive current
0V < VIN < VCCIO
--
500
µA
Bus-hold, high, overdrive current
0V < VIN < VCCIO
--
-500
µA
--
0.8
2
V
Bus-hold trip point
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pa
8.
Revision History
Date
Revision
Description
Page(s)
June 21, 2013
0
Initial Release
All
August 12, 2013
1
Updated signal names and improved signal name
table by separating table into functional sections
August 19, 2013
2
Corrected P2_TXD5, P2_TXD6, P2_TXD7 pin
names
3
Added sections:
3. Device Interfaces
4. Maximum Ratings, Thermal Characteristics,
and DC Parameters
5. AC Specifications
From page 27
4
Updated address/data bus timing diagrams,
updated section 4.4.6 (Interrupts), added
information for bus hold parameters, bus timing
waveforms, pin capacitances and leakage current
36-38, 40, from
page 44
November 25, 2013
February 5, 2014
9.
9, 12 – 24, 26
22
For Additional Information
The Innovasic Support Team wants its information to be complete, accurate, useful, and easy to
understand. Please feel free to contact experts at Innovasic with suggestions, comments, or
questions at any time.
Innovasic Support Team
5635 Jefferson St. NE, Suite A
Albuquerque, NM 87109 USA
Phone: +1-505-883-5263 (International)
Fax: +1 (505) 883-5477
Toll Free: (888) 824-4184 (In US)
E-mail: [email protected]
Website: http://www.Innovasic.com
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