RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5256DFP,VP is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is f abricated using high-perf ormance 3 poly silicon CMOS technology . The use of resistiv e load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough f or battery back-up application. It is ideal f or the memory sy stems which require simple interf ace. Especially the M5M5256DVP are packaged in a 28-pin thin small outline package. FEATURE Access Oprating Power supply current time Temperature Activ e Stand-by (max) (max) (max) Ty pe M5M5256DFP,VP-55LL 55ns 20µA 0~70°C M5M5256DFP,VP-70LL M5M5256DFP,VP-70LLI (Vcc= 5.5V) 70ns 70ns -40~85°C 50mA 40µA (Vcc= 5.5V) (Vcc= 5.5V) 5µA M5M5256DFP,VP-55XL M5M5256DFP,VP-70XL (Vcc= 5.5V) 55ns 70ns 0~70°C •Single +5V power supply •No clocks, no ref resh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •/OE prev ents data contention in the I/O bus •Common Data I/O •Battery backup capability •Low stand-by current .......... 0.05µA(ty p.) 0.05µA (Vcc= 3.0V, Typical) PIN CONFIGURATION (TOP VIEW) A14 A12 1 28 2 A7 A6 A5 A4 3 27 26 4 25 A3 A2 A1 A0 DQ1 DQ2 7 A13 A8 24 A9 23 A11 22 /OE 8 21 9 20 5 6 16 A10 /S DQ8 DQ7 DQ6 DQ5 15 DQ4 10 19 11 18 12 17 13 DQ3 GND 14 Outline 28P2W-C (FP) 22 /OE 23 A11 24 A9 25 A8 26 A13 27 /W 28 Vcc 1 A14 2 A12 M5M5256DVP 3 A7 4 A6 5 A5 6 A4 7 A3 Outline Vcc /W A10 21 /S 20 DQ8 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 GND 14 DQ3 13 DQ2 12 DQ1 11 A0 10 A1 9 A2 8 28P2C-A (VP) PACKAGE M5M5256DFP M5M5256DVP : 28 pin 450 mil SOP 2 : 28pin 8 X 13.4 mm TSOP APPLICATION Small capacity m emory units 1 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5256DFP,VP is determined by a combination of the dev ice control inputs /S, /W and /OE. Each mode is summarized in the f unction table. A write cy cle is executed whenev er the low lev el /W ov erlaps with the low lev el /S. The address must be set up bef ore the write cy cle and must be stable during the entire cy cle. The data is latched into a cell on the trailing edge of /W, /S, whichev er occurs f irst, requiring the setup and hold time relativ e to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high lev el,the output stage is in a high-impedance state, and the data bus contention problem in the write cy cle is eliminated. A read cy cle is executed by setting /W at a high lev el and /OE at a low lev el while /S are in an activ e state. When setting /S at a high lev el, the chip is in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specif ied as Icc3 or Icc4, and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the nonselected mode. FUNCTION TABLE /S /W /OE Mode DQ Icc H X X Non selection High-impedance Stand-by L L X Write D IN Activ e L H L Read D OUT Activ e High-impedance Activ e L H H Note • "H" and "L" in this table mean VIH and VIL, respectiv ely . • "X" in this table should be "H" or "L". BLOCK DIAGRAM ADDRESS INPUT A8 25 A 13 26 A 14 1 A 12 22 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 A 10 21 A 11 23 A9 24 WRITE CONTROL INPUT /W 27 CHIP SELECT INPUT 20 /S OUTPUT ENABLE /OE INPUT 22 32768 WORD X 8BIT 11 DQ1 12 DQ2 13 DQ3 15 DQ4 16 DQ5 17 DQ6 18 DQ7 19 DQ8 28 VCC (5V) 14 GND (0V) (512 ROWS X 512 COLUMNS) DATA I/O CLOCK GENERATOR 2 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage Vcc VI VO Pd Input voltage Output voltage Power dissipation T opr Operating temperature T stg Storage temperature Ratings -0.3 * ~7.0 -0.3 * ~Vcc+0.3 Conditions With respect to GND Unit V (Max 7.0) V 0~Vcc 700 0~70 -40~85 -65~150 V mW Ta=25°C -LL,-XL -LLI °C °C _ 30ns ) * -3.0V in case of AC ( Pulse width < DC ELECTRICAL CHARACTERISTICS Symbol ( Vcc=5V±10%, unless otherwise noted) Parameter Limits Test conditions V IH High-level input voltage Min 2.2 V IL Low-level input voltage -0.3* V OH1 Typ Max Vcc +0.3 0.8 Unit V V High-level output voltage 1 IOH=-1mA 2.4 V V OH2 High-level output voltage 2 IOH=-0.1mA Vcc -0.5 V V OL Low-level output voltage IOL=2mA II Input current IO Icc1 Icc2 V I =0 ~ Vcc 0.4 ±1 µA Output current in off-state /S=V IH or or /OE=V IH, V I/O =0 ~ Vcc ±1 µA 55ns _ /S<0.2V, Other inputs<0.2V or >Vcc-0.2V 70ns Output-open 1MHz 30 45 Active supply current 25 40 2 4 55ns 30 50 70ns 25 45 1MHz 4 8 (AC, MOS lev el ) Active supply current (AC, TTL lev el ) /S=V IL, other inputs=VIH or V IL Output-open ~25°C Icc3 Stand-by current _ /S>Vcc-0.2V, other inputs=0~Vcc ~40°C ~70°C ~85°C Icc4 Stand-by current -LL,-LLI V mA mA 2 -XL 0.1 0.4 -LL,-LLI 6 -XL 1.2 -LL,-LLI 20 -XL 5 -LLI 40 /S=V IH,other inputs=0~ Vcc 3 µA mA * -3.0V in case of AC ( Pulse width <_ 30ns ) CAPACITANCE Symbol CI CO ( Vcc=5V±10%, unless otherwise noted) Parameter Input capacitance Output capacitance Test conditions V I =GND, V I =25mVrms, f=1MHz V O =GND,V O =25mVrms, f=1MHz Min Limits Typ Max 6 8 Unit pF pF Note 0: Direction f or current f lowing into an IC is positiv e (no mark). 1: Ty pical v alue is one at Ta = 25°C. 2: C I , C O are periodically sampled and are not 100% tested. 3 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted ) (1) READ CYCLE Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after /S high Output disable time after /OE high Output enable time after /S low Output enable time after /OE low Data valid time after address Limits -70LL,-70LLI, -55LL, 55XL -70 XL Min Max Max Min 70 55 70 55 55 70 35 30 25 20 25 20 5 5 5 5 10 10 Unit ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to /W high Chip select setup time Data setup time Data hold time Write recovery time Output disable time from /W low Output disable time from /OE high Output enable time from /W high Output enable time from /OE low Limits -70LL,-70LLI, -55LL, -55XL -70 XL Min Max Min Max 55 70 40 50 0 0 50 65 50 65 25 30 0 0 0 0 25 20 25 20 5 5 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns 4 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM (3) TIMING DIAGRAMS Read cycle tCR A 0~ 14 ta(A) tv (A) ta (S) /S (Note 3) ta (OE) tdis (S) (Note 3) tdis (OE) (Note 3) ten (OE) /OE (Note 3) ten (S) DATA VALID DQ1~ 8 /W = "H" lev el Write cycle (/W control mode) tCW A 0~ 14 t su (S) /S (Note 3) (Note 3) tsu (A-WH) /OE tsu (A) tw (W) trec (W) /W tdis (W) tdis (OE) ten (W) ten(OE) DATA IN STABLE DQ1~ 8 (Note 3) (Note 3) tsu (D) th (D) 5 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM Write cycle ( /S control mode) tCW A 0~ 14 tsu (A) tsu (S) trec (W) /S (Note 5) /W (Note 4) (Note 3) th (D) DATA IN STABLE DQ1~ 8 Note 3 4 5 6 7 (Note 3) tsu (D) : : : : : Hatching indicates the state is "don't care". Writing is executed in ov erlap of /S and /W low. If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state. Don't apply inv erted phase signal externally when DQ pin is output mode. ten, tdis are periodically sampled and are not 100% tested. (4) MEASUREMENT CONDITIONS Input pulse level .............. V IH=2.4V,V IL=0.6V Input rise and fall time ..... 5ns Reference level ................ V OH=V OL=1.5V Output load ...................... Fig.1 CL=50pF (-55LL,-55XL ) CL=100pF (-70LL,-70LLI,-70XL ) CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) Vcc 1.8k Ω DQ 990Ω CL (Including scope and JIG) Fig.1 Output load 6 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc (PD) VI (/S) ( Vcc=5V±10%, unless otherwise noted) Parameter Test conditions Min 2 Power down supply v oltage _ VCC(PD) 2.2V < _ VCC(PD) < _ 2.2V 2V< Chip select input /S (PD) Power down supply current _ Vcc -0.2V, Vcc = 3V, /S > Other inputs=0~Vcc Max V VCC(PD) ~40°C Unit V 2.2 V 1 -LL,-LLI ~25°C -XL Icc Limits Typ 0.05 -LL,-LLI -XL 0.2 3 0.6 µA 10 2 -LL,-LLI ~70°C -XL -LLI ~85°C 20 (2) TIMING REQUIREMENTS ( Vcc=5V±10%, unless otherwise noted ) Symbol tsu (PD) trec (PD) Parameter Test conditions Min Limits Typ Max ns ns 0 Power down set up time Power down recov ery time Unit tCR (3) POWER DOWN CHARACTERISTICS /S control mode Vcc tsu (PD) 4.5V 4.5V 2.2V 2.2V /S trec (PD) _ Vcc - 0.2V /S > 7 RENESAS LSIs M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! · Renesas T echnology Corporation puts the m axim um effort int o m a k ing sem iconductor products better and more reliable, but there is always the possibility that trouble m ay occur with them . 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New publication, effective Feb 2004. Specifications subject to change without notice