HD74LS122 Retriggerable Monostable Multivibrator (with Clear) REJ03D0428–0200 Rev.2.00 Feb.18.2005 This d-c triggered multivibrator features output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. The HD74LS122 has internal timing resistor that allows the circuit to be used with only an external capacitor, if so desired. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-level active (B) inputs or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear. This device is provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 mV/ns. A = "L" Clear = "H" Retrigger Pulse "H" B "L" tw + tPLH "H" Q tw "L" Output without retrigger A = "L" "H" B "L" "H" Clear "L" "H" Q "L" Output without clear Figure 1 Rev.2.00, Feb.18.2005, page 1 of 7 Typical Input / Output Pulse HD74LS122 Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS122P DILP-14 pin PRDP0014AB-B (DP-14AV) P — PRSP0014DF-B FP (FP-14DAV) Note: Please consult the sales office for the above package availability. HD74LS122FPEL SOP-14 pin (JEITA) EL (2,000 pcs/reel) Pin Arrangement A1 1 14 VCC A2 2 13 Rext/Cext B1 3 12 NC B2 4 11 Cext CLR 5 CLR 10 NC Q 6 Q 9 Rint GND 7 8 Q Q (Top view) Function Table Inputs Clear A1 A2 L X X X H H X X X X X X H L X H L X H X L H X L H H ↓ H ↓ ↓ H ↓ H ↑ L X ↑ X L Notes: H; high level, L; low level, X; irrelevant ↑; transition from low to high level ↓; transition from high to low level ; one high-level pulse ; one low-level pulse Rev.2.00, Feb.18.2005, page 2 of 7 Outputs B1 X X L X ↑ H ↑ H H H H H H B2 X X X L H ↑ H ↑ H H H H H Q L L L L Q H H H H HD74LS122 Block Diagram External parameter Cext Rect /Cext A1 A2 Rint Q Q Q Q B1 B2 CLR Clear Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Item VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Topr –20 25 75 °C tw 40 — — ns External timing resistance Rext 5 — 260 kΩ External capacitance Cext 50 pF Supply voltage Output current Operating temperature Input pulse width Wiring capacitance at Rext/Cext terminal Rev.2.00, Feb.18.2005, page 3 of 7 Rext/Cext Non restriction — — HD74LS122 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 Output voltage VOL Input current IIH IIL II V µA mA mA Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, V IL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V Short-circuit output –20 — –100 mA VCC = 5.25 V IOS current Supply current** ICC — 6 11 mA VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA * VCC = 5 V, Ta = 25°C ** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. Note: To measure VOH at Q, VOL at Q, or IOS at Q, ground Rext / Cext, apply 2 V to B and clear, and pulse A from 2 V to 0 V. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Propagation delay time Output pulse width Symbol tPLH tPHL tPLH tPHL tPLH tPHL t(out)min Inputs t(out) Rev.2.00, Feb.18.2005, page 4 of 7 A B Clear A or B Outputs Q Q Q Q Q Q Q Q min. — — — — — — — 4 typ. 23 32 23 34 20 28 116 4.5 max. 33 45 44 56 27 45 200 5 Unit Condition ns Cext = 0, Rext = 5 kΩ, CL = 15 pF, RL = 2 kΩ µs Cext = 1000 pF, Rext = 10 kΩ, CL = 15 pF, RL = 2 kΩ HD74LS122 Typical Application Data for HD74LS122 For pulse widths when Cext ≤ 1000 pF, See Figure 3. The output pulse is primarily a function of the external capacitor and resistor. For Cext > 1000 pF, the output pulse width (tw) is defined as: tw(out) = K • Rext • Cext; See Figure 4. VCC Rext + – Cext Rext (kΩ) Cext (pF) tw(out) (ns) to Cext Figure 2 to Rext/Cext Timing Component Connections Output pulse width tw (ns) 100,000 Rext = 160kΩ 10,000 1,000 Rext = 80kΩ 40kΩ 20kΩ 10kΩ 5kΩ 100 10 1 10 100 1,000 External capacitance Cext (pF) Typical Output Pulse Width (Cext ≤ 1000 pF) Figure 3 A coefficient of output pulse width K 0.5 0.4 0.3 0.2 VCC = 5V Ta = 25°C 0.1 0 103 2 3 5 7104 2 3 5 7105 2 3 5 7106 2 3 Timing capacitance Cext (pF) Figure 4 Rev.2.00, Feb.18.2005, page 5 of 7 Cext vs. K (Cext > 1000 pF) 5 7107 HD74LS122 Testing Method Test Circuit VCC Output Q Cext A1 Input Rext 4.5V P.G. Zout = 50Ω Cext Rext /Cext VCC RL Load circuit 1 Q CL B1 Input P.G. Zout = 50Ω Output Q Q CLR Input Same as Load Circuit 1. CLR P.G. Zout = 50Ω H2 Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveform tw (in) A 3V ≥ 40ns 1.3V 1.3V 1.3V tw (in) 0V ≥ 40ns tw (in) B 1.3V 3V ≥ 40ns 1.3V 1.3V tw (in) 0V ≥ 40ns tw (CLR) 3V ≥ 40ns Clear 1.3V 1.3V 0V tPLH tPLH VOH 1.3V Q 1.3V 1.3V 1.3V VOL tPHL tw (out) tPLH Q 1.3V tw (out) 1.3V 1.3V VOH 1.3V VOL tPHL Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns. Rev.2.00, Feb.18.2005, page 6 of 7 tPHL HD74LS122 Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B MASS[Typ.] 0.97g Previous Code DP-14AV D 8 E 14 1 7 b3 Z A1 A Reference Symbol Nom e1 7.62 D 19.2 E 6.3 L A θ bp e Dimension in Millimeters Min e1 A1 0.51 bp 0.40 JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B *1 Previous Code FP-14DAV D 0.48 0.56 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 2.39 L 2.54 MASS[Typ.] 0.23g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 7.4 1.30 Z ( Ni/Pd/Au plating ) 20.32 5.06 b3 c Max 8 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 Nom Max D 10.06 10.5 E 5.50 A2 7 e A1 bp Dimension in Millimeters Min x M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 1.42 Z L L Rev.2.00, Feb.18.2005, page 7 of 7 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0