12V Wireless Power Transmitter IC for TX-A6 Product Datasheet IDTP9036A Features Description 5W Solution for Wireless Power Consortium (WPC)-Compliant Power Transmitter Design TX-A6 Conforms to WPC Specification Version 1.1 Specifications Reduced EMI To Meet Requirements of WPC 1.1 Certification 12V Operating Input Voltage Closed-Loop Power Transfer Control Between Base Station and Mobile Device Demodulates and Decodes WPC-Compliant Message Packets 5V Regulated DC/DC Converter Integrated RESET Function Proprietary Back-Channel Communication I2C Interface Open-Drain LED Indicator Outputs Over-Temperature Protection Security and Encryption up to 64 bits Foreign Object Detection (FOD) The IDTP9036A is a highly-integrated WPC-compliant wireless power transmitter IC for power transmitter WPC design TX-A6. The device operates with a 12V adaptor, and drives an external half-bridge inverter for DC/AC conversion. It controls the transferred power by modulating the switching frequency of the half-bridge inverter from 115kHz to 205kHz at a fixed 50% duty cycle as specified by the WPC specification for an “A6” transmitter. It contains logic circuits required to demodulate and decode WPC-compliant message packets sent by the mobile device to adjust the transferred power. The IDTP9036A is an intelligent device which manages mobile device detection, and then the selection of one section of the triple A6 coil without user supervision. The A6 configuration allows free mobile device positioning over a wider area than configurations that use a single coil, detecting a mobile device for charging while minimizing idle power. Once the mobile device is detected and authenticated, the IDTP9036A continuously monitors all communications from the mobile device, and adjusts the transmitted power accordingly by varying the switching frequency of the half-bridge inverter. The IDTP9036A features a proprietary back-channel communication mode which enables the device to communicate with IDT’s wireless power receiver solutions (e.g. IDTP9020). This feature enables additional layers of capabilities beyond the standard WPC requirements. This device also features optional security and encryptions to securely authenticate the receiver before transferring power. This feature is available when an IDTP9020 is used for the receiver. Applications Wireless Interface Transmitter(s) Mobile Device Receiver Control Control System Comm Cont Sensing Control Comm DeMod Comm Load Reflection Power Generation IN PWR Typical Application Circuit Control System Cont Sensing Control Mod Power Pick-Up Induction Output Load Base Station Input Power The IDTP9036A includes over-temperature/current protection and a Foreign Object Detection (FOD) method to protect the base station and mobile device from overloading in the presence of a metallic foreign object. It manages fault conditions associated with power transfer and controls status LEDs to indicate operating modes. WPC-Compliant Wireless Charging Base Stations (See page 2) Out PWR Package: 6x6-48 TQFN (See page 31) Ordering Information (See page 32) Revision 1.0.6 1 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet SIMPLIFIED APPLICATION DIAGRAM BUCK5VT LDO2P5V 100 0.1uF 22K 4.7K + c 3.92K 100 - ISNS 3.3K 0.1uF + 0.1uF 100K 240 0.1uF - 0.02 4.7nF 6.8K 100pF 44uF (2x22uF) D 100 Q 330 Q IDTP9090 10 33nF 10 10K 0.1uF 10 330 0.1uF 15nF 47nF 0.33 47nF 11.5u GPIO_0 ADAPTOR REG_IN IC3 GPIO_6 BUCK5VT_IN 12.5u 1.5K 10uF BUCK5VT LDO2P5V_IN IC4 GPIO_5 1uF 22nF 10K 3.3nF 10K 0.1uF 422 4.7K LEDA 22nF 10K 3.3nF 10K 4.7K 11.5u 1.5K GPIO_4 Buzzer 33nF 15K 15K GPIO_3 47K LEDB ISNS 8 7 6 5 47K 2.7K HPF 22nF 10K 3.3nF 15K 10K ISNS 10K 6.8nF 1nF WP SCL SDA 1.5K 10K PGND 2.7K 1 2 3 4 3.3nF VOSNS 10K 0.1uF 4.7K IDTP9036A 47K GPIO_1 SCL SDA __ EN BUCK5VT_SNS BUCK5VT 4.7uH LX RESET RESET 100K BST LDO5V LDO2P5V GND GPIO_2 EP IC5 REFGND AGND DGND 10uF 47nF LDO5V LDO2P5V 1uF 1uF 100K Figure 1. IDTP9036A Simplified Application Schematic Revision 1.0.6 2 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet ABSOLUTE MAXIMUM RATINGS These absolute maximum ratings are stress ratings only. Stresses greater than those listed below (Table 1 and Table 2) may cause permanent damage to the device. Functional operation of the IDTP9036A at absolute maximum ratings is not implied. Application of the absolute maximum rating conditions affects device reliability. Table 1. Absolute Maximum Ratings Summary. All voltages are referred to ground, unless otherwise noted. PINS RATING UNITS BUCK5VT_IN, REG_IN (THESE PINS MUST BE CONNECTED TO GETHER AT ALL TIMES.) -0.3 to 24 V 0 V -0.3 to VIN+0.3 V -0.3 to VIN+5 V LDO2P5V -0.3 to 2.75 V AGND, DGND, PGND, REFGND -0.3 to +0.3 V BUCK5VT_SNS, BUCK5VT, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, HPF, ISNS, LDO2P5V_IN, LDO5V, RESET, SCL, SDA, VOSNS -0.3 to +6.0 V IN, SW (THESE PINS MUST BE LEFT UNCONNECTED (OPEN) AT ALL TIMES.) , LX BST Table 2. Package Thermal Information SYMBOL DESCRIPTION RATING UNITS JA Thermal Resistance Junction to Ambient (NTG48 - TQFN) 30.8 C/W JC Thermal Resistance Junction to Case (NTG48 - TQFN) 14.6 C/W JB2 Thermal Resistance Junction to Board (NTG48 - TQFN) 0.75 C/W TJ Junction Operating Temperature -40 to +125 C TA Ambient Operating Temperature -40 to +85 C TSTG Storage Temperature -55 to +150 C TLEAD Lead Temperature (soldering, 10s) +300 C Note 1: The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is 125°C, the maximum junction operating temperature. Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. Note 2: This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions. Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. Note 4: For the NTG48 package, connecting the 4.1 mm X 4.1 mm EP to internal/external ground planes with a 5x5 matrix of PCB plated-through-hole (PTH) vias, from top to bottom sides of the PCB, is recommended for improving the overall thermal performance. Revision 1.0.6 3 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Table 3. ESD Information TEST MODEL PINS HBM All ±2000 V CDM All ±500 V Revision 1.0.6 RATINGS 4 UNITS © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet ELECTRICAL CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. IN = SW = Open. TA = -40 to +85C, unless otherwise noted. Typical values are at 25C, unless otherwise noted. Table 4. Device Characteristics SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNITS 11.4 12 12.6 V External Half-Bridge Inverter VIN IIN_A IIN2 IIN_S FSW_LOW FSW_HIGH Input Supply Operating Voltage Range1 Standby Input Current Sleep Mode Input Current 24 460 = 5V to VIN Switching Frequency at SW WPC-compliant Operating Range Under-Voltage Protection Trip Point VIN rising VIN falling Hysteresis mA 600 µA 205 kHz kHz 115 UVLO VIN_UVLO 10.3 9.0 625 V mV DC-DC Converter (For Biasing Internal Circuitry Only) 3 VBUCK5VT_IN VBUCK5VT IOUT5 FSW Input Voltage Range1 Output Voltage External Load Switching Frequency at LX 11.4 External ILoad = 8mA 4.5 5 12.6 V 5.5 8 V mA 1.5 MHz 5 2.5 V V mA Low Drop Out Regulators (For Biasing Internal Circuitry Only)3 LDO2P5V3 VLDO2P5V_IN VLDO2P5V IOUT Input Voltage Range Output Voltage External Load Supplied from BUCK5VT ILoad = 2mA Input Voltage Range Output Voltage See Note 1. ILoad = 2mA 8 LDO5V3 VREG_IN VLDO5V 11.4 12.6 5 V V Thermal Shutdown TSD Revision 1.0.6 Thermal Shutdown Temperature Rising Threshold Temperature Falling Threshold 5 140 110 C © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet ELECTRICAL CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. IN = SW = Open. TA = -40 to +85C, unless otherwise noted. Typical values are at 25C, unless otherwise noted. Table 4. Device Characteristics, Continued SYMBOL DESCRIPTION CONDITIONS MIN VIH VIL IEN ¯¯ EN ¯¯ input current TYP MAX UNITS 900 550 mV mV VEN ¯¯ = 5V 7.5 μA VEN ¯¯ = VIN = 12.6V 35 μA General Purpose Inputs / Outputs (GPIO) VIH VIL ILKG VOH VOL IOH IOL Input Threshold High Input Threshold Low Input Leakage Output Logic High Output Logic Low Output Current High Output Current Low 3.5 8 1.5 +1 V V µA 1.5 +1 -1 4 IOH=-8mA IOL=8mA V V µA V V mA mA 0.5 -8 RESET VIH VIL ILKG SCL, SDA Input Threshold High Input Threshold Low Input Leakage (I2C Clock Frequency fSCL Clock Frequency fSCL Clock Frequency Hold Time (Repeated) for START Condition tHD;DAT Data Hold Time tLOW tHIGH Clock Low Period Clock High Period Set-up Time for Repeated START Condition tSU;STA Revision 1.0.6 -1 Interface) fSCL tHD;STA 3.5 EEPROM loading, Step 1, IDTP9036A as Master EEPROM loading, Step 2, IDTP9036A as Master IDTP9036A as Slave I2C-bus devices 6 0 100 kHz 300 kHz 400 kHz 0.6 μs 10 ns 1.3 0.6 μs μs 100 ns © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet ELECTRICAL CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. IN = SW = Open. TA = -40 to +85C, unless otherwise noted. Typical values are at 25C, unless otherwise noted. Table 4. Device Characteristics, Continued SYMBOL DESCRIPTION Bus Free Time Between STOP and START Condition Capacitive Load for CB Each Bus Line SCL, SDA Input CBIN Capacitance5 VIL Input Threshold Low VIH Input Threshold High ILKG Leakage Current Output Logic Low VOL (SDA) IOH Output Current High IOL Output Current Low Analog-to-Digital Converter ADC Conversion N Resolution fSAMPLE Sampling Rate Number of Channels Channel at ADC MUX input ADC Clock ADCCLK Frequency Full-Scale Input VIN_FS Voltage CONDITIONS MIN tBUF TYP MAX 1.3 μs 100 5 When powered by device 5V UNITS pF pF 1.5 3.5 V V -1.0 IPD= 2mA (Note 1) 1.0 µA 0.5 V 2 mA mA -2 12 Bit 62.5 kSPS 8 1 MHz 2.39 V 40 MHz 2.5 V Microcontroller FCLOCK VMCU Clock Frequency MCU Supply Voltage from internal 2.5V LDO Note 1: BUCK5VT_IN, REG_IN. These pins must be connected together at all times. Note 2: This current is the sum of the input currents for REG_IN and BUCK5VT_IN. Note 3: DC-DC BUCK5VT, LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM, thermistor, LED, buzzer and pull-up resistor loads (up to an absolute maximum of 8mA), as recommended in Figure 11 WPC “Qi” Compliance Schematic and Table 7 WPC “Qi” Compliance Bill of Materials. If any of these outputs is used to power external loads, the performance of the IDTP9036A is not guaranteed. Note 4: Any of the GPIO pins is capable of sourcing 8mA, but if more than one is sourcing current, the total current must not exceed 8mA. Note 5: The 2.5V LDO is powered by the 5V DC/DC converter, so the LDO’s output current must be counted in the output current budget of the DC/DC converter. Revision 1.0.6 7 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet PIN CONFIGURATION IC6 IC5 IC4 IC3 IC2 GND IC1 HPF ISNS IN IN IN TQFN-48L 48 47 46 45 44 43 42 41 40 39 38 37 GPIO_6 1 36 NC5 GPIO_5 2 35 SW GPIO_4 3 34 SW GPIO_3 4 33 SW GPIO_2 5 32 PGND GPIO_1 6 31 NC4 EP (Center Exposed Pad) NC1 10 27 VOSNS NC2 11 26 LX RESET 12 25 BUCK5VT_SNS 13 14 15 16 17 18 19 20 21 22 23 24 BUCK5VT_IN PGND NC3 28 DGND 9 AGND SDA BST PGND BUCK5VT 29 LDO2P5V_IN 8 LDO2P5V SCL LDO5V PGND REG_IN 30 REFGND 7 EN GPIO_0 Figure 2. IDTP9036A Pin Configuration (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm, 0.4mm pitch) Revision 1.0.6 8 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet PIN DESCRIPTION Table 5. IDTP9036A NTG48 Package Pin Functions by Pin Number 1 GPIO_6 I/O General purpose input/output 6. Must be connected to pin 45. 2 GPIO_5 I/O General purpose input/output 5. Must be connected to pin 46. 3 GPIO_4 I/O General purpose input/output 4 4 GPIO_3 I/O General purpose input/output 3 5 GPIO_2 I/O General purpose input/output 2. Must be connected to pin 47. 6 GPIO_1 I/O General purpose input/output 1 7 GPIO_0 I/O General purpose input/output 0 8 SCL I/O I2C clock 9 SDA I/O I2C data 10 NC1 - Internally connected. Must be connected to GND. 11 NC2 - Internally connected. Must be left unconnected. 12 RESET I Active-high chip reset pin. A 1µF ceramic capacitor must be connected between this pin and LDO5V, and a 100kΩ resistor to G D. I Active-low enable pin. Device is suspended and placed in low current (sleep) mode when pulled high. Tie to GND for stand-alone operation. 13 14 REFGND - Signal ground connection. Must be connected to AGND. 15 REG_IN1 I LDO5V power supply input. A 1µF ceramic capacitor must be connected between this pin and GND. This pin must be connected to pin 24. 16 LDO5V2 O 5V LDO output. A 1µF ceramic capacitor must be connected between this pin and GND. 17 LDO2P5V2 O 2.5V LDO output. A 1µF ceramic capacitor must be connected between this pin and GND. 18 LDO2P5V_IN I 2.5V LDO input. The LDO2P5V_IN input must be connected to BUCK5VT. A 1µF ceramic capacitor must be connected between this pin and GND. 19 BUCK5VT2 I Power and digital supply input to internal circuitry Revision 1.0.6 9 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Table 5. IDTP9036A NTG48 Package Pin Functions by Pin Number PIN NAME TYPE DESCRIPTION 20 BST I Bootstrap pin for BUCK converter top switch gate drive supply 21 AGND - Analog ground connection. Connect to signal ground. Must be connected to REFGND. 22 DGND - Digital ground connection. Must be connected to GND. 23 NC3 - Internally connected. Must be left unconnected. 24 BUCK5VT_IN1 I Buck converter power supply input. Connect 0.1µF and 1µF ceramic capacitors between this pin and PGND. This pin must be connected to pin 15. 25 BUCK5VT_SNS I Buck regulator feedback. Connect to the high side of the buck converter output capacitor. 26 LX O Switch ode of BUCK converter. Connects to one of the inductor’s terminals. 27 VOSNS I Coil voltage sense input. Not used. Connect to ground. 28 PGND - Power ground 29 PGND - Power ground 30 PGND - Power ground 31 NC4 - Internally connected. Must be left unconnected. 32 PGND - Power ground 33 SW - 34 SW - 35 SW - 36 NC5 - 37 IN1 - 38 IN1 - 39 IN1 - 40 ISNS O Revision 1.0.6 Internally connected. These pins must be left unconnected (open) at all times. Internally connected. Must be left unconnected. Internally connected. These pins must be left unconnected (open) at all times. ISNS output signal 10 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Table 5. IDTP9036A NTG48 Package Pin Functions by Pin Number PIN NAME TYPE I DESCRIPTION 41 HPF High pass filter input 42 IC1 43 GND 44 IC2 Reserved for special designs. Must be connected to GND. 45 IC3 Reserved for special designs. Must be connected to GPIO6. 46 IC4 Reserved for special designs. Must be connected to GPIO5. 47 IC5 Reserved for special designs. Must be connected to GPIO2. 48 IC6 Reserved for special designs. Must be left unconnected. 49 Center Exposed Pad Reserved for special designs. Must be connected to GND. - Thermal Ground EP, Center Exposed Pad, is on the bottom of the package and must be electrically tied to GND. For good thermal performance, solder to a large copper pad embedded with a pattern of plated through-hole vias. The die is not electrically bonded to the EP, and the EP must not be used as a current-carrying electrical connection. Note 1: REG_IN, BUCK5VT_IN. These pins must be connected together at all times. Note 2: DC-DC BUCK5VT, LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM, thermistor, LED, buzzer and pull-up resistor loads (up to an absolute maximum of 8mA), as recommended in Figure 11 WPC “Qi” Compliance Schematic and Table 7 WPC “Qi” Compliance Bill of Materials. Revision 1.0.6 11 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet TYPICAL PERFORMANCE CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. IN = SW = Open. TA = 25oC, unless otherwise noted. Figure 3. Efficiency vs. RX Output Power with Left Coil #1 Figure 4. Efficiency vs. RX Output Power with Center Coil #2 Revision 1.0.6 12 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Figure 5. Efficiency vs. RX Output Power with Right Coil #3 Revision 1.0.6 13 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet SIMPLIFIED SYSTEMS APPLICATIONS DIAGRAM Inverter Cp + LDO2P5V EN 10K 3.92K 100 - EN 4.7K + c ISNS 3.3K 0.1uF 100K Rm 22nF ZREF_P ACM_P 4.7nF 6.8K 100pF IDTP9020 330nF 0.1uF + C 0.1uF - 0.02 22K Cd Power 100 0.1uF 240 Ls Modulation Cm Load Lp - BUCK5VT Modulation Cs 183nF IN_P IN_P IN_P 44uF REC_OUT REC_OUT REC_OUT REC_OUT 40uF (2x22uF) D 100 330 IDTP9090 Q 10 IN_M 33nF 10 10K 2nF 11.4uH Q 0.1uF 15nF 47nF 0.33 22nF 47nF 11.5u 330nF USB/ADP_IN GPIO_0 ADAPTOR 12.5u 1uF 22nF 10K 3.3nF 0.1uF REC_OUT 22nF 10K 3.3nF 10K 4.7K 15K BUCK5VR 47nF 10uF BST ISNS LDO2P5V_IN LDO5V LDO5V 1uF 1uF BUCK5VR 4.7K IDTP9036A 3.3nF VOSNS 10K 47K ISNS 22nF 10K 3.3nF 15K LDO5V HPF WP SCL SDA __ EN RESET 100K GPIO _5 LDO5V SCL SDA 47K 2.7K GPIO _3 SCL SDA REFGND AGND DGND GPIO _2 GPIO _1 GPIO _0 GPIO_6 5K GPIO_5 5K GPIO_4 5K GPIO_3 5K GPIO_2 GPIO_1 100nF 5K GPIO_0 5K BUCK5VT_SNS BUCK5VT 4.7uH LX RESET RESET GPIO _4 GPIO_1 SCL SDA GPIO _6 RESET 100K 6.8nF 1nF LDO2P5V 100 2.7K 2.7K LDO2P5V 1uF 10K ISNS 10K BUCK5VR 1.5K 10K PGND 2.7K 8 7 6 5 4.7uF 47nF LDO2P5V_IN 47K 1 2 3 4 REG_IN 1uF USB_OUT BUCK5VR_SNS LX LX LX GPIO_3 LEDB 0.1uF GND 11.5u 1.5K 4.7K 33nF 15K 10K GPIO_4 LEDA BUCK5VR_IN BUCK5VR_IN 10uF 422 Buzzer REC_OUT 1.5K 10uF IC4 GPIO_5 ZREF_M BUCK5VR_IN IC3 GPIO_6 BUCK5VT LDO2P5V_IN ACM_M USB_IN REG_IN BUCK5VT_IN PGND IN_M IN_M 0.1uF 10 330 BST LDO5V LDO2P5V GND GPIO_2 EP IC5 REFGND AGND DGND 10uF 47nF LDO5V LDO2P5V 1uF 1uF 100K Figure 6. IDTP9036A/IDTP9020 Simplified Systems Application Diagram Revision 1.0.6 14 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet BLOCK DIAGRAM IN BUCK5VT_SNS REG_IN BUCK5VT LDO5V 1.5 MHZ LDO2P5V_IN BUCK5VT_IN BUCK5VT LX VIN_UVLO IBIAS THSHDN EN Enable Sequence LDO5V LDO2P5V LDO2P5V UVLO_5V/ 2P5V Temp. Signal REF SW REF VIN_OVP GND SCL SDA HPF Demodulator Temp. Signal I2C ROM OTP ADC Micro Controller Unit (MCU) VOSNS MCU Peripherals RAM VOSNS GPIO VINSNS GPIO_<6:0> REG_IN RESET Clock Generation PGND RC OSC IDTP9036A PLL Figure 7. IDTP9036A Internal Functional Block Diagram Revision 1.0.6 15 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet THEORY OF OPERATION The IDTP9036A is a highly-integrated WPC1 (Wireless Power Consortium)-compliant wireless power charging IC solution for the transmitter base station. It can deliver more than 5W of power to the receiver when used with the IDTP9020 or 5W in WPC “Qi” mode using near-field magnetic induction as a means to transfer energy UNDER VOLTAGE LOCKOUT (UVLO) The IDTP9036A has a built-in UVLO circuit that monitors the input voltage and enables normal operation, as shown in Figure 8. UVLO exit event VCOIL (10V/div) OVERVIEW 0V VIN (5V/div) Figure 7 shows the block diagram of the IDTP9036A. When the VIN_UVLO block detects that the voltage at REG_IN and BUCK5VT_IN (connected together externally) is above the Vin_rising UVLO threshold and EN ¯¯ is at a logic LOW, the Enable Sequence circuitry activates the voltage reference, the 5V and 2.5V LDOs, and the 5V buck switching regulator. The voltages at the outputs of the LDOs and the buck regulator are monitored to ensure that they remain in regulation, and the adaptor voltage, coil current, and internal temperature are monitored. VIN=10V 0V The digital block and the MCU output a PWM signal via GPIO0 to the external output inverter powering the selected external field-generating coil. Time (1s/div) Figure 8. VIN versus UVLO threshold with /EN low. Communication packets from the receiver in the mobile device are detected and filtered by an external operational amplifier and passive filter, then provided to the ISNS pin to be further processed by the Demodulator and converted to digital signals that can be read by the MCU. OVER-TEMPERATURE PROTECTION The internal temperature of the IDTP9036A is monitored, and the part shuts down if the temperature exceeds 140°C and reactivates when the temperature falls below 110°C. Several internal voltages are digitized by the ADC and supplied to the MCU for system control and algorithm – related purposes. Two GPIO ports are available to the system designer for driving LEDs and a buzzer. The clock for the MCU and other circuitry is generated by an internal RC oscillator. I2C SDA and SCL pins permit communication with an external device or host. EXTERNAL DRIVERS and INVERTER The external gate driver circuitry drives the off-chip power FETs. The FETs are configured as a power inverter that switches the top sides of the resonant circuits between the VIN supply voltage and ground at a rate set by the MCU control algorithm. Note 1 - Refer to the WPC specification at http://www.wirelesspowerconsortium.com/ for the most current information Revision 1.0.6 16 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet DEMODULATOR Power is transferred from the transmitter to the receiver through the coupling of their respective coils: a looselycoupled transformer. The amount of power transferred is determined by the transmitter’s switching frequency (115kHz-205kHz, by WPC1), and is controlled by the receiver through instructions the receiver sends back through the same coils to the transmitter to change increase or decrease power, end power transfer, or do something else. The instructions take the form of data packets which the receiver modulates on the carrier. The modulation is detected and then coupled through a series of filters connected to the IDTP9036A’s Demodulator and then fed to the HPF pin. Recovering the data packets is the function of the Demodulator. Decoding and executing the packets is one of the functions of the MCU. MICRO-CONTROLLER UNIT (MCU) The IDTP9036A’s MCU processes the algorithm, commands, and data that control the power transferred to the reciever. The MCU is provided with RAM and ROM, and parametric trim and operational modes are set at the factory through the One-Time Programming (OTP) block, read by the MCU at power-up. Communication with external memory is performed through I2C via the SCL and SDA pins. APPLICATIONS INFORMATION The recommended applications schematic diagram is shown in Figure 11. The IDTP9036A operates from a 12VDC (±5%) input. The switching frequency varies from 115kHz to 205kHz. At the 205kHz limit the duty cycle is also variable. The power transfer is controlled via changes in switching frequency and duty cycle. The base or TXside has three series-resonance circuits made of a WPC Type-A6 triple coil and three capacitors. Two of the coils are 11.5H each, and the other one is 12.5μH, each with a series resonant capacitor (~133nF or 147nF). The resonant circuits are driven by an external half-bridge inverter, as shown in Figure 9. Only the resonant circuit that is aligned with a receiver coil gets a complete path from the inverter output to power ground. The selection is made by voltage levels from GPIO5 and GPIO6, each of which drives a selection FET directly and drives an input of a wired-NAND circuit that activates or de-activates the third resonant circuit. Revision 1.0.6 12V + - A6 Coil External Driver Fsw from GPIO0 GPIO5 GPIO6 GPIO5 GPIO6 Figure 9. Half Bridge inverter TX Coil Driver. EXTERNAL CHIP RESET and EN ¯¯ The IDTP9036A can be externally reset by pulling the RESET pin to a logic high above the VIH level. The RESET pin is a dedicated high-impedance active-high digital input, and its effect is similar to the power-up reset function. Because of the internal low-voltage monitoring scheme, the use of the external RESET pin is not mandatory. A manual external reset scheme can be added by connecting 5V to the RESET pin through a simple switch. When RESET is HIGH, the microcontroller’s registers are set to the default configuration. When the RESET pin is released to a LOW, the microcontroller starts executing the code from the EEPROM. If the particular application requires the IDTP9036A to be disabled, this can be accomplished with the EN ¯¯ pin. When the EN ¯¯ pin is pulled high, the device is suspended and placed in low current (sleep) mode. If pulled low, the device is active. The current into EN ¯¯ is approximately for input voltages between VIN and +2V, and close to zero if V(EN ¯¯) is less than 2V. SYSTEM FEEDBACK CONTROL (WPC) The IDTP9036A contains logic to demodulate and decode error packets sent by the mobile device (Rx-side), and adjusts power transfer accordingly. The IDTP9036A varies the switching frequency of the external half bridge inverter between 115kHz to 205 kHz to adjust power transfer. The mobile device controls the amount of power transferred via a communication link that exists from the mobile 17 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet device to the base station. The mobile device (IDTP9020 or another WPC-compliant receiver) communicates with the IDTP9036A via Communication Packets. Each packet has the following format: Required packet(s) in PING: Table 6 – Data Packet Format. The mobile device must send a Signal Strength Packet within a time period specified by the WPC, otherwise the power signal is terminated and the process repeats. Preamble Header Message 1. Signal Strength Packet (0x01) Checksum The mobile device calculates the Signal Strength Packet value, which is an unsigned integer value between 0-255, based on this formula: The overall system behavior between the transmitter and receiver follows the state machine diagram below: where U is a monitored variable (i.e. rectified voltage/current/power) and Umax is a maximum value of that monitored variable expected during the digital ping phase at 175 kHz. If the IDTP9036A does not detect the start bit of the header byte of the Signal Strength Packet during the Ping Phase, it removes the Power Signal after a delay. If a Signal Strength Packet is received, the IDTP9036A goes to the Identification and Configuration Phase. If the IDTP9036A does not move to the Identification and Configuration Phase after receiving the Signal Strength Packet, or if a packet other than a Signal Strength Packet is received, then power is terminated and eventually a new selection phase will begin. IDENTIFICATION AND CONFIGURATION (ID & Config) Figure 10. System state machine diagram In this phase, the IDTP9036A tries to identify the mobile device and collects configuration information. The IDTP9036A performs four phases: Selection, Ping, Identification & Configuration, and Power Transfer. Required packet(s) in ID & Config: START (SELECTION) PHASE 1. Identification Packet (0x71) 2. Extended Identification Packet (0x81)* 3. Configuration Packet (0x51) In this phase, the IDTP9036A operates in a low power mode to determine if a potential receiver has been placed on the coil surface prior to the PING state. Twice a second, the IDTP9036A applies a brief AC signal sequentially to each one of the coils of the triple A6 coil and listens for a response. When a response is found, it locks its output and communication sense line to that coil. * If Also, the IDTP9036A must correctly receive the following sequence of packets without changing the operating point (175 kHz @ 50% duty cycle): PING PHASE 1. Identification Packet (0x71) 2. Extented Identification (0x81) 3. Up to 7 optional configuration packets from the following set: In this phase, the IDTP9036A applies a power signal at 175 kHz with a fixed 50% duty cycle and attempts to establish a communication link with a mobile device. Revision 1.0.6 Ext bit of 0x71 packet is set to 1. 18 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet a. Power Control Hold-Off Packet (0x06) b. Proprietary Packet (0x18 – 0xF2) c. Reserved Packet 4. Configuration Packet (0x51) If the IDTP9036A does not detect the start bit of the header byte of the next packet in the sequence within a WPC-specified time after receiving the stop bit of the checksum byte of the preceding Signal Strength Packet, then the Power Signal is removed within after a delay. If a correct Control Packet in the above sequence is received late, or if Control Packets that are not in the sequence are received, the IDTP9036A removes the Power Signal after a delay. POWER TRANSFER PHASE In this phase, the IDTP9036A adapts the power transfer to the receiver based on control data it receives in Control Error Packets. Upon receiving a Control Error value, the IDTP9036A makes adjustments to its operating point after a delay to enable the Primary Coil current to stabilize again after communication. If the IDTP9036A correctly receives a packet that does not comply with the sequence, then it removes the Power Signal. FOREIGN OBJECT DETECTION (FOD) In addition to over-temperature protection, the IDTP9036A employs a proprietary FOD technique which detects foreign objects placed on the base station. The FOD algorithm is multi-layered and may issue warnings and/or change device operation depending on the severity of the warning. FOD is an optional feature that is not included in the standard firmware. Please contact IDT to incorporate this feature into a specific product, indicating volume and business case. Required packet(s) in Power Transfer: 1. Control Error Packet (0x03) 2. Rectified Power Packet (0x04) For this purpose, the IDTP9036A may receive zero or more of the following packets: 1. 2. 3. 4. 5. 6. Control Error Packet (0x03) Rectified Power Packet (0x04) Charge Status Packet (0x05) End Power Transfer Packet (0x02) Any Proprietary Packet Any reserved Packets If the IDTP9036A does not correctly receive the first Control Error Packet in time, it removes the Power Signal after a delay. Because Control Error Packets come at a regular interval, the IDTP9036A expects a new Control Error Packet after receiving the stop bit of the checksum byte of the preceding Control Error Packet. If that does not happen, then the IDTP9036A removes the Power Signal. Similary, the IDTP9036A must receive a Rectified Power Packet within a WPC-specified time after receiving the stop bit of the checksum byte of the Configuration Packet (which was received earlier in the identification and configuration phase). Otherwise, it removes the Power Signal. Revision 1.0.6 19 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet APPLICATIONS INFORMATION Figure 11. IDTP9036A WPC “Qi” Compliance Low-cost Schematic (See IDTP9036A Evaluation Kit User Manual for complete details and optional components.) Revision 1.0.6 20 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Figure 11a. Input power, LDO5V, LEDs, buzzer, and I2C Revision 1.0.6 21 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Figure 11b. Wired-NOR using GPIO5 and GPIO6, LDO2P5V Revision 1.0.6 22 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Figure 11c. External inverter logic, drivers, switches, and current sense Revision 1.0.6 23 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Figure 11d. Coil switching Revision 1.0.6 24 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Table 7. IDTP9036A WPC “Qi” Compliance Bill of Materials Item 1 Quantity Part 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 1 6 4 2 1 3 6 1 2 1 2 1 3 1 1 3 1 1 3 3 1 1 1 1 3 9 BUZZER AUDIO PIEZO 25VP-P SMD CAP CER 4700PF 50V 10% X7R 0402 CAP CER 0.1UF 50V 10% X7R 0402 CAP CER 0.1UF 50V 10% X7R 0603 CAP CER 22UF 25V 10% X5R 1206 CAP CER 0.015UF 50V 10% X7R 0402 CAP CER 82nF 100V 5% NP0 1812 CAP CER 1UF 25V 10% X7R 0603 CAP CER 0.047UF 16V 10% X7R 0603 CAP CER 10UF 25V 20% X5R 0805 CAP CER 6800PF 50V 10% X7R 0402 CAP CER 0.056UF 100V 5% NP0 1812 CAP CER 1000PF 50V 10% X7R 0402 CAP CER 0.022UF 50V 10% X7R 0603 CAP CER 3300PF 50V 10% X7R 0402 CAP CER 0.068UF 100V 5% NP0 1812 CAP CER 3300PF 100V 10% X7R 0603 TBD 0402 29 30 31 32 33 34 35 36 1 1 1 1 1 3 1 8 CONN HEADER LOPRO STR 10POS GOLD PJ-002AH IND 4p7uH 500mA SMD 37 38 39 3 MOSFET N-CH SGL 60V 340MA SOT323 2 9 RES 10K OHM 1/10W 5% 0603 SMD 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 4 2 2 1 6 4 3 3 1 2 2 2 1 1 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 CAP CER 100PF 200V 5% NP0 0805 CAP CER 470PF 50V 10% X7R 0603 Cap 25V X7R 0402 LED SMARTLED 630NM RED 0603 SMD LED SMARTLED GREEN 570NM 0603 DIODE SWITCH 200V 250MW SOD123 PC TEST POINT MINIATURE SMT CHOKE COMMON MODE 1400 OHM SMD MOSFET N-CH 80V 8-SOIC TRANS PNP LP 100MA 45V SOT23 MOSFET N-CH 60V 115MA SOT323 RES 6.80K OHM 1/16W 1% 0402 SMD RES 4.7K OHM 1/10W 5% 0402 SMD RES 2.7K OHM 1/10W 5% 0402 SMD RES 100K OHM 1/10W 5% 0402 SMD RES 10.0K OHM 1/10W 1% 0402 SMD RES 10.0K OHM 1/10W 1% 0603 SMD RES 47K OHM 1/10W 5% 0402 SMD RES 249 OHM 1/10W 1% 0603 SMD RES 15K OHM 1/10W 5% 0603 SMD RES 422 OHM 1/10W 1% 0402 SMD RES 330 OHM 1/10W 5% 0603 SMD RES 240 OHM 1/10W 5% 0402 SMD RES 10 OHM 1/20W 5% 0201 SMD RES 100 OHM 1/10W 5% 0603 SMD RES 0.02 OHM 0.5W 1% 1206 SMD RES 100 OHM 1/10W 5% 0402 SMD RES 3.3K OHM 1/10W 5% 0402 SMD RES 1/10W 1% 0402 SMD RES 22K OHM 1/10W 1% 0402 SMD RES 4.99K OHM 1/10W 1% 0402 SMD RES 3.92K OHM 1/10W 1% 0402 SMD RES 100K OHM 1/10W 1% 0402 SMD RES 0.33 OHM 1/10W 1% 0603 SMD THERMISTOR NTC K 5% RADIAL Wireless controller IC EEPROM 64KBIT 400KHZ 8TDFN IC D-TYPE F-F W/CLR PRESET SM8 IC AMP SINGLE R-R I/O SOT23-5 IC Quad 2 input AND Gate IC OPAMP GP R-R CMOS 1MHZ SC70-5 Part_Number Reference P3,IO3,GND3,P4,IO4,LDO5, IO5,+5V,IO6,P9,P10,P11, P12,P17,SDA,SCL,RST,EN PS1240P02CT3 BZ1 C1005X7R1H472K050BA C1 C1005X7R1H104K C2,C41,C42,C45,C52,C55 GRM188R71H104KA93D C3,C17,C21,C34 GRM31CR61E226KE15L C4,C50 GRM155R71H153KA12D C5 C1812C823J1GACTU C8,C11,C20 C1608X7R1E105K C12,C14,C25,C51,C83,C84 GRM188R71C473KA01D C15 C2012X5R1E106M C18,C22 C1005X7R1H682K C23 C1812C563J1GACTU C24,C28 C1005X7R1H102K C26 C1608X7R1H223K C27,C46,C48 C1005X7R1H332K C29 C1812C683J1GACTU C30 C1608X7R2A332K C32,C47,C49 NP C53 GRM188R71C473KA01D C69 C0805X101J2GACTU C71,C77,C79 C1608X7R1H471K C74,C75,C76 C1005X7R1H104K C82 C1005X7R1E222K C85 L29K-G1J2-1-0-2-R18-Z D1 LG L29K-G2J1-24-Z D2 BAV21W-7-F D9,D10,D11 5015 VIN1,PGND1,GND1,GND2, VINAD,VIN,PGND,GNDAD,GND 5103308-1 J1 PJ-002AH J3 XPL2010-472MLB L1 Y31-60050F L2 ACM4520-901-2P-T-000 L3 SiR826ADP Q1,Q22,Q23 BC857CLT1G Q4 2N7002 Q6,Q7,Q8,Q11,Q12,Q13,Q14, Q15 2N7002WT1G Q16,Q17,Q18 DMG7430LFG Q20,Q21 ERJ-3GEYJ103V R1,R4,R26,R74,R94,R98, R107,R116,R119 RC0402FR-076K8L R2 ERJ-2GEJ472X R5,R7,R97,R111 ERJ-2GEJ272X R10,R13 ERJ-2GEJ104X R14,R19 ERJ-2RKF1002X R22 ERJ-3EKF1002V R23,R35,R53,R54,R56,R57 ERJ-2GEJ473X R29,R62,R70,R120 ERJ-3EKF2490V R59,R60,R61 ERJ-3GEYJ153V R63,R64,R65 ERJ-2RKF4220X R66 NP R69,R117 ERJ-1GEJ331C R73,R75 ERJ-1GEJ100C R76,R77 ERJ-2GEJ241X R81 ERJ-1GEJ100C R82 ERJ-3GEYJ101V R84 PF1206FRF070R02L R86 ERJ-2GEJ101X R87,R88 ERJ-2GEJ332X R89 TBD R108 ERJ-2RKF2202X R109 ERJ-2RKF4991X R114 ERJ-2RKF3921X R118 CRCW040243K0JNED R121 ERJ-3RQJR33V R122 NTCLE203E3103JB0 Th1,Th2,Th3 P9036A U1 24AA64T-I/MNY U2 SN74LVC2G74 U4 FAN4174IS5XCT-ND U9 74AHCT08BQ,115 U10 AD8614ARTZ-REEL7 U12 IDTP9090 U13 Value TP PCB Footprint TEST_PT30DPAD Buzzer 4.7nF 0.1uF 0.1uF 22uF 15nF 82nF 1uF 47nF 10uF 6.8nF 56nF 1nF 22nF/50V 3.3nF 68nF 3.3nF NP 47nF NP 470pF 0.1uF 2.2nF RED GREEN Diode TEST POINT buzz_ps1240 I2C connector AC_Adapter 4.7uH A6 3-Coil Tx ACM4520 SiR826ADP BC857CL 2N7002 LOPRO8PIN01INREVB CONN_POWER_JACK5_5MM 2N7002 DMG7430LFG 10K SOT23_3 powerdi3333_8ld_fet 402 402 603 1206 402 1812 603 603 805 402 1812 402 603 402 1812 603 402 603 805 603 402 402 0603_DIODE 0603_DIODE SOD123 TEST_PT_SM_135X70 805 3coil_a6_standard emi_tdk_acm4520 SOIC8LD_PWRPAK_FET SOT23_3 SOT23_3 402 6.8K 4.7K 2.7K 100K 10K 10K 47K 249 15K 422 NP 330 10 240 10 100 0.02 100 3.3K NP 22K 4.99K 3.92K 43K 0.33 NP IDTP9036A 24AA64T-I/MNY 74LVC2G74 FAN4174 74AHCT08 AD8614 IDTP9090 402 402 402 402 402 603 402 603 603 402 402 201 201 402 201 603 2512 402 402 402 402 402 402 402 603 NTC1 NTG_48LD_6X6MM_0P4PITCH DFN8 LSSOP_8LD SOT_23_5 DHVQFN_14LD_2p5x3mm SOT_23_5 nlg8LD_3x3_0p65mm Note 1: Recommended capacitor temperature/dielectric and voltage ratings: 100V capacitors are recommended because 100Vp-p voltage transients may appear on the resonance capacitors as stated in the WPC specification. C0G/NPO-type capacitor values stay relatively constant with voltage while X7R and X5R ceramic capacitor values de-rate from 40% to over 80%. The decision to use lower voltage 50V C0G/NPO capacitors is left to the end user. External Components 7). A complete design schematic compliant to the WPC “Qi” standard is given in Figure 11. It includes WPC “Qi” LED signaling, buzzer, and an EEPROM for loading IDTP9036A firmware. The IDTP9036A requires a minimum number of external components for proper operation (see the BOM in Table Revision 1.0.6 25 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet I2C Communication modes. The table also includes information about external resistors or internal pull up/down options to select LED modes. Eight of the ten LED modes (those associated with advanced charging modes) are currently designated as “Future” modes. The IDTP9036A includes an I2C block which can support either I2C Master or I2C Slave operation. After power-onreset (POR), the IDTP9036A will initially become I2C Master for the purpose of uploading firmware from an external memory device, such as an EEPROM. The I2C Master mode on the IDTP9036A does not support multimaster mode, and it is important for system designers to avoid any bus master conflict until the IDTP9036A has finished any firmware uploading and has released control of the bus as I2C Master. After any firmware uploading from external memory is complete, and when the IDTP9036A begins normal operation, the IDTP9036A is normally configured by the firmware to be exclusively in I2C Slave mode. GPIO4: Red LED and AC or DC buzzer (optional) with resistor options for different buzzer. LED FUNCTIONS Two GPIOs are used to drive LEDs which indicate, through various on/off and illumination options, the state of charging and some possible fault conditions. A red LED indicates various Fault and FOD (“Foreign Object Detection”) states. The green L D indicates Power Transfer and Charge Complete state information. Upon power up, the two LEDs together may optionally indicate the Standby State and remain in this state until another of the defined Operational States occurs For maximum flexibility, the IDTP9036A tries to communicate with the first address on the EEPROM at 100kHz. If no ACK is received, communication is attempted at the other addresses at 300kHz. EEPROM As shown in Figure 12, one or two resistors configure the defined LED option combinations. The DC voltage set in this way is read one time during power-on to determine the LED configuration. To avoid interfering with the LED operation, the useful DC voltage range must be limited to not greater than 1Vdc. The IDTP9036A requires an external EEPROM which contains either standard or custom TX firmware. The external EEPROM memory chip is pre-programmed with a standard start-up program that is automatically loaded when 12V power is applied. The IDTP9036A uses I2C slave address 0x52 to access the EEPROM. The IDTP9036A slave address is 0x39. The EEPROM can be reprogrammed to update the start-up program using the IDT Windows GUI (see the IDTP9036A-Qi Demo Board User Manual for complete details). A serial 8Kbyte (8Kx8 64Kbits) external EEPROM is sufficient. LDO2P5V_OUT IDTP9036 Ra GPIO3 If the standard default firmware is not suitable for the application, custom ROM options are possible. Please contact IDT sales for more information. IDT will provide the appropriate image in the format best suited to the application. Resistor to set options To ADC Rb LED Mode Resistor Configuration Overview of Standard GPIO Usage Figure 12. IDTP9036A LED Resistor Options. There are 7 GPIO’s on the IDTP9036A transmitter IC, of which two are available for use as follows: LED Pattern Operational Status Definitions: Blink Slow, Fast, repeat. GPIO3: Green LED_B to indicate standby, power transfer, and power complete. Table 8 lists how the red and green LEDs can be used to display information about the IDTP9036A’s operating Revision 1.0.6 26 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet Table 8 – IDTP9036A LED Resistor Optioning (Not all options supported, shaded rows are for future development). LED Control Option LED Select Resistor Value Description 1 Pull Down Standby LEDs ON 2 R1 Standby LEDs ON plus 3 R2 Standby LEDs ON plus 4 R3 Standby LEDs ON plus 5 R4 Standby LEDs ON plus 6 Pull Up Standby LEDs OFF 7 R5 Standby LEDs OFF plus 8 R6 Standby LEDs OFF plus 9 R7 Standby LEDs OFF plus 10 R8 Standby LEDs OFF plus Operational Charge Status Power LED #/ Transfer Complete Color Standby LED1- Green ON BLINK SLOW ON LED2- Red ON OFF OFF LED1- Green ON BLINK SLOW ON LED2- Red ON OFF OFF LED1- Green ON BLINK SLOW ON LED2- Red ON OFF OFF LED1- Green ON BLINK SLOW ON LED2- Red ON OFF OFF LED1- Green ON BLINK SLOW ON LED2- Red ON OFF OFF LED1- Green OFF BLINK SLOW ON LED2- Red OFF OFF OFF LED1- Green OFF BLINK SLOW ON LED2- Red OFF OFF OFF LED1- Green OFF BLINK SLOW ON LED2- Red OFF OFF OFF LED1- Green OFF BLINK SLOW ON LED2- Red OFF OFF OFF LED1- Green OFF BLINK SLOW ON LED2- Red OFF OFF OFF Fault Condition OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON FOD Warning OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST OFF BLINK FAST R1-R8 are created using combination of two 1% resistors. Designates Future Option Buzzer Function For 30 seconds: 400ms ON, 800ms OFF, repeat Next 30 seconds: Off/silence (but no change to LED on/off patterns) The pattern is repeated while the error condition exists An optional buzzer feature is supported on GPIO4. The default configuration is an “AC” buzzer. The signal is created by toggling GPIO4 active-high/active-low at a 2kHz frequency. The buzzer is synchronized with the FOD LED such that the 400ms on tone corresponds with the red LED illumination and 800ms off (no sound) corresponds with the red LED being off. Buzzer Action: Power Transfer Indication The IDTP9036A supports audible notification when the device operation successfully reaches the Power Transfer state. The duration of the power transfer indication sound is 400ms. Decoupling/Bulk Capacitors The latency between reaching the Power Transfer state and sounding the buzzer does not exceed 500ms. Additionally, the buzzer sound is concurrent within ±250ms of any change to the LED configuration indicating the start of power transfer. As with any high-performance mixed-signal IC, the IDTP9036A must be isolated from the system power supply noise to perform optimally. A decoupling capacitor of 0.1μF must be connected between each power supply and the PCB ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor must be mounted on the component side of the PCB. Additionally, medium value capacitors in the 22μF range must be used at the VI input to minimize ripple current and voltage droop due to the large current requirements of the resonant half Half-Bridge driver. At least four 22μF capacitors must be used close to the drain Buzzer Action: No Power Transfer due to Foreign Object Detected (FOD) When a major FOD situation is detected such that, for safety reasons, power transfer is not initiated, or that power transfer is terminated, the buzzer is sounded in a repeating sequence: Revision 1.0.6 27 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet of the top MOSFET of the external half-bridge. The value of the capacitors will decrease as the voltage applied approaches the nominal voltage, due to the ceramic dielectric characteristics. For example, a 22μF X7R 25V capacitor’s value could be as low as 6μF when operating at 13V, depending on the manufacturer. 100nF capacitor for the center coil. The part numbers are shown in Table 7. Buck Converter The input capacitors (CIN) must be connected directly between the power pins (REG_IN and BUCK5VT_IN) and power PGND pins as near as possible to the IC pins. The output capacitor (COUT) must be placed as close to the device and power ground pins (PGND) as possible. There must also be an 82μF to 100μF bulk capacitor connected at the point where the input voltage to the board is applied. A 100μF 16V POSCO must be connected between the input supply and ground as shown in Figure 11. POSCON capacitors have much lower ESR than aluminum electrolytic capacitors and will reduce voltage ripple. Connect a 47nF bootstrap capacitor rated above 25V between the BST pin and the LX pin. The output-sense connection to the feedback pin, BUCK5VT_SNS, must be separated from any power trace. Connect the output-sense trace as close as possible to the load point to avoid additional load regulation errors. The buck will regulate the voltage at the point on the output the sense line is connected to. ADC Considerations The GPIO pins can be configured to connect internally to the successive approximation ADC through the ADC’s input multiplexer. The ADC has a limited input range, so attention must be paid to the maximum VIN (2.4V). 0.01μF decoupling capacitors can be added to the GPIO inputs to minimize noise. The power traces, including PGND traces, the LX or 5V output traces, and the VIN trace must be kept short, direct and wide to allow large current flow. Use several via pads when routing power lines between layers. WPC TX-A6 Coil LDOs The external half-bridge output connects to three seriesresonance circuits made by a WPC triple Type-A6 coil (two 11.5H side coils and one 12.5μH center coil) and series resonant capacitors (total value 133nF for the two side coils and total value 147nF for the center coil). The selected inductor serves as the primary coil of a looselycoupled transformer, the secondary of which is the inductor connected to the power receiver (IDTP9020 or another). Input Capacitor The input capacitors must be located as physically close as possible to the power pin (LDO2P5V_IN) and power ground (GND). Ceramic capacitors are recommended for their low ESR and small profile. Also, ceramic capacitors are inherently more capable than tantalum capacitors to withstand input current surges from low impedance sources such as batteries used in portable devices. Typically, 10V- or 16V-rated capacitors are required. The recommended external components are shown in Table 7. The TX-A6 power transmitter coils are mounted on a ferrite base acting as a shield to concentrate the field on the top side of the coil and to reduce EMI. The coil assembly can be mounted next to the IDTP9036A. Either ground plane or grounded metal shielding (preferably copper) can be added beneath the ferrite shield for added reduction in radiated electrical field emissions. The coil ground plane/shield must be connected to the IDTP9036A ground plane by a single trace. Output Capacitor For proper voltage regulation and stability, a capacitor is required on the output of each LDO (LDO2P5V and LDO5V). The output capacitor must be placed as close to the device and power (PGND) pins as possible. Since the LDOs have been designed to function with very low ESR capacitors, a ceramic capacitor is recommended for best performance. Resonance Capacitors The resonance capacitors must be C0G type dielectric and have a DC rating to 100V. Use one 33nF and one 100nF capacitor for each side coil, and one 47nF and one Revision 1.0.6 28 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet - PCB Layout Considerations - For optimum device performance and lowest output phase noise, the following guidelines must be observed. Please contact IDT for Gerber files that contain the recommended board layout. - As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. - The 0.1μF decoupling capacitors must be mounted on the component side of the board as close as possible to the pins intended to be decoupled. Keep PCB traces to each power pin and to ground vias as short as possible. - To optimize board layout, place all components on the same side of the board. Route signal traces away from the IDTP9036A. - The NQG48 6.0mm x 6.0mm x 0.75mm 48L package has an inner thermal pad which requires blind assembly. It is recommended that a more active flux solder paste be used such as Alpha OM-350 solder paste from Cookson Electronics (http://www.cooksonsemi.com). Please contact IDT for Gerber files that contain recommended solder stencil design. - The package center exposed pad (EP) must be reliably soldered directly to the PCB. The center land pad on the PCB (set 1:1 with EP) must also be tied to the board ground plane, primarily to maximize thermal performance in the application. The ground connection is best achieved using a matrix of platedthrough-hole (PTH) vias embedded in the PCB center land pad for the NTG48. The PTH vias perform as thermal conduits to the ground plane (thermally, a heat spreader) from the solder side of the board. - On the solder side of the board, these thermal vias embed in a copper fill having the same dimensions as the center land pad on the component side. Recommendations for the via finished hole-size and array pitch are 0.3mm to 0.33mm and 1.3mm, respectively. Revision 1.0.6 Layout and PCB design have a significant influence on the power dissipation capabilities of power management ICs. This is due to the fact that the surface mount packages used with these devices rely heavily on thermally conductive traces or pads to transfer heat away from the package. Appropriate PC layout techniques must then be used to remove the heat due to device power dissipation. The following general guidelines will be helpful in designing a board layout for lowest thermal resistance: 1. PC board traces with large cross sectional areas remove more heat. For optimum results, use large area PCB patterns with wide and heavy (2 oz.) copper traces. 2. In cases where maximum heat dissipation is required, use double-sided copper planes connected with multiple vias. 3. Thermal vias are needed to provide a thermal path to the inner and/or bottom layers of the PCB to remove the heat generated by device power dissipation. 4. Where possible, increase the thermally conducting surface area(s) openly exposed to moving air, so that heat can be removed by convection (or forced air flow, if available). Power Dissipation/Thermal Requirements The IDTP9036A is offered in a TQFN-48L package. The maximum power dissipation capability is 1.3W, limited by the die’s specified maximum operating junction temperature, TJ, of 125°C. The junction temperature rises with the device power dissipation based on the package thermal resistance. The package offers a typical thermal resistance, junction to ambient (JA), of 31°C/W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section. The techniques as noted in the PCB Layout section need to be followed when designing the printed circuit board layout. Care should be exercised to avoid the placement of the IDTP9036A IC package in proximity to other heat generating devices in a given application design. The ambient temperature around the power IC will also have an effect on the thermal limits of an application. The main factors influencing θJA (in the order of decreasing influence) are PCB characteristics, die/package attach thermal pad size, and internal package construction. Board designers should keep in mind that the package thermal metric θJA is impacted by the characteristics of the PCB itself upon 29 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet which the TQFN is mounted. Changing the design or configuration of the PCB impacts the overall thermal resistivity and, thus, the board’s heat sinking efficiency. Thermal Overload Protection The IDTP9036A integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. This circuitry will shut down or reset the device if the die temperature exceeds 140°C. Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many systemdependant issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components, affect the power-dissipation limits of a given component. Special Notes NQG TQFN-48 Package Assembly Note 1: Unopened Dry Packaged Parts have a one year shelf life. Note 2: The HIC indicator card for newly opened Dry Packaged Parts should be checked. If there is any moisture content, the parts must be baked for a minimum of 8 hours at 125˚C within 24 hours of the assembly reflow process. Three basic approaches for enhancing thermal performance are listed below: 1. Improving the power dissipation capability of the PCB design 2. Improving the thermal coupling of the component to the PCB 3. Introducing airflow into the system Revision 1.0.6 30 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet PACKAGE OUTLINE DRAWING REVISIONS DCN REV DESCRIPTION DATE 00 INITIAL RELEASE 3/16/10 APPROVED POD IN BOTTOM VIEW 37 DAP SIZE 4.5x4.5 48 36 1 C0.35 25 12 24 13 IDT TOLERANCES UNLESS SPECIFIED POD IN SIDE VIEW DECIMAL X± .1 XX± .05 XXX± .030 APPROVALS DRAWN PKP CHECKED TM ANGULAR ±1° DATE 12/04/09 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 PHONE: (408) 284-8200 FAX: (408) 284-3572 www.IDT.com TITLE NT/NTG48 PACKAGE OUTLINE 6.0 x 6.0 mm BODY 0.4 mm PITCH TQFN SIZE C DRAWING No. REV PSC-4294 DO NOT SCALE DRAWING 00 SHEET 1OF 1 Figure 13. IDTP9036A Package Outline Drawing (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm48L, 0.4mm pitch) Revision 1.0.6 31 © 2013 Integrated Device Technology, Inc. IDTP9036A Product Datasheet ORDERING GUIDE Table 8. Ordering Summary PART NUMBER MARKING PACKAGE AMBIENT TEMP. RANGE SHIPPING CARRIER QUANTITY P9036A-0NTGI P9036A-0NTGI8 P9036ANTG P9036ANTG NTG48 - TQFN-48 6x6x0.75mm NTG48 - TQFN-48 6x6x0.75mm -40°C to +85°C -40°C to +85°C Tray Tape and Reel 25 2,500 www.IDT.com 6024 Silver Creek Valley Road San Jose, California 95138 Tel: 800-345-7015 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. © Copyright 2013. All rights reserved.