M66238FP Standard Clock Generator with PLL Frequency Synthesizer REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Description The M66238 is a LSI that incorporates a PLL synthesizer and a sync clock generator in it. The PLL synthesizer covers the range of 25 MHz to 50 MHz at the minimum steps of 3 kHz. The sync circuit outputs a clock and a one-shot pulse which are synchronized with an external trigger signal. Setting a dividing ratio allows acquisition of sync clock outputs within the range of 0.78 MHz to 25 MHz. Features • • • • • Sync clock output frequency range: 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of 25 to 50 MHz Sync accuracy (jitter): ±3 ns Trigger input: Polarity selectable One-shot pulse output: Polarity and width selectable 5 V power supply Application Pixel clock generator Block Diagram Chip select input CS 3 Serial data input SIN 4 Serial clock input SCLK 5 Command register Serial write control circuit Command control circuit 10 TCKI Test pin 11 TCKO 15 12 Clock input XIN 7 Clock output XOUT 6 Crystal oscillator circuit 15-bit counter fin Phase comparator 12-bit divider Reset input RESET Trigger input 2 VCO 25 MHz to 50 MHz fvco Charge pump TR 17 21 UP 20 24 DOWN CPOUT 26 29 CPIN RV Filter connect pin Test pin Filter connect pin REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 1 of 14 VCO load output Sync/divider circuit Sync clock generator 12 CKO/ PLLO PLL output 13 CKOB Clock output 14 PULSE One-shot pulse output M66238FP Pin Arrangement M66238FP Digital GND pin DGND 1 32 AGND Reset input RESET 2 31 AVCC Analog GND pin Analog power supply pin Chip select input CS 3 30 AGND Analog GND pin Serial data input SIN 4 29 RV Serial clock input SCLK 5 28 AVCC VCO load output Analog power supply pin Clock output XOUT 6 27 AGND Analog GND pin Clock input XIN 7 26 CPIN Filter connect pin Digital GND pin DGND 8 25 AGND Analog GND pin Digital power supply pin DVCC 9 24 CPOUT Filter connect pin Test pin TCKI 10 23 DGND TCKO 11 22 DVCC Digital GND pin Digital power supply pin PLL output CKO/PLLO 12 21 UP Clock output CKOB 13 20 DOWN One-shot pulse output PULSE 14 19 DVCC Digital power supply pin Sync output power supply pin Sync output GND pin VCCO 15 18 DGND Digital GND pin GNDO 16 17 TR Trigger input Test pin (Top view) Outline: 32P2W-A Pin Description Pin Name RESET CS SIN Name Reset input Chip select input Serial data input I/O Input Input Input SCLK XIN XOUT Serial clock input Clock input Clock output Input Input Output TR CKOB CKO/PLLO Trigger input Clock output PLL output Input Output Output PULSE CPOUT One-shot pulse output Filter connect pin Output Output CPIN RV Filter connect pin VCO load output Input Output TCKI TCKO UP DOWN DVCC DGND VCCO GNDO AVCC AGND Test pin Test pin Test pin Test pin Digital power supply pin Digital GND pin Sync output power supply pin Sync output GND pin Analog power supply pin Analog GND pin Input Output Output Output — — — — — — REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 2 of 14 Function Initialize M66238 internal status. Transfer serial data when CS = "L". Synchronize 32-bit serial data from MCU with SCK, and enter. Enter a sync clock for writing 32-bit serial data. Used by connecting crystal oscillator between XIN and XOUT. When using an external clock signal, connect the clock oscillator to XIN pin and open XOUT pin. Trigger input for clock sync. Output an inverted CKO signal. CKO outputs a clock synchronized with a trigger signal and PLLO outputs a PLL oscillator clock as it is. Output a one-shot pulse synchronized with a CKO signal. Connect a low pass filter to charge pump output. Low pass filter input pin. Connect a load resistor for VCO circuit operation between RV and GND. Shipping test pin. Connect to GND when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Digital power supply pin. Digital GND pin. Power supply pin for sync output. GND pin for sync output. Analog power supply pin. Analog GND pin. M66238FP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Power dissipation*1 Storage temperature Note: Symbol Ratings –0.5 to +7.0 –0.5 to Vcc + 0.5 –0.5 to Vcc + 0.5 650 –65 to +150 Vcc Vi Vo Pd Tstg Unit V V V mW °C 1. When board is mounted All voltages adopt the GND pin of the circuit as the base (0 V) and absolute values are displayed for maximum and minimum values. Recommended Operating Conditions (Ta = 0 to 70°C) Item Symbol Supply voltage Supply voltage Input voltage Output voltage Operating ambient temperature Note: Min 4.75 — 0 0 0 Vcc GND Vi Vo Topr Typ 5 0 — — — Max 5.25 — Vcc Vcc 70 Unit V V V V °C The direction of current flowing into a circuit is defined to be positive (no sign) and the direction of current flowing out is defined to be negative (–sign). Absolute values are displayed for maximum and minimum values. Electrical Characteristics (Ta = 0 to 70°C, Vcc = 5 V ± 5%, GND = 0 V) Item High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol VIH VIL VIH VIL VOH VOL Supply current (at time of standstill) Supply current (at time of operation) High-level input current Low-level input current Input capacitance Note: Min 2 — 0.8 × Vcc — Vcc – 0.8 — Typ — — — — — — Max — 0.8 — 0.2 × Vcc — 0.55 Unit V V V V V V Test Conditions Icc (s) — — 50 µA GND = 0 V, VI = Vcc or GND Icc (a) — — 120 mA IIH IIL CI — — — — — — 10 –10 10 µA µA pF GND = 0 V, CKO = 50 MHz VI = Vcc or GND GND = 0 V, VI = Vcc GND = 0 V, VI = 0 V TR XIN GND = 0 V, IOH = –4 mA GND = 0 V, IOL = 4 mA Measurement circuit; The direction of current flowing to the circuit is specified to be positive (no sign). REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 3 of 14 M66238FP Timing Requirements (Ta = 0 to 70°C, Vcc = 5 V ± 5%, GND = 0 V) Item CS width CS set up time CS hold time SCK width SIN set up time SIN hold time Clock input frequency Clock input duty Trigger input "H" pulse width Clock input rising time Clock input falling time Symbol tw (CS) tsu (CS-SCK) th (SCK-CS) tw (SCK) tsu (SIN-SCK) th (SCK-SIN) fin fiDUTY tw (TR) tr tf Min 1 50 50 25 25 25 7 40 200 — — Typ — — — — — — — — — — — Max — — — — — — 12 60 — 5 5 Unit µs ns ns ns ns ns MHz % ns ns ns Switching Characteristics (Ta = 0 to 70°C, Vcc = 5 V ± 5%, GND = 0 V, CL = 15 pF) Item VCO oscillation frequency Synchronous output frequency Synchronous accuracy (jitter) Synchronous clock output start Synchronous clock reversible output start One-shot pulse output start Synchronous clock output stop Synchronous clock reversible output stop One-shot pulse output width Synchronous clock output duty Synchronous clock reversible output duty Note: Symbol fvco fout ∆t tss (CKO) tss (CKOB) tss (PULSE) tsp (CKO) tsp (CKOB) tw (PULSE) foDUTY (CKO) foDUT (CKOB) Min 25 — — — — — — — n • tp – 10 40 40 Typ — — — — — — — — — — — Max 50 50 ±3 tlp + 200 tlp + 200 tlp + 200 40 40 n • tp + 10 60 60 tp = 1 / fout, tlp = tp × (100 – fvcoduty) / 100 The n value of one-shot pulse output width is set in the register. Measurement Circuit Input VCC Output Tested element PG Zo CL Notes: • Waveform for switching test Input pulse level XIN: 0 to Vcc, TR: 0 to 3 V Input pulse rising time: 3 ns Input pulse falling time: 3 ns Zo: 50 Ω Decision voltage Input voltage XIN: Vcc/2, Tr: 1.3 V Output voltage All outputs: Vcc/2 • Electrostatic capacitance: CL includes floating capacitance of connection and probe input capacitance. REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 4 of 14 Unit MHz MHz ns ns ns ns ns ns ns % % M66238FP List of Register Setting Commands A1 0 A0 0 1 0 1 1 Setting Setting of CKO/PLLO dividing ratio, PLL synthesizer 15-bit generation dividing ratio and reference clock generation 12-bit dividing ratio. Setting of one-shot pulse polarity and width, setting of trigger edge, HALT of entire M66238, HALT of charge pump and VCO, phase comparator output UP/DOWN, CKO/PLLO switching. Dummy trigger generation command Serial Data Write Timing CS SCLK SIN A0 A1 D0 D1 D2 Address bit REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 5 of 14 D3 D4 D5 D6 Data bit D26 D27 D28 D29 M66238FP Register Configuration 1. Clock frequency setting command Reference clock generation 12-bit division ratio, PLL synthesizer 15-bit division ratio and CKO/PLLO division ratio are set at address (A1, A0) = (0, 0). Data Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description 12-bit reference clock dividing ratio is set. D11 and D0 correspond to MSB and LSB, respectively. 11 K = Σ (Dk × 2k) Default 0 1 k=0 K: Reference clock dividing ratio 0 1 0 0 0 0 1 0 0 0 15-bit PLL synthesizer dividing ratio is set. D26 and D12 correspond to MSB and LSB, respectively. 26 N = Σ (Dn × 2n-12) 0 0 n = 12 N: PLL synthesizer dividing ratio REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 6 of 14 0 1 0 1 1 1 1 1 0 0 0 0 0 M66238FP Data Bit D27 Description 0 1 D28 0 1 D29 0 1 Setting of CKO/PLLO dividing ratios Dividing Ratio 1/1 1/2 1/4 1/8 1/16 1/32 REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 7 of 14 D29 0 0 0 0 1 1 D28 0 0 1 1 0 0 D27 0 1 0 1 0 1 PLLO/CKO Oscillator Frequency 25 MHz to 50 MHz 12.5 MHz to 25 MHz 6.25 MHz to 12.5 MHz 3.125 MHz to 6.25 MHz 1.563 MHz to 3.125 MHz 0.781 MHz to 1.563 MHz Default 0 1 0 M66238FP 2. Operating mode setting commands Address (A1, A0) = (1, 0) allows setting of one-shot pulse polarity and width, trigger edge, M66238 entire halt, charge pump and VCO halt, phase comparator UP/DOWN output, LPF cutoff, CKO/PLLO switching, VCO switching and charge pump switching. Data Bit D0 Description 0 1 D1 0 1 D2 D3 D4 0 1 0 1 0 1 D5 0 1 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 : D29 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Default 0 Setting of trigger edge D1 D0 0 0 1 1 0 1 0 1 Description Synchronizes with TR Synchronizes with TR Synchronizes with TR Synchronizes with TR CKO is stopped when TR = "H" CKO is stopped when TR = "L" CKO is output when TR = "H" CKO is output when TR = "L" When trigger occurs: spike of sync clock is not eliminated. When trigger occurs: spike of sync clock is eliminated (disabled when D1 = 1). Polarity of one-shot pulse: Negative pulse Polarity of one-shot pulse: Positive pulse Setting of one-shot pulse width D5 0 0 1 1 D4 0 1 0 1 Description CKO 2-cycle width CKO 4-cycle width CKO 8-cycle width CKO 16-cycle width CKO/PLLO pin: CKO output CKO/PLLO pin: PLLO output Entire M66238: Operating state Entire M66238: Halt state VCO: Operating state VCO: Halt state Charge pump: ON Charge pump: OFF Low pass filter: Operating state Low pass filter: Separated Normal use: Not output to outside Phase comparator UP/DOWN output enable Normal use VCO test circuit set Normal use Charge pump test circuit set Normal use 15-bit counter test clock enable Normal use Sync clock generator test clock enable Normal use Sync clock generator test input enable Normal use 12-bit counter test output enable Normal use 15-bit counter test output enable Normal use Sync clock generator trigger test output enable Normal use Sync clock generator test output enable In normal use: "0" set REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 8 of 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 0 M66238FP 3. Dummy trigger generating command The internal status of sync clock generator becomes unstable and a stable sync clock output (CKO) is not obtained after the power is turned on, after a reset is cleared or after an internal VCO oscillator frequency is set. To obtain a stable sync clock output, enter a trigger signal from the TR input after VCO oscillator becomes stable, or enter a dummy trigger generating command from the MCU. The PLL synthesizer oscillator frequency after the cancellation of a reset depends on a default (See the register configuration). Set the command for address (A1, A0) = (1, 1). Data Bit D0 Description 0 The command must be stored two times continuously when a dummy trigger is generated. For the first time, set the dummy trigger generating command with D0 = 1. For the second time, set the dummy trigger generating command with D0 = 0. The second setting becomes a sync edge and a clock begins to be output from CKO. After the first setting, CKO is in the halt state. In normal use: "0" 1 D1 ↓ D29 0 1 Default 0 0 ↓ 0 0 1 Operating Timing 1. Sync Clock Spike Non-removal Mode upon Occurrence of Trigger 1.1 Setting of Trigger Edge when D1 = 0 One-shot pulse start timing: 1st leading edge of CKO after TR fall One-shot pulse polarity: Negative pulse One-shot pulse width: 16 cycles of CKO CKO output dividing ratio: 1/2 division An example set for the condition of address (A1, A0) = (1, 0), data (D6, D5, D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0, 0, 0) is shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise of CKO. tlp tp = 1 / fvco Internal VCO oscillator clock tw (TR) TR tsp (CKO) ∆t tss (CKO) CKO SPIKE ∆t tp = 1 / fout PULSE tss (PULSE) tw (PULSE) REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 9 of 14 M66238FP 1.2 Setting of Trigger Edge when D1 = 1 One-shot pulse start timing: 1st leading edge of CKO after TR rise (except the rise of a spike which occurs when CKO is stopped). One-shot pulse polarity: Negative pulse One-shot pulse width: 16 cycles of CKO CKO output dividing ratio: 1/2 division An example set for the condition of address (A1, A0) = (1, 0), data (D6, D5, D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0, 1, 0) is shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise of CKO. tp = 1 / fvco tlp Internal VCO oscillator clock tw (TR) TR tsp (CKO) ∆t tss (CKO) CKO ∆t SPIKE tp = 1 / fout PULSE tw (PULSE) 2. Sync Clock Spike Removal Mode upon Occurrence of Trigger When address (A1, A0) = (1, 0) and data (D6, D5, D4, D3, D2, D1, D0) = (0, 1, 1, 0, 1, 0, 0), CKO with the first rise after occurrence of a trigger is output and then CKO stops. However, this mode is not available when D1 = 1 in trigger edge setting. Set a wide TR so that TR sync edge is entered 200 ns or more after CKO stops. tw (TR) TR 200 ns or more required ∆t tss (CKO) CKO 1st CKOB ∆t tss (CKOB) ∆t PULSE tss (PULSE) tw (PULSE) Notes: 1. 200 ns or more required 2. tss (CKO, CKOB, PULSE) is defined by input clock width "L" + α. In addition, the value of α denotes IC internal delay, and the values of α and tss are definite unless temperature, Vcc, etc. are changed, and tss variations at that time is defined as ∆t (sync accuracy: jitter). REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 10 of 14 M66238FP CKO/PLLO Output Frequency Range The M66238 requires an internal VCO oscillator frequency of 25 MHz to 50 MHz. Settings of dividing ratio K of 12-bit divider and dividing ratio N of 15-bit counter are required in order to determine the internal VCO oscillator frequency. The relation between the settings and the internal VCO oscillator frequency is shown below. Oscillator frequency fVCO = fin × N (MHz) K 11 K = Σ (Dk × 2k) k=0 26 N = Σ (Dn × 2n−12) n = 12 Note: 3. Setting of fin / K ≥ 100 kHz is recommended in consideration of the frequency accuracy characteristics of PLL output. Therefore, set the division ratio K of the 12-bit divider and the division ratio N of the 15-bit counter to meet the following conditions: 25 MHz ≤ fvco ≤ 50 MHz In addition, for PLLO and CKO, setting the division ratios of the sync/division circuit (synchronous clock generating area) to 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow the frequencies of 0.78 Hz to 50 MHz to be accommodated. REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 11 of 14 M66238FP Input Timing (1) Register Setting CS VCC 50% 0V tsu (CS-SCK) tw (SCK) tw (CS) th (SCK-CS) tw (SCK) VCC SCK 50% 50% 50% 0V tsu (SIN-SCK) th (SCK-SIN) VCC SIN 50% 50% 0V (2) Clock from Trigger Input and One-shot Pulse Output 3V 1.3 V TR 0V VOH CKO CKOB 50% VOL PULSE tss (3) Stop of Clock from Trigger Input 3V TR 1.3 V 0V CKO VOH CKOB 50% VOL tsp (4) Trigger Input Width 3.0 V TR 1.3 V 1.3 V 0V tw (TR) (5) One-shot Pulse Width VOH PULSE 50% 50% VOL tw (PULSE) REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 12 of 14 M66238FP Application Circuit Example Digital power supply Programmable Interface 1 32 2 31 3 30 4 29 5 28 6 27 8 1 MΩ 9 10 Crystal oscillator 30 pF NC 11 30 pF 7.5 kΩ 2 kΩ 26 Analog GND 24 23 22 21 NC 13 20 NC 14 19 15 18 16 17 1.2 kΩ 0.015 µF 25 12 Digital GND REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 13 of 14 M66238FP 7 Analog power supply Programmable Interface M66238FP Package Dimensions 32P2W-A Plastic 32pin 450mil SOP EIAJ Package Code SOP32-P-450-1.27 JEDEC Code — Weight(g) 0.67 32 Lead Material Alloy 42 e E HE e1 I2 17 b2 Recommended Mount Pad Symbol 16 1 A F D G e b A2 x A1 M L L1 y c z Z1 Detail G REJ03F0268-0200 Rev.2.00 Mar 18, 2008 Page 14 of 14 Detail F A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2 Dimension in Millimeters Min Nom Max — — 2.4 0.05 — — — 2.0 — 0.35 0.4 0.5 0.13 0.15 0.2 19.8 20.0 20.2 8.2 8.4 8.6 1.27 — — 11.63 11.93 12.23 0.3 0.5 0.7 1.765 — — — — 0.475 — — 0.625 — — 0.25 0.15 — — 0° 10° — 0.76 — — 11.43 — — 1.27 — — Sales Strategic Planning Div. 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