Application Manual AB-RTCMC-32.768kHz-B5GA-S3

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Application Manual
AB-RTCMC-32.768kHz-B5GA-S3
Real Time Clock/Calendar Module
with I2C Interface
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
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Tel: (949) 546-8000 Fax: (949) 546-8001
[email protected]
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CONTENTS
1.0 Overview................................................................................................................. ................................................................. 4
2.0 General Description ................................................................................................. ............................................................ 4
3.0 Block Diagram ......................................................................................................................................................................... 4
4.0 Pinout ................................................................................................................................................................................... 5
5.0 Pin Description ............................................................................................................................................................. 5
6.0 Functional Description ............................................................................................................................................................. 6
6.1 CLKOUT Output ................................................................................................................................................................... 6
7.0 Device Protection Diagram ....................................................................................................................................................... 6
8.0 Register Organization ............................................................................................................................................................... 7
8.1 Register Overview ................................................................................................................................................................. 7
8.2 Control Registers ................................................................................................................................................................... 7
8.2.1 Control/Status 1 (address 00h …bits description)......................................................................................................... 7
8.2.2 Control/Status 2 (address 01h …bits description)......................................................................................................... 8
8.3 Time and Date Registers ....................................................................................................................................................... 8
8.3.1 Seconds (address 02h …bits description)...................................................................................................................... 8
8.3.2 Minutes (address 03h …bits description)...................................................................................................................... 8
8.3.3 Hours (address 04h …bits description).......................................................................................................................... 9
8.3.4 Days (address 05h …bits description)........................................................................................................................... 9
8.3.5 Weekdays (address 06h …bits description)................................................................................................................... 9
8.3.6 Months/Century (address 07h …bits description)....................................................................................................... 10
8.3.7 Years (address 08h …bits description)........................................................................................................................ 10
8.4 Alarm Registers ................................................................................................................................................................... 11
8.4.1 Minute Alarm (address 09h …bits description)........................................................................................................... 11
8.4.2 Hour Alarm (address 0Ah …bits description)............................................................................................................. 11
8.4.3 Day Alarm (address 0Bh …bits description)............................................................................................................... 11
8.4.4 Weekday Alarm (address 0Ch …bits description)...................................................................................................... 11
8.5 CLKOUT Register ............................................................................................................................................................... 12
8.5.1 CLKOUT Frequency (address 0Dh …bits description).............................................................................................. 12
8.6 Timer Register ..................................................................................................................................................................... 12
8.6.1 Timer Control (address 0Eh …bits description).......................................................................................................... 13
8.6.2 Timer (address 0Fh …bits description)....................................................................................................................... 13
8.7 Register Reset Value ........................................................................................................................................................... 14
9.0 Detailed Functional Description ............................................................................................................................................. 15
9.1 Interrupt Output ................................................................................................................................................................... 15
9.1.1 Bits TF and AF............................................................................................................................................................. 15
9.1.2 Bits TIE and AIE.......................................................................................................................................................... 15
9.1.3 Countdown Timer Interrupt......................................................................................................................................... 15
9.2 Voltage Low Detector and Clock Monitor .......................................................................................................................... 16
9.3 Setting and Reading the Time …......................................................................................................................................... 16
9.4 Alarm Flag ........................................................................................................................................................................... 18
9.5 Stop Bit Function ................................................................................................................................................................. 19
9.5.1 First Increment of Time Circuits after Stop Bit Release.............................................................................................. 20
9.6 Reset .................................................................................................................................................................................... 20
10.0 Characteristics of the I2C Bus ............................................................................................................................................ 21
10.1 Bit Transfer ........................................................................................................................................................................ 21
10.2 Start and Stop Conditions .................................................................................................................................................. 21
10.3 System Configuration ........................................................................................................................................................ 22
10.4 Acknowledge ..................................................................................................................................................................... 23
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11.0 I2C Bus Protocol .................................................................................................................................................................... 24
11.1 Addressing ......................................................................................................................................................................... 24
11.2 Clock and Calendar Read and Write Cycles ..................................................................................................................... 24
11.2.1 Write Mode ............................................................................................................................................................... 24
11.2.2 Read Mode at Specific Address ............................................................................................................................... 25
11.2.3 Read Mode ................................................................................................................................................................ 25
11.3 Interface Watchdog Timer ................................................................................................................................................. 26
12.0 Absolute Maximum Rating ................................................................................................................................................... 26
13.0 Frequency Characteristics...................................................................................................................................................... 27
13.1 Frequency vs Temperature Characteristics ....................................................................................................................... 27
14.0 DC Characteristics................................................................................................................................................................. 28
15.0 I2C Timing Characteristics .................................................................................................................................................... 29
15.1 Timing Chart ..................................................................................................................................................................... 29
16.0 Recommended Reflow Temperature Characteristics............................................................................................................. 30
17.0 Packages ................................................................................................................................................................................ 31
17.1 Dimensions and Solderpad Layout .................................................................................................................................... 31
17.2 Marking and Pin 1 Index ................................................................................................................................................... 31
18.0 Packing Information .............................................................................................................................................................. 32
18.1 Carrier Tape ....................................................................................................................................................................... 32
18.2 Reel 7 Inch for 12mm Tape ............................................................................................................................................... 32
19.0 Handling Precautions for Crystals Modules with Embedded Crystals ................................................................................. 33
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AB-RTCMC-32.768kHz-B5GA-S3
I2C-Bus Interface Real Time Clock / Calendar Module
1.0 OVERVIEW
 RTC module with built-in crystal oscillating at 32.768 kHz
 400kHz two-wire I2C interface
 Wide Interface operating voltage: 1.8 – 5.5 V
 Wide clock operating voltage: 1.2 – 5.5 V
 Low power consumption: 250 nA typ @ 3.0V / 25°C
 Provides year, month, day, weekday, hours, minutes, seconds
 Alarm and Timer functions
 Century flag
 Low voltage detector, internal power on reset
 Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz, 32 Hz, 1 Hz)
 I2C slave address: read A3h, write A2h
 Small and compact package size: 3.7 x 2.5 x 0.9 mm. RoHS-compliant and 100% leadfree
2.0 GENERAL DESCRIPTION
The AB-RTCMC-32.768kHz-B5GA-S3 is a CMOS real time clock / calendar optimized for low power consumption. A
programmable clock output, interrupt output and voltage low detector are also provided. All address and data are transferred serially
via a two-line bi-directional I2C bus. Maximum bus speed is 400kbit/sec. The built-in word address register is incremented
automatically after each written or read data byte.
3.0 BLOCK DIAGRAM
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4.0 PINOUT
Pin #
1
2
3
4
5
Function
CLKOE
VDD
CLKOUT
SCL
SDA
Pin #
6
7
8
9
10
Function
INT
VSS
N.C
N.C.
N.C.
5.0 PIN DESCRIPTION
Pin No.
Pin Name
Function
1
CLKOE
2
VDD
3
CLKOUT
4
SCL
Serial Clock Input pin; requires pull-up resistor
5
SDA
Serial Data Input-Output pin; open-drain; requires pull-up resistor
6
INT
Interrupt Output pin; open-drain; active LOW
7
VSS
Ground
8
N.C.
Not Connected
9
N.C.
Not Connected
10
N.C.
Not Connected
CLKOUT enable/disable pin; enable is active HIGH; tie to GND when not using
CLKOUT
Positive supply voltage
Clock Output pin; push-pull
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6.0 FUNCTIONAL DESCRIPTION
The AB-RTCMC-32.768kHz-B5GA-S3 RTC module combines a RTC IC with on chip oscillator together with a 32.768 kHz quartz
crystal in a miniature ceramic package.
The AB-RTCMC-32.768kHz-B5GA-S3 contains sixteen 8-bit registers with an auto-incrementing address register, a frequency
divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, a timer, a voltage low
detector and a 400 kHz I2C bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers
(memory address 00h and 01h) are used as control and/or status registers. The memory addresses 02h through 08h are used as
counters for the clock function (seconds up to year counters). Address locations 09h through 0Ch contain alarm registers which
define the conditions for an alarm. Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control and
timer registers, respectively.
The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm, hour alarm, day alarm and weekday alarm
registers are all coded in BCD format.
When one of the RTC counters is read (memory locations 02h through 08h), the contents of all counters are frozen at the beginning
of a read cycle. Therefore, faulty reading of the clock / calendar during a carry condition is prevented.
6.1 CLKOUT OUTPUT
A programmable square wave is available at the CLKOUT pin. Frequencies of 32.768 kHz, 1024 Hz, 32 Hz and 1 Hz can be
generated for use as system clock, microcontroller clock or input to a charge pump. CLKOUT is a CMOS push-pull output, and if
disabled it becomes logic 0.
7.0 DEVICE PROTECTION DIAGRAM
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8.0 REGISTER ORGANIZATION
8.1 REGISTER OVERVIEW
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Function
Control/Status 1
Control/Status 2
Seconds
Minutes
Hours
Days
Weekdays
Months/Century
Years
Minute Alarm
Hour Alarm
Day Alarm
Weekday Alarm
CLKOUT Frequency
Timer Control
Timer
Bit 7
TEST1
N
VL
X
X
X
X
C
80
AE_M
AE_H
AE_D
AE_W
FE
TE
128
Bit 6
N
N
40
40
X
X
X
X
40
40
X
X
X
X
X
64
Bit 5
STOP
N
20
20
20
20
X
X
20
20
20
20
X
X
X
32
Bit 4
N
TI/TP
10
10
10
10
X
10
10
10
10
10
X
X
X
16
Bit 3
TESTC
AF
8
8
8
8
X
8
8
8
8
8
X
X
X
8
Bit 2
N
TF
4
4
4
4
4
4
4
4
4
4
4
X
X
4
Bit 1
N
AIE
2
2
2
2
2
2
2
2
2
2
2
FD1
TD1
2
Bit 0
N
TIE
1
1
1
1
1
1
1
1
1
1
1
FD0
TD0
1
Bit 2
N
Bit 1
N
Bit 0
N
Bit positions labeled as “X” are not implemented.
Bit positions labeled as “N” should always be written with logic 0.
8.2 CONTROL REGISTERS
8.2.1 CONTROL / STATUS 1 (address 00h…bits description)
Address
00h
Function
Control/Status 1
Bit
Symbol
7
TEST1
6
N
Value
0 1)
1
0 2)
0
5
1)
STOP
1
4
N
3
TESTC
2 to 0
N
0
2)
0
1 1)
000 2)
Bit 7
TEST1
Bit 6
N
Bit 5
STOP
Bit 4
N
Bit 3
TESTC
Description
Must be set to logic 0 for normal operations
Test mode
Default value
RTC source clock runs
RTC divider chain flip-flops are asynchronously set to logic 0
The RTC clock is stopped (CLKOUT at 32.768kHz is still available)
Default value
Must be set to logic 0 for normal operations
Test mode
Default value
Reference
See section
9.5
1) Default value.
2) Bits labeled as “N” should always be written with logic 0.
Note:
The two bits: TEST1 and TESTC are for device testing. Make sure TEST1 and TESTC are set to 0 during normal operation. If
accidentally set to 1, they may modify the clock data or result in abnormal time.
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8.2.2 CONTROL / STATUS 2 (address 01h…bits description)
Address
01h
Bit
7 to 5
Function
Control/Status 2
Symbol
N
Value
000 2)
0
4
TI/TP
3
AF
2
TF
1
AIE
0
TIE
1)
1
0
1)
1
0
1)
1
0
1)
1
0
1)
1
Bit 7
N
Bit 6
N
Bit 5
N
Bit 4
TI/TP
Bit 3
AF
Bit 2
TF
Bit 1
AIE
Description
Bit 0
TIE
Reference
Default value
INT is active when TF is active (subject to the status of TIE)
See section
8.6 and 9.1
INT pulses active according to 9.1.3 (subject to the status of TIE)
Remark: if AF and AIE are active then INT will be permanently
active
Alarm flag inactive
Alarm flag active
Timer flag inactive
Timer flag active
Alarm interrupt disabled
Alarm interrupt enabled
Timer interrupt disabled
Timer interrupt enabled
See section
9.1
See section
9.1
See section
9.1
See section
9.1
1) Default value.
2) Bits labeled as “N” should always be written with logic 0.
8.3 TIME AND DATE REGISTERS
8.3.1 SECONDS (address 02h…bits description)
Address
02h
Function
Seconds
Bit
Symbol
7
VL
6 to 0
Seconds
Value
0
1 1)
0 to 59
Bit 7
VL
Bit 6
40
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0
1
Bit 1
2
Bit 0
1
Description
Clock integrity is guaranteed
Integrity of clock information is not guaranteed
These registers hold the current seconds coded in BCD format
1) Startup value.
8.3.2 MINUTES (address 03h…bits description)
Address
03h
Bit
7
6 to 0
Function
Minutes
Symbol
X
Minutes
Value
0 to 59
Bit 7
X
Bit 6
40
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Description
Unused
These registers hold the current minutes coded in BCD format
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8.3.3 HOURS (address 04h…bits description)
Address
04h
Bit
7 to 6
5 to 0
Function
Hours
Symbol
X
Hours
Value
0 to 23
Bit 7
X
Bit 6
X
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0
1
Bit 1
2
Bit 0
1
Bit 1
2
Bit 0
1
Description
Unused
These registers hold the current hours coded in BCD format
8.3.4 DAYS (address 05h…bits description)
Address
05h
Bit
7 to 6
5 to 0
Function
Days
Symbol
X
Days
Value
1 to 31
Bit 7
X
Bit 6
X
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Description
Unused
These registers hold the current day coded in BCD format
8.3.5 WEEKDAYS (address 06h…bits description)
Address
06h
Bit
7 to 3
2 to 0
Function
Weekdays
Symbol
X
Weekdays
Bit 7
X
Value
0 to 6
Weekday 1)
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Bit 7
X
X
X
X
X
X
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
4
Description
Unused
These registers hold the current weekday coded in BCD format
Bit 6
X
X
X
X
X
X
X
Bit 5
X
X
X
X
X
X
X
Bit 4
X
X
X
X
X
X
X
Bit 3
X
X
X
X
X
X
X
Bit 2
0
0
0
0
1
1
1
Bit 1
0
0
1
1
0
0
1
Bit 0
0
1
0
1
0
1
0
1) Definition may be re-assigned by the user.
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8.3.6 MONTHS/CENTURY (address 07h…bits description)
Address
07h
Bit
7
6 to 5
4 to 0
Function
Months
Symbol
C
1)
X
Months
Value
0 2)
1
1 to 12
Month
January
February
March
April
May
June
July
August
September
October
November
December
Bit 7
C
Bit 6
X
Bit 5
X
Bit 4
10
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0
1
Description
Indicates the century is x
Indicates the century is x+1
unused
These registers hold the current month coded in BCD format
Bit 7
X
X
X
X
X
X
X
X
X
X
X
X
Bit 6
X
X
X
X
X
X
X
X
X
X
X
X
Bit 5
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
0
0
0
0
0
0
0
0
0
1
1
1
Bit 3
0
0
0
0
0
0
0
1
1
0
0
0
Bit 2
0
0
0
1
1
1
1
0
0
0
0
0
Bit 1
0
1
1
0
0
1
1
0
0
0
0
1
Bit 0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0
1
1) This bit may be re-assigned by the user.
2) This bit is toggled when the register Years overflows from 99 to 00.
8.3.7 YEARS (address 08h…bits description)
Address
08h
Bit
7 to 0
Function
Years
Symbol
Years
Value
00 to 99
Bit 7
80
Bit 6
40
Description
These registers hold the current year coded in BCD format
1)
1) When the register Years overflows from 99 to 00, the century bit C in the register Months is toggled.
Note:
The AB-RTCMC-32.768kHz-B5GA-S3 compensates for leap years by adding a 29th day to February if the year counter contains a
value which is divisible by 4, including 00.
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8.4 ALARM REGISTERS
8.4.1 MINUTE ALARM (address 09h…bits description)
Address
09h
Function
Minute Alarm
Bit 7
AE_M
Bit
Symbol
7
AE_M
6 to 0
Minute Alarm
Value
0
1 1)
0 to 59
Bit 6
40
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0
1
Bit 1
2
Bit 0
1
Bit 1
2
Bit 0
1
Bit 1
2
Bit 0
1
Description
Minute alarm is enabled
Minute alarm is disabled
Minute Alarm information coded in BCD format
1) Default value.
8.4.2 HOUR ALARM (address 0Ah…bits description)
Address
0Ah
Function
Hour Alarm
Bit 7
AE_H
Bit
Symbol
7
AE_H
6
5 to 0
X
Hour Alarm
Value
0
1 1)
0 to 23
Bit 6
X
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Description
Hour alarm is enabled
Hour alarm is disabled
unused
Hour Alarm information coded in BCD format
1) Default value.
8.4.3 DAY ALARM (address 0Bh…bits description)
Address
0Bh
Function
Day Alarm
Bit 7
AE_D
Bit
Symbol
7
AE_D
6
5 to 0
X
Day Alarm
Value
0
1 1)
1 to 31
Bit 6
X
Bit 5
20
Bit 4
10
Bit 3
8
Bit 2
4
Description
Day alarm is enabled
Day alarm is disabled
unused
Day Alarm information coded in BCD format
1) Default value.
8.4.4 WEEKDAY ALARM (address 0Ch…bits description)
Address
0Ch
Function
Weekday Alarm
Bit 7
AE_W
Bit
Symbol
7
AE_W
6 to 3
2 to 0
X
Weekday Alarm
Value
0
1 1)
0 to 6
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
4
Description
Weekday alarm is enabled
Weekday alarm is disabled
unused
Weekday Alarm information coded in BCD format
1) Default value.
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8.5 CLKOUT REGISTER
A programmable square wave output is available at CLKOUT pin. Operation is controlled by the FE bit in register CLKOUT
Frequency and Clock Output Enable pin (CLKOE). To enable CLKOUT, CLKOE pin must be set HIGH.
Frequencies of 32.768 kHz (default), 1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock,
input to a charge pump, or for calibration of the oscillator.
8.5.1 CLKOUT FREQUENCY (address 0Dh…bits description)
Address
0Dh
Function
CLKOUT Frequency
Bit
Symbol
7
FE
6 to 2
1 to 0
X
FD [1:0]
CLKOUT Frequency
32.768kHz
1024Hz
32Hz
1Hz
Bit 7
FE
Value
0
1 1)
00 1) to 11
Bit 7
X
X
X
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
FD1
Bit 0
FD0
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Description
The CLKOUT output is inhibited and set to logic 0
The CLKOUT output is activated
unused
CLKOUT Frequency selection
Bit 6
X
X
X
X
Bit 5
X
X
X
X
Bit 4
X
X
X
X
Bit 3
X
X
X
X
Bit 2
X
X
X
X
1) Default value.
8.6 TIMER REGISTER
The 8-bit countdown timer register at address 0Fh is controlled by the timer control register at address 0Eh. The Timer Control
register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 sec, or 1/60 Hz) and enables / disables the
timer. The timer counts down from a software loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer
Flag TF to logic 1. The TF may only be cleared using the interface.
The generation of interrupts from the timer function is controlled via bit TIE (Control / Status 2 register). If bit TIE is enabled, the
INT pin follows the condition of bit TF. The interrupt may be generated as a pulsed signal every countdown period or as a
permanent active signal which follows the condition of the Timer Flag TF. TI/TP (Control / Status 2 register) is used for this mode
control. When reading the timer, the current countdown value is returned.
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8.6.1 TIMER CONTROL (address 0Eh…bits description)
Address
0Eh
Function
Timer Control
Bit
Symbol
7
TE
6 to 2
1 to 0
X
TD [1:0]
Timer Frequency
4096Hz
64Hz
1Hz
1
60
Hz
Bit 7
TE
Value
0 1)
1
00 to 11 1)
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
TD1
Bit 0
TD0
Description
Timer is disabled
Timer is enabled
unused
Timer source clock frequency selection 2)
Bit 7
X
X
X
Bit 6
X
X
X
Bit 5
X
X
X
Bit 4
X
X
X
Bit 3
X
X
X
Bit 2
X
X
X
Bit 1
0
0
1
Bit 0
0
1
0
X
X
X
X
X
X
1
1
1) Default value.
2) These bits determine the source clock frequency for the countdown timer. when not in use, TD1/TD0 should be set to 1/60Hz for power saving.
8.6.2 TIMER (address 0Fh…bits description)
Address
0Fh
Function
Timer
Bit 7
128
Bit
Symbol
Value
7 to 0
Timer
00h to FFh
Bit 6
64
Bit 5
32
Bit 4
16
Bit 3
8
Bit 2
4
Bit 1
2
Bit 0
1
Description
Countdown value = n
Countdown period 
n
Source ClockFrequency
Note:
For accurate read back of the countdown value, the I2C bus clock (SDA) must be operating at a frequency of at least twice the
selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
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8.7 REGISTER RESET VALUES
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Function
Control/Status 1
Control/Status 2
Seconds
Minutes
Hours
Days
Weekdays
Months/Century
Years
Minute Alarm
Hour Alarm
Day Alarm
Weekday Alarm
CLKOUT Frequency
Timer Control
Timer
Bit 7
0
0
1
X
X
X
X
X
X
1
1
1
1
1
0
X
Bit 6
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 5
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 3
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 2
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 1
0
0
X
X
X
X
X
X
X
X
X
X
X
0
1
X
Bit 0
0
0
X
X
X
X
X
X
X
X
X
X
X
0
1
X
Bit positions labeled as “X” are undefined at power-on and unchanged by subsequent resets.
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9.0 DETAILED FUNCTIONAL DESCRIPTION
9.1 INTERRUPT OUTPUT
9.1.1 BITS TF AND AF
When an alarm occurs, AF is set to 1. Similarly, at the end of a timer countdown, TF is set to 1. These bits maintain their value unit
overwritten using the interface. If both timer and alarm are required in the application, the source of the interrupt can be determined
by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND in performed during a write access.
Note:
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
9.1.2 BITS TIE AND AIE
These bits activate or deactivate the generation of an interrupt when TF or AF is asserted respectively. The interrupt is the logical OR
of these two conditions when both AIE and TIE are set.
9.1.3 COUNTDOWN TIMER INTERRUPT
The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the
countdown timer and on the countdown value “n”. As a consequence, the width of the interrupt pulse varies.
INT operation (bit TI/TP = 1)1)
Source Clock
4096Hz
64Hz
1Hz
1
60
Hz
INT period [s]
n=1
1
2)
8192
s
n>1
1
4096
1
s
128
1
1
1
64
s
1
64
s
1
64
s
64
s
64
s
s
1) TF and INT become active simultaneously.
2) n = loaded countdown value. Timer is stopped when n = 0.
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9.2 VOLTAGE LOW DETECTOR AND CLOCK MONITOR
The AB-RTCMC-32.768kHz-B5GA-S3 has an on-chip voltage low detector. When VDD drops below VLOW, the VL (Voltage Low)
flag is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using the
interface.
The VL flag is intended to detect the situation when VDD is decreasing slowly; for example under battery operation. Should the
oscillator stop or VDD reach VLOW before power is reasserted, then the VL flag will be set. This indicates that the time is possibly
corrupted.
9.3 SETTING AND READING THE TIME
Data flow and data dependencies starting from 1 Hz clock tick
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During read / write operations, the time counting circuits (memory locations 02h through 08h) are blocked, in order to prevent the
following:
 Faulty writing or reading of the clock and calendar during a carry condition
 Incrementing the time registers during the read cycle
After this read / write access is completed, the time circuit is released again and any pending request to increment the time counters
that occurred during the read access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed
within 1 second.
As a consequence of this method, it is very important to make a read or write access in one go. This means, setting or reading
seconds through years should be made in one single access. Failing to comply with this method, could result in the time becoming
corrupted.
As an example, if the time (seconds through hours) is set in one access, and then, in a second access the date is set, it is possible that
the time may be incremented between the two accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Send a START condition and the slave address for write (A2h)
Set the address pointer to 2 (seconds) by sending 02h
Send a RE-START condition or STOP followed by START
Send the slave address for read (A3h)
Read the seconds
Read the minutes
Read the hours
Read the days
Read the weekdays
Read the century and months
Read the years
Send a STOP condition
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9.4 ALARM FLAG
By clearing the MSB of one or more of the alarm registers AE_x (Alarm Enable), the corresponding alarm condition(s) are active.
When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an interrupt ( INT ). The AF is cleared using the
interface.
The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is loaded with a valid
minute, hour, day or weekday and its corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with the
current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF in register Control / Status 2)
is set to logic 1.
The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT pin follows the
condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared it will only be set again when the
time increments to match the alarm condition once more. Alarm registers which have their AE_x bit at logic 1 are ignored.
1) Only when all enabled alarm settings are matching. It’s only on increment to a matched case that the alarm flag is set.
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9.5 STOP BIT FUNCTION
The function of the STOP bit is to allow an accurate starting of the time circuits. The STOP bit function will cause the upper part of
the prescaler to (F2 to F14) to be held in reset and thus no 1 Hz ticks will be generated. The time circuits can then be set and will not
increment until the STOP bit is released.
The STOP bit function will not affect the 32.768 kHz output on CLKOUT, but will stop the generation of 1024 Hz, 32 Hz and 1 Hz.
The lower two stages of the prescaler (F0 and F1) are not reset and as the I2C bus is asynchronous to the crystal oscillator, the
accuracy of re-starting the time circuits will be between zero and one 8192 Hz cycle.
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9.5.1 FIRST INCREMENT OF TIME CIRCUITS AFTER STOP BIT RELEASE
Bit
Prescaler Bits 1)
Time
1Hz Tick
Comment
STOP
F0F1 – F2 to F14
hh:mm:ss
Clock is running normally
0
01-0 0001 1101 0100
12:45:12 Prescaler counting normally
STOP bit is activated by user. F0 and F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12 Prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00 Prescaler is reset; time circuits are frozen
STOP bit is released by user
XX-0 0000 0000 0000
08:00:00 Prescaler is now running
XX-1 0000 0000 0000
08:00:00 XX-0 1000 0000 0000
08:00:00 XX-1 1000 0000 0000
08:00:00 :
:
:
11-1 1111 1111 1110
08:00:00 00-0 0000 0000 0001
08:00:01 0 to 1 transition of F14 increments the time circuits
0
10-0 0000 0000 0001
08:00:01 :
:
:
11-1 1111 1111 1111
08:00:01 00-0 0000 0000 0000
08:00:01 10-0 0000 0000 0000
08:00:01 :
:
:
11-1 1111 1111 1110
08:00:01 00-0 0000 0000 0001
08:00:02 0 to 1 transition for F14 increments the time circuits
1) F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by
the prescaler bits F0 and F1 not being reset and the unknown state of the 32.768 kHz clock.
9.6 RESET
The AB-RTCMC-32.768kHz-B5GA-S3 includes an internal reset circuit which is active whenever the oscillator is stopped. In the
reset state, the I2C bus logic is initialized including the address pointer and all registers are set according to 8.7. I 2C bus
communication is not possible during reset.
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10.0 CHARACTERISTICS OF THE I2C BUS
The I2C bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data Line
(SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be
initiated only when the bus is not busy.
10.1 BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse, as changes in the data line at this time will be interpreted as a control signal. Data changes should be executed during the
LOW period of the clock pulse.
10.2 START AND STOP CONDITIONS
Both SDA data and SCL clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the STOP condition (P).
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10.3 SYSTEM CONFIGURATION
Since multiple devices can be connected with the I 2C bus, all I2C bus devices have a fixed and unique device number built-in to
allow individual addressing of each device.
The device that controls the I2C bus is the Master; the devices which are controlled by the Master are the Slaves. A device generating
a message is a Transmitter; a device receiving a message is the Receiver. The AB-RTCMC-32.768kHz-B5GA-S3 acts as a SlaveReceiver or Slave-Transmitter.
Before any data is transmitted on the I2C bus, the device which should respond is addressed first. The addressing is always carried
out with the first byte transmitted after the start procedure. The clock signal SCL is only an input signal, but the data signal SDA is a
bidirectional line.
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10.4 ACKNOWLEDGE
There is no limit to the numbers of data bytes transmitted between the START and STOP conditions. Each byte (of 8 bits) is
followed by an acknowledge cycle. Therefore, the Master generates an extra acknowledge clock pulse.
The acknowledge bit is a HIGH level signal put on the SDA line by the Transmitter-Device, the Receiver-Device must pull down the
SDA line during the acknowledge clock pulse to confirm the correct reception of the last byte.
Either a Master-Receiver or a Slave-Receiver which is addressed must generate an acknowledge after the correct reception of each
byte. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse (setup and hold times must be taken into consideration).
If the Master is addressed as Receiver, it can stop data transmission by not generating an acknowledge on the last byte that has been
sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line HIGH to enable the Master to generate
a STOP condition.
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11.0 I2C BUS PROTOCOL
11.1 ADDRESSING
Before any data is transmitted on the I2C bus, the device which should respond is addressed first. The addressing is always carried
out with the first byte transmitted after the start procedure.
The AB-RTCMC-32.768kHz-B5GA-S3 acts as a Slave-Receiver or Slave-Transmitter. Therefore, the clock signal SCL is only an
input signal, but the data signal SDA is a bidirectional line.
11.2 CLOCK AND CALENDAR READ AND WRITE CYCLES
11.2.1 WRITE MODE
Master transmits to Slave-Receiver at specified address. The Word Address is 4-bit value that defines which register is to be accessed
next. The upper four bits of the Word Address are not used. After reading or writing one byte, the Word Address is automatically
incremented by 1.
1) Master sends out the “Start Condition”.
2) Master sends out the “Slave Address”, A2h for the AB-RTCMC-32.768kHz-B5GA-S3; the R/ W bit in write mode.
3) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3.
4) Master sends out the “Word Address” to the AB-RTCMC-32.768kHz-B5GA-S3.
5) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3.
6) Master sends out the “data” to write to the specified address in step 4).
7) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3.
8) Steps 6) and 7) can be repeated if necessary. The address will be incremented automatically in the
AB-RTCMC-32.768kHz-B5GA-S3.
9) Master sends out the “Stop Condition”.
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11.2.2 READ MODE AT SPECIFIC ADDRESS
Master reads data after setting Word Address
1) Master sends out the “Start Condition”.
2) Master sends out the “Slave Address”, A2h for the AB-RTCMC-32.768kHz-B5GA-S3; the R/ W bit in write mode.
3) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3.
4) Master sends out the “Word Address” to the AB-RTCMC-32.768kHz-B5GA-S3.
5) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3.
6) Master sends out the “Start Condition”. “Stop Condition” has not been sent.
7) Master sends out the “Slave Address”, A3h for the AB-RTCMC-32.768kHz-B5GA-S3; the R/ W bit in read mode.
8) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3. At this point, the Master becomes a Receiver, the Slave
becomes the Transmitter.
9) The Slave sends out the “data” from the Word Address specified in step 4).
10) Acknowledgement from the Master.
11) Steps 9) and 10) can be repeated if necessary. The address will be incremented automatically in the AB-RTCMC32.768kHz-B5GA-S3.
12) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the last byte that has
been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line HIGH to enable the
Master to generate a stop condition.
13) Master sends out the “Stop Condition”.
11.2.3 READ MODE
Master reads Slave-Transmitter immediately after first byte
1) Master sends out the “Start Condition”.
2) Master sends out the “Slave Address”, A3h for the AB-RTCMC-32.768kHz-B5GA-S3; the R/ W bit in read mode.
3) Acknowledgement from the AB-RTCMC-32.768kHz-B5GA-S3. At this point, the Master becomes a Receiver, the Slave
becomes the Transmitter
4) The AB-RTCMC-32.768kHz-B5GA-S3sends out the “data” from the last accessed Word Address incremented by 1.
5) Acknowledgement from the Master.
6) Steps 4) and 5) can be repeated if necessary. The address will be incremented automatically in the
AB-RTCMC-32.768kHz-B5GA-S3.
7) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the last byte that has
been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line HIGH to enable the Master
to generate a stop condition.
8) Master sends out the “Stop Condition”.
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11.3 INTERFACE WATCHDOG TIMER
During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes
locked and does not clear the interface, the AB-RTCMC-32.768kHz-B5GA-S3 has a built in watchdog timer. Should the interface be
active for more than 1 s from the time a valid slave address is transmitted, then the AB-RTCMC-32.768kHz-B5GA-S3will
automatically clear the interface and allow the time counting circuits to continue counting.
The watchdog is implemented to prevent the excessive loss of time due to interface access failure e. g. if main power is removed
from a battery backup system during an interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger between 1 s and 2 s
after receiving a valid slave address.
12.0 ABSOLUTE MAXIMUM RATING
Parameters
Symbol
Conditions
Min.
Max.
Units
VDD
>GND / <VDD
-0.5
+6.5
V
Input Voltage
VI
Input Pin
VSS-0.5
VDD +0.5
V
Output Voltage
VO
INT pin
VSS -0.5
VDD +0.5
V
Supply Current
IDD; ISS
VDD Pin
-50
+50
mA
-10
+10
mA
-10
+10
mA
±3500
±250
V
100
mA
-40
+85
ºC
-55
+125
ºC
Supply Voltage
DC Input Current
II
DC Output Current
IO
Electro Static Discharge Voltage
Latch-up Current
VESD
ILU
Operating Ambient Temperature Range
TOPR
Storage Temperature Range
TSTO
HBM
MM
1)
2)
All pins 3)
Stored as bard product
1) Pass level; Human Body Model (HBM), according to JESD22-A114.
2) Pass level; Machine Model (MM), according to JESD22-A115.
3) Pass level; latch-up testing, according to JESD78 at maximum ambient temperature (Tamb(max) = +85°C).
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13.0 FREQUENCY CHARACTERISTICS
Parameters
Symbol
Frequency Precision
∆F/F
Frequency vs Voltage Characteristics
∆F/V
Frequency vs Temp. Characteristics
∆F/FOPR
Turnover Temperature
Conditions
TAMB=+25°C;
VDD=3.0V
TAMB=+25°C;
VDD=1.8~5.5V
Tref=+25°C; VDD=3.0V
TO
∆F/F
At +25°C
Oscillation Start-up Time
TSTART
At +25°C
CLKOUT duty cycle
δCLKOUT
At +25°C
Aging first year
Typ.
Max.
Units
±10
±20
ppm
±0.8
±1.5
ppm/V
-0.035ppm/°C2 (TOPRTO)2 ±10%
+25
±5
ppm
°C
±3
ppm
350
500
ms
50
40/60
%
13.1 FREQUENCY VS. TEMPERATURE CHARACTERISTICS
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14.0 DC CHARACTERISTICS
Parameters
Symbol
Conditions
Min.
Typ.
Max.
Units
Supplies
Supply Voltage
VDD
Current Consumption
IDDO
2
I C bus active
1) 2) 3)
Current Consumption
I2C bus inactive (fSCL=0Hz)
CLKOUT disabled
Tamb= +25°C
IDD
1) 2) 3)
Current Consumption
I2C bus inactive (fSCL=0Hz)
CLKOUT disabled
TOPR= -40 ~ +85°C
Current Consumption
IDD
3)
I2C bus inactive (fSCL=0Hz)
CLKOUT enabled (32.768kHz)
Load = 7.5pF/Tamb= +25°C
IDD32k
I2C bus inactive
TAMB=+25°C
I2C bus active
fSCL=400kHz
For clock data integrity
TAMB=+25°C
fSCL=400kHz
1.2
5.5
1.8
5.5
VLOW
5.5
fSCL=100kHz
V
800
µA
200
µA
VDD = 5.0V
2)
275
550
nA
VDD = 3.0V
2)
250
500
nA
VDD = 2.0V
2)
225
450
nA
VDD = 5.0V
500
750
nA
VDD = 3.0V
400
650
nA
VDD = 2.0V
400
600
nA
VDD = 5.0V
2.5
3.4
µA
VDD = 3.0V
1.5
2.2
µA
VDD = 2.0V
1.1
1.6
µA
Inputs
LOW Level Input Voltage
VIL
VSS-0.5
30%VDD
V
HIGH Level Input Voltage
VIH
70%VDD
VDD+0.5
V
+1
µA
7
pF
Pin: SDA
-3
mA
Pin: INT
-1
mA
Pin: CLKOUT
-1
mA
IOH
Pin: CLKOUT
1
mA
ILO
VO = VDD or VSS
+1
µA
+85
°C
1.0
V
Input Leakage Current
Input Capacitance
4)
IL
VI = VDD or VSS
-1
0
CI
Outputs
LOW Level Output Current
VOL = 0.4V; VDD = 5V
HIGH Level Output Current
VOH = 4.6V; VDD = 5V
Output Leakage Current
IOL
-1
0
Operating Temperature Range
Operating Temperature Range
TOPR
-40
Voltage Detector
Low Voltage
VLOW
TAMB=+25°C
0.9
1) Timer source clock = 1/60 Hz.
2) CLKOUT disabled (FE = 0 or CLKOE = 0).
3) VIL and VIH with an input voltage swing of VSS to VDD.
4) Tested on sample basis.
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
Page (28) of (33)
30332 Esperanza
Rancho Santa Margarita, CA-92688
Tel: (949) 546-8000 Fax: (949) 546-8001
[email protected]
[email protected]_________________________
15.0 I2C BUS TIMING CHARACTERISTICS
Parameters
1)
SCL clock frequency
Symbol
Min.
fSCL
Typ.
Max.
Units
400
kHz
Hold time (repeated) START condition
tHD;STA
0.6
µs
Setup time for repeated START condition
tSU;STA
0.6
µs
LOW period of SCL clock
tLOW
1.3
µs
HIGH period of SCL clock
tHIGH
0.6
µs
Bus free time between STOP and START condition
tBUF
1.3
µs
Rise time of both SDA and SCL signals
tr
0.3
µs
Fall time of both SDA and SCL signals
tf
0.3
µs
Capacitive load for each bus line
Cb
400
pF
Data setup time
tSU;DAT
100
ns
Data hold time
tHD;DAT
0
ns
Setup time for STOP condition
tSU;STO
0.6
µs
Spike pulse width
tw(spike)
50
ns
1) All timing values are valid within the operating supply voltage at ambient temperature and referenced to V IL and VIH with an input voltage swing
of VSS to VDD.
15.1 TIMING CHART
Note:
The I2C BUS access time between a START and a START condition or between a START and a STOP condition to this device must
be less than one second.
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
Page (29) of (33)
30332 Esperanza
Rancho Santa Margarita, CA-92688
Tel: (949) 546-8000 Fax: (949) 546-8001
[email protected]
[email protected]_________________________
16.0 RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING)
Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”
Temperature
Symbol
Conditions
Units
TSmax to TP
3°C/second max
°C/s
Tcool
6°C/second max
°C/s
T to-peak
8 minutes max
m
Temperature Min
TSmin
150
°C
Temperature Max
TSmax
200
°C
Time Tsmin to Tsmax
ts
60 ~ 180
sec
Temperature Liquidus
TL
217
°C
Time above Liquidus
tL
60 ~150
sec
Peak Temperature
TP
260
°C
Time within 5°C of Peak Temperature
tP
20 ~ 40
sec
Average Ramp-up Rate
Ramp Down Rate
Time 25°C to Peak Temperature
Preheat
Time Above Liquidus
Peak Temperature
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
Page (30) of (33)
30332 Esperanza
Rancho Santa Margarita, CA-92688
Tel: (949) 546-8000 Fax: (949) 546-8001
[email protected]
[email protected]_________________________
17.0 PACKAGES
17.1 DIMENSIONS AND SOLDERPADS LAYOUT
All dimensions are in mm.
17.2 MARKING AND PIN #1 INDEX
MYWWXX
Pin 1 Indicator
8564
Product Code
M: Internal Code
Y: Year. e.g. 3 for 2013
WW: Week. e.g 08 for the 8th week of the year
XX: Lot Code
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
Page (31) of (33)
30332 Esperanza
Rancho Santa Margarita, CA-92688
Tel: (949) 546-8000 Fax: (949) 546-8001
[email protected]
[email protected]_________________________
18.0 PACKING INFO
18.1 CARRIER TAPE
12 mm Carrier-Tape:
Cover Tape:
Material:
Base Material:
Adhesive Material:
Polystyrene / Butadine or Polystyrol black, conductive
Polyester, conductive 0.061 mm
Pressure-sensitive Synthetic Polymer
All dimensions are in mm.
Tape Leader and Trailer: 300 mm minimum.
18.2 REEL 7 INCH FOR 12MM TAPE
7” Reel:
Material:
Qty/Reel:
Plastic, Polystyrol
1000pcs
All dimensions are in mm.
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
Page (32) of (33)
30332 Esperanza
Rancho Santa Margarita, CA-92688
Tel: (949) 546-8000 Fax: (949) 546-8001
[email protected]
[email protected]_________________________
19.0 HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS
The built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package is evacuated and
hermetically sealed in order for the crystal blank to function undisturbed from air molecules, humidity and other influences.
Shock and vibration
Keep the crystal from being exposed to excessive mechanical shock and vibration. Abracon guarantees that the crystal will bear a
mechanical shock of 5000g / 0.3 ms.
The following special situations may generate either shock or vibration:
Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router. These machines
sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency close to 32.768 kHz. This might cause
breakage of crystal blanks due to resonance. Router speed should be adjusted to avoid resonant vibration.
Ultrasonic Cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damages crystals due to mechanical
resonance of the crystal blank.
Overheating, rework high-temperature-exposure
Avoid overheating the package. The package is sealed with a sealring consisting of 80% Gold and 20% Tin. The eutectic melting
temperature of this alloy is at 280°C. Heating the sealring up to >280°C will cause melting of the metal seal which then, due to the
vacuum, is sucked into the cavity forming an air duct. This happens when using hot-air-gun set at temperatures >300°C.
Use the following methods for re-work:
• Use a hot-air- gun set at 270°C
• Use 2 temperature-controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints from both sides of the
package at the same time, remove part with tweezers when pad solder is liquid.
___________________________________________________________________________________________
Abracon Corporation (www.abracon.com)
Page (33) of (33)