TECHNICAL DATA AUTOMOTIVE DIGITAL CLOCK IC IN7100MQ DESCRIPTION IN7100 is a automotive digital clock, CMOS LSI. It drives fluorescent indicator panel directly. It can be driven by a 4.194304 MHz crystal oscillator or an external clock signal (1024 Hz). It has 4-ways display brightness control function and its display format is 12 hours. Semicon IN7100MQ OYWW FEATURES • 4.194304 MHz crystal oscillator • 4-ways display brightness control ( Segment signal duty: 1, 1/4, 1/8, 1/16 ) • Hours and Minutes Setting • ± 30 seconds auto correction • 1024 Hz external clock drive • 1024 Hz SIGNAL output • Segment Output: P-channel open drain • 40 DIP package MS-011AC MQFP-44 ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) Parameter Power Supply Voltage Symbol Specification Unit VDD - VSS − 0.5 ~ + 8.0 V VIN VSS − 0.3 ~ VDD + 0.3 V VOUT VDD − 30 ~ VDD + 0.3 V Ta − 40 ~ + 85 °C TSTG − 55 ~ + 125 °C Input Voltage Output Voltage Operating Temperature Storage Temperature DC CHARACTERISTICS (Ta=25°C, RH≤70%, CD=CG=15pF, Xtal=4.194304MHz) Characteristic Power Supply Voltage Power Supply Current Leakage Current High Level Output Current(1) High Level Output Current(2) Low Level Output Current(3) High Level Input Current(4) High Level Input Current(5) External Clock Duty OSC. Feedback Resistance Symbol VDD-VSS IDD IOFF IOH1 IOH2 IOL IIH1 IIH2 CLD RF Test Conditions No output loads, VDD=6V VDD-VSS =5.0V VDD-VSS=3.0V, VDD-VOUT=0.5V VDD-VSS=3.0V, VDD-VOUT=0.5V VDD-VSS=3.0V, VOUT –VSS=0.5V VIN=VDD=6V VIN=VDD=6V Min 3.0 — Typ — 0.3 300 500 500 — — 40 — — — 15 120 50 3 VDD=6V Max 7.0 0.5 5.0 — — — 30 600 60 Unit V mA μA μA μA μA μA μA % MΩ (VDD-VSS=3.0~7.0V, Ta = −40 ~ +85°C, RH≤70%, CD=CG=15pF, Xtal=4.194304MHz) Rev. 00 IN7100MQ Characteristic Power Supply Current High Level Output Current(1) High Level Output Current(2) (1) (2) (3) (4) (5) Symbol IDD IOH1 IOH2 Test Conditions No output loads VDD-VSS=3.0V, VDD-VOUT=0.5V VDD-VSS=3.0V, VDD-VOUT=0.5V Min — 250 400 Typ — — — Max 0.5 — — Unit mA μA μA for segment other than bc4, ad2, 1Hz for segment bc4, ad2, 1Hz and CLOUT for CLOUT for DS1, DS2, RES, HS, MS and BLK for T1, T2, T3 and AC PIN CONFIGURATION N.C N.C B3 1Hz F2 ad2 B2 F1 A1 B1 23 33 A3 T1 34 22 N.C F3 MS T2 HS T3 RES VDD OI VDD OO BLK VSS DS1 VSS DS2 AC bc4 CL OUT G3 12 44 E3 CLK 11 1 D3 C3 G2 E2 C2 G1 E1 D1 C1 N.C MQFP-44 Rev. 00 IN7100MQ Block Diagram (for die) Rev. 00 IN7100MQ APPLICATION CIRCUIT D1 IN4007 B+ C3 47uf R1 270 + ZD1 IN4743A Cx 1 pF C4 1000pf C2 15 pF EC1 0.22 uF R5 27 4.194304 MHz VDD OI ZD2 IN4732A C5 10uf OO AC HS GRID MS + FIP RES D2 IN4007 R4 67 2W R2 18k FILAMENT SEGMENT R7 30k − BLK IGN + R8 100k DS2 T+ D3 IN4007 DS1 T3 CLOUT 1024 Hz T2 D4 IN4007 T1 CLK VSS E− R3 6.8k Rev. 00 IN7100MQ APPLICATION CIRCUIT (for EMI enhancement) D1 IN4007 B+ C3 33uf R1 100 + ZD1 IN4743A Cx (1 pF) C4 10nf C1 15 pF C2 13 pF EC1 1 uF R5 24 4.194303 MHz VDD OI ZD2 IN4732A C5 10uf OO AC HS GRID MS + FIP RES D2 IN4007 R4 67 2W R2 47k R7 33k BLK T+ DS2 D3 IN4007 FILAMENT SEGMENT IGN + − DS1 T3 CLOUT 1024 Hz) T2 D4 IN4007 T1 CLK VSS E− ZD3 IN4732A Rev. 00 IN7100MQ PIN DESCRIPTION QFP-44 NAME I/O DESCRIPTION 1 E3 O SEGMENT OUTPUT 2 D3 O SEGMENT OUTPUT 3 C3 O SEGMENT OUTPUT 4 G2 O SEGMENT OUTPUT 5 E2 O SEGMENT OUTPUT 6 C2 O SEGMENT OUTPUT 7 G1 O SEGMENT OUTPUT 8 E1 O SEGMENT OUTPUT 9 D1 O SEGMENT OUTPUT 10 C1 O SEGMENT OUTPUT 11 -- -- NO CONNECTION 12 CLK I EXTERNAL CLOCK INPUT; External clock of 1024 Hz frequency can drive the IC operation 13 CLOUT O CLOCK OUTPUT; Clock of 1024 Hz frequency is generated when using 4.194304 MHz crystal 14 AC I CLEAR INPUT (power on reset input pin) 15, 16 VSS I GROUND 17 OO O OSCILLATOR OUTPUT (4.194304 MHz crystal output) 18 OI O OSCILLATOR INPUT (4.194304 MHz crystal input) 19 RES I RES INPUT (±30 minutes auto correction Input) 20 HS I HOUR ADJUST INPUT 21 MS I MINUTE ADJUST INPUT 22 -- -- NO CONNECTION 23 T1 I TEST PIN1 24 B1 O SEGMENT OUTPUT 25 A1 O SEGMENT OUTPUT 26 F1 O SEGMENT OUTPUT 27 B2 O SEGMENT OUTPUT 28 ad2 O SEGMENT OUTPUT 29 F2 O SEGMENT OUTPUT 30 1HZ O SEGMENT OUTPUT (colon) -- -- NO CONNECTION 31 B3 O SEGMENT OUTPUT 32 -- -- NO CONNECTION 33 -- -- NO CONNECTION 34 A3 O SEGMENT OUTPUT 35 F3 O SEGMENT OUTPUT 36 T2 I TEST PIN2 37 T3 I TEST PIN3 38, 39 VDD I POWER SUPPLY 40 BLK I BLANCKING INPUT; When this pin is low state, FIP is off and the operation of HS, MS, RES, switch is blocking, or vice versa 41 DS1 I 42 DS2 I 43 bc4 O SEGMENT OUTPUT 44 G3 O SEGMENT OUTPUT DIMMER INPUT1, DIMMER INPUT2; This PIN control the brightness of FIP. Duty of segment output is determined depend on the level of DS1, DS2 | DS1 | VDD | VSS | VDD | VSS | | DS2 | VDD | VDD | VSS | VSS | | DUTY | 1/16 | 1/8 | 1/4 | 1 | Rev. 00 IN7100MQ INTERNAL STATE pull down: BLK, DS1, DS2, AC, RES, HS, MS, TE1, TE2, TE3 P-ch OPEN DRAIN: bc4, g3, e3, d3, c3, g2, e2, c2, g1, e1, d1, c1, b1, a1, f1, b2, ad2, f2, 1Hz, b3, a3, f3 PGK Dimension (MQFP-44) Rev. 00