M66313FP 32-Bit LED Driver with Shift Register and Latch REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Description The M66313FP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel-output shift register, equipped with direct set input and output latches. The M66313FP guarantees sufficient 24 mA output current to drive anode common LED, allowing 32-bit simultaneous and continuous current output. The parallel outputs are open-drain outputs. The M66313FP employs CMOS technology, allowing considerable reduction of power dissipation, compared to previous BIPOLAR or Bi-CMOS products. In addition, the pin configuration is suitable for easy wiring on the printed circuit board. Features • High output current. All parallel output IOL = +24 mA, LEDs can be turned on simultaneously. • Low power dissipation : 200 µW/package (max) (VCC = 5 V, Ta = 25°C, quiescent state) • High noise margin Employment of Schmitt–trigger circuit on all inputs allows application with long wiring. • Direct set input (SD) • Open-drain output (Q1 to Q32) • Serial data output for cascading (SQ32) • Wide operating temperature range (Ta = −40 to +85°C) • Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED connection) Application LED array drive for eraser unit of a copying machine LED array drive of a button telephone set Various LED modules REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 1 of 9 M66313FP Block Diagram Serial data output Parallel data outputs Q1 Q2 Q3 Q4 Q29 Q30 Q31 Q32 SQ32 VCC 2 3 4 5 17 18 19 20 14 8 …………… …… 0 0 0 0 0 0 0 0 LE D SD LE D SD LE D SD LE D SD LE D SD LE D SD LE D SD D 1 1 1 1 CK D SD CK D SD CK D SD CK D SD LE SD …… …… 1 1 1 1 CK D SD CK D SD CK D SD CK D SD ………… …… …… 10 9 OE A Output Serial enable data input input 13 VCC Parallel output SQ32 Serial output Output type REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 2 of 9 11 1 32 21 CK SD LE GND1 GND2 GND3 Shift Direct Latch clock set enable input input input VCC Q1 to Q32 12 M66313FP Pin Arrangement M66313FP GND1 1 Q7 42 → Q7 Q1 ← 2 Q1 Q8 41 → Q8 Q2 ← 3 Q2 Q9 40 → Q9 Q3 ← 4 Q3 Q10 39 → Q10 Q4 ← 5 Q4 Q11 38 → Q11 Q5 ← 6 Q5 Q12 37 → Q12 Q6 ← 7 Q6 Q13 36 → Q13 8 Q14 35 → Q14 Serial data input A→ 9 A Q15 34 → Q15 Output enable input OE → 10 OE Q16 33 → Q16 Latch enable input LE → 11 LE Direct set input SD → 12 SD Q17 31 → Q17 Shift clock input CK → 13 CK Parallel data outputs VCC Parallel data outputs 32 GND2 Q18 30 → Q18 SQ32 Q19 29 → Q19 Q27 ← 15 Q27 Q20 28 → Q20 Q28 ← 16 Q28 Q21 27 → Q21 Q29 ← 17 Q29 Q22 26 → Q22 Q30 ← 18 Q30 Q23 25 → Q23 Q31 ← 19 Q31 Q24 24 → Q24 Q32 ← 20 Q32 Q25 23 → Q25 Q26 22 → Q26 Serial data output SQ32 ← 14 GND3 21 Parallel data outputs Parallel data outputs (Top view) Outline: 42P2R-A Functional Description The employment of silicon gate CMOS process of the M66313FP guarantees low power dissipation and maintains high noise margin as well as high output current and high speed required to drive LEDs. Each shift register bit consists of a flip-flop for shifting and an output latch. The shift operation takes place when the clock input CK changes from low-level to high-level. The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is shifted in sequence when a pulse is applied to CK. The parallel outputs Q1 to Q32 are open-drain outputs. If the latch-enable input LE is turned high–level, the content of the shift register at that instant is latched. To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of the 32nd bit. If the direct set input SD is turned low-level, shift register and latches are set. If the high-level input is applied to the output enable input OE, Q1 to Q32 are set to the high-impedance state, but SQ32 is not set to the high-impedance state. The shift operation is not affected when OE is changed. REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 3 of 9 M66313FP Function Table (Note) Operation Mode Input Parallel Data Output SD CK LE A OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Serial Data Output SQ32 Set L X X X L L Shift H ↑ L H L L Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q020 Q021 Q022 Q023 Q024 Q025 Q026 Q027 Q028 Q029 Q030 Q031 q031 Z Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q020 Q021 Q022 Q023 Q024 Q025 Q026 Q027 Q028 Q029 Q030 Q031 q031 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H ↑ L L L Latch H X H X L Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q020 Q021 Q022 Q023 Q024 Q025 Q026 Q027 Q028 Q029 Q030 Q031 Q032 q32 Output disable X X X X H Note Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z q32 ↑: Transition from low-to-high-level. Q0: Shows the status of output Q before CK input changes. X: Irrelevant 0 q : The content of shift register before CK changes. q: The content of the shift register. Z: High-impedance state. Absolute Maximum Ratings (Ta = −40 to +85°C, unless otherwise noted) Item Symbol Supply voltage VCC Input voltage Output voltage Input protection diode current VI VO IIK Output parasitic diode current IOK Q1 to Q32 SQ32 Output current IO Supply/GND current Power dissipation Storage temperature range ICC Pd Tstg Ratings −0.5 to + 7.0 Unit V −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 −20 20 −20 20 50 ±25 −920, +20 650 −65 to +150 V V mA mA Conditions VI < 0 V VI > VCC VO < 0 V VO > VCC mA mA mW °C VCC, GND Recommended Operating Conditions Item Symbol Min Limits Typ Max Unit Supply voltage Input voltage Output voltage VCC VI VO 4.5 0 0 5 — — 5.5 VCC VCC V V V Operating free–air ambient temperature range Topr −40 — +85 °C REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 4 of 9 M66313FP Electrical Characteristics (VCC = 4.5 to 5.5 V, unless otherwise noted) Limits Ta = 25°C Sym bol Item Positive-going threshold voltage VT+ Negative-going threshold voltage VT− High-level output voltage SQ32 Low-level output voltage Q1 to Q32 Ta = −40 to +85°C Typ Min (Note1) Max Min Max Unit 0.35×VCC 2.8 0.7×VCC 0.35×VCC 0.7×VCC V Conditions VO = 0.1V, VCC−0.1V IO = 20µA 0.2×VCC 2 0.55×VCC 0.2×VCC 0.55×VCC V VO = 0.1V,VCC−0.1V IO = 20µA VOH VCC−0.1 — — VCC−0.1 — V VI = VT+,VT− VCC = 4.5V 3.83 VOL — — 3.66 IOH = −4mA — — — 0.1 — 0.1 — 0.20 0.41 — 0.50 — 0.25 0.48 — 0.55 IOH = −20µA V VI = VT+,VT− VCC = 4.5V IOL = 20µA IOL = 24mA IOL = 28mA (Note 2) SQ32 — — 0.1 — 0.1 IOL = 20µA — — 0.44 — 0.53 IOL = 4mA High-level input current IIH — — 0.5 — 5.0 µA VI = VCC, VCC = 5.5V Low-level input current IIL — — –0.5 — −5.0 µA VI = GND, VCC = 5.5V IO — — 1.0 — 10.0 µA — — −1.0 — −10.0 VI = VT+, VT− Maximum output leak current Q1 to Q32 Quiescent state dissipation current Note: VO = VCC VO = GND VCC = 5.5V ICC — — 40.0 1. All typical values are at VCC = 5 V, Ta = 25°C 2. Ta = −40 to +70°C REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 5 of 9 — 400.0 µA VI = VCC, GND, VCC = 5.5V M66313FP Switching Characteristics (VCC = 5V) Limits Item Symbol Maximum clock frequency fmax Min Ta = 25°C Typ Max 5 — 30 35 — 150 Ta = −40 to +85°C Min Max 4 — — 200 Unit Conditions MHz ns CL = 50 pF RL = 1 kΩ Output enable time to low-level CK-Q1 to Q32 (Turned on) tPZL Output disable time from low-level CK-Q1 to Q32 (Turned off) CK-SQ32 tPLZ — 35 200 — 250 ns tPLH tPHL — — 35 40 100 100 — — 130 130 ns ns SD-Q1 to Q 32 (Turned on) SD-SQ32 tPZL — 35 150 — 200 ns tPLH — 40 100 — 130 ns Output enable time to low-level LE- Q 1 to Q 32 (Turned on) tPZL — 30 100 — 130 ns Output disable time from low-level LE-Q1 to Q32 (Turned off) tPLZ — 35 150 — 200 ns Output enable time to low-level OE-Q1 to Q32 (Turned on) tPZL — 30 100 — 130 ns Output disable time OE-Q1 to Q32 from low-level (Turned off) Input capacitance Output capacitance Power dissipation capacitance (Note 1) tPLZ — 35 150 — 200 ns CI CO CPD — — — 3 6 160 10 15 — — — — 10 15 — pF pF pF Low-to-high, high-tolow output propagation time Output enable time to low-level Low-to-high output propagation time Note (Note 2) OE–VCC 1. CPD is the equivalent capacitance of IC calculated by the operating power dissipation without load. The operating power dissipation without load is given as follows. 2 PD = CPD • VCC • fI + ICC • VCC REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 6 of 9 M66313FP Timing Requirements (VCC = 5V) Limits Item Symbol CK, LE, SD pulse width Setup time A to CK Hold time A to CK Hold time LE to CK Recovery time CK to SD Note: tW tsu th Min Ta = 25°C Typ 100 100 10 50 50 trec 16 27 5 15 20 Ta = −40 to +85°C Min Max Max — — — — — 130 130 15 70 70 2. Test Circuit VCC Input VCC RL PG DUT 50 Ω GND SQ32 Q1 to Q32 CL CL (1) Characteristics of pulse generator (PG): tr = 6 ns, tf = 6 ns (2) CL includes probe and stray capacitance. REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 7 of 9 — — — — — Unit ns ns ns ns Conditions (Note 2) M66313FP Timing Chart tw tw tw VCC CK 50% 50% 50% tPLH SQ32 50% 50% tPLZ Q1 to Q32 GND tPHL VOH VOL tPZL ≈ VCC 50% 10% VCC 50% 50% LE GND tPZL ≈ VCC Q1 to Q32 50% VOL tPLZ ≈ VCC Q1 to Q32 10% VOL VOL tw VCC SD 50% 50% trec GND VCC A 50% GND tsu VCC CK 50% th 50% GND tPLH VCC CK 50% VOH SQ32 GND 50% VOL tPZL ≈ VCC Q1 to Q32 50% VOL th LE VCC 50% GND OE 50% 50% tPZL Q1 to Q32 50% REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 8 of 9 tPLZ VCC GND ≈ VCC 10% CK VOL 50% VCC GND Q1 to Q32 ≈ VCC VOL M66313FP Package Dimensions 42P2R-A MMP EIAJ Package Code SSOP42-P-450-0.80 Plastic 42pin 450mil SSOP JEDEC Code — Weight(g) 0.63 e b2 22 E HE e1 I2 42 Lead Material Alloy 42/Cu Alloy Recommended Mount Pad F Symbol 1 21 A D G A2 e b L L1 y A1 A A1 A2 b c D E e HE L L1 z Z1 y c z Z1 Detail G REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 9 of 9 Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max — — 2.4 0.05 — — — 2.0 — 0.35 0.4 0.5 0.13 0.15 0.2 17.3 17.5 17.7 8.2 8.4 8.6 — 0.8 — 11.63 11.93 12.23 0.3 0.5 0.7 — 1.765 — — 0.75 — — 0.9 — — — 0.15 0° — 10° — 0.5 — — 11.43 — — 1.27 — Sales Strategic Planning Div. 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