DATA SHEET LND-31200-SPCL ADVANCED DISPLAY CONTROLLER IC LND-31200-SPCL ADVANCED DISPLAY CONTROLLER IC What is the LND-31200-SPCL? The LND-31200-SPCL is an advanced, high voltage, display driver designed to meet the needs of the next generation of advanced displays. Some of the unique features of this device include up to 45V operation, row/column selectable output, cascadable drive scheme, token architecture, left/right shift modes, and 80 output drivers all in a high voltage, submicron process which allows the smallest tape mount footprint in its class (only 12mm x 1.25mm for 80 channels !). Despite all this the device is capable of up to 45V operation with each pixel capable of being independently driven by up to eight different voltages. For customers requiring customized truth tables, configurable logic is definable through only a metal mask change; the waveforms are then addressed through state/data truth table latches. The LND-31200-SPCL offers the greatest flexibility of any display driver on the market today. How Does it Work? Determine row/column mode through the R/C pin. Turn on display through DISP_OFF. Connect V1-V8 to desired power supplies. Set data shift direction. Clock data into shift register. Data is loaded 8 bits at a time. Each pair of data bits, plus the state bits, lookup a different voltage from a truth table and applies it to a single pixel. In this way, data can be varied in four ways through state latch changes alone while data remains constant. Data will be carried through the carry terminals for seamless integration into the next LND-31200-SPCL. In this way, an unlimited number of pixels can potentially be addressed in either row or column mode. Features · · · · · · · · · 80 Output Driver High Voltage: 45V Tiny 12mm X 1.25mm die 8 Selectable voltages per pixel for greyscale operation Row/Column Addressable Left/Right Shift Modes Interchangable carry in/carry out terminals ICS fully cascadable for larger displays High voltage, submicron process for smallest possible tapemount footprint Applications · VGA Display Drivers ( Laptop Computers) · Portable Equipment · Embedded Systems · Hand Held Instruments · Customizable Driver for New Display Technologies How Do I get samples? The LND-31200-SPCL is meant for tape mounted applications. Though default truth table logic is included for the display (and described in this data sheet), many customers will want to customize their logic. There is an NRE fee for this metal mask change. Samples are then provided in die form or placed onto 75mm tape for evaluation. Linear Dimensions can supply product in die form, tested or untested, as well as on tape. To arrange for samples, call the factory or your local Linear Dimensions representative. Linear Dimensions, Inc. 445 East Ohio Street, Chicago, IL 60611 p 312.3211810 f 312.321.1830 ADVANCED DISPLAY CONTROLLER IC PROPOSED DATA SHEET O1 O159 O2 O160 Vdd 8 160 High Voltage Output Driving Cell V1..V8 Vss Vee LS HV Pass Gate Control S0 S1 2 bits Latch R/C* Voltage Select Logic & Level Shifter DISP_OFF* 160 x 2 bits Data Latch (8 bit x 40) 8 D0..D7 8 Data Mux 2 1 Shift Register 40 Shift Clock Carry Carry SCLK DIR LP Data Strobe Timing Generator EIO2* EIO1* Table 1. Pin Description PIN NAME INPUT/OUTPUT DESCRIPTION Vdd Input Power suppl for logic circuit (+5V). Vss Input Power supply for logic and analog Ground (0V). Vee Input High voltage power supply for LCD driver circuit (45V max). V1-V8 Input Eight voltage levels between Vss and Vee. OI-0160 Output LCD drive voltage output. Do-D7 Input Data input. Each output needs two bits data. One sift clock takes care of 4 outputs. EIOI*, EIO2* Input/Output Enable data input and generate cascade output signal. DIR Input Input or output is set according to DIR. (Table 2) See the data shift direction (Table 3): Vdd: EIOI input, EIO2 output; data shift form S1 to S160. Vss: EIOI output, EIO2 input; data shift from S160 to S1. R/C* Input Set the output voltage waveform mode: Vdd: Row driver waveform Vss: Column driver waveform Global statelogic inputs for the DC cancellation and SO, S1 Input LP Input LS Input State logic latch. The global state data is latched at the falling edge of this pulse. SCLK Input Data shift clock. Falling edge trigger. DISP_OFF* Input Vdd: Driver output enable. crosstalk elimination. Pixel data latch. Input data is latched to the LCD driver outputs. Falling edge trigger. Vss: Driver output tied to V1. Linear Dimensions, Inc. 445 East Ohio Street, Chicago, IL 60611 p 312.3211810 f 312.321.1830 ADVANCED DISPLAY CONTROLLER IC PROPOSED DATA SHEET Table 2. DIR Shift direction and EIO1*, EIO2* state DIR EIO1* EIO2* H IN OUT L OUT IN Table 3. DIR shift dorection and the corresponding data bit mapping *nH and nL are the high bit and the low bit data for output number n. n ranged from 1 to 160. DIR SCLK: I 2 3 4 --- 38 39 40 H D0 IL 5L 9L 13L --- 149L 153L 157L H D1 IH 5H 9H 13H --- 149H 153H 157H H D2 2L 6L 10L 14L --- 150L 154L 158L H D3 2H 6H 10H 14H --- 150H 154H 158H H D4 3L 7L 11L 15L --- 151L 155L 159L H D5 3H 7H 11H 15H --- 151H 155H 159H H D6 4L 8L 12L 16L --- 152L 156L 160L H D7 4H 8H 12H 16H --- 152H 156H 160H L D0 160H 156H 152H 148H --- 12H 8H 4H L D1 160L 156L 152L 148L --- 12L 8L 4L L D2 159H 155H 151H 147H --- 11H 7H 3H L D3 159L 155L 151L 147L --- 11L 7L 3L L D4 158H 154H 250H 146H --- 10H 6H 2H L D5 158L 154L 150L 146L --- 10L 6L 2L L D6 157H 153H 149H 145H --- 9H 5H 1H L D7 157L 153L 149L 145L --- 9L 5L 1L Table 4. R/C*=1 (Row driver mode) STATE (SO, SI) (0,0) (nL, nH) (0,0) non. V7 V5 (1,0) sel. V3 (0,1) evl. (1,1) prep. V1 Table 5. R/C*=0 (Column driver mode) Data Data (SO, SI) (1,0) V7 V8 V3 V1 (SO, SI) (0,1) V2 V1 V6 V8 (SO, SI) (1,1) V2 V4 V6 V8 (nL, nH) (0,0) gray (1,0) gray (0,1) gray (1,1) gray STATE (SO, SI) (0,0) V8 V7 V6 V5 (SO, SI) (1,0) V5 V6 V7 V8 (SO, SI) (0,1) V4 V3 V2 V1 Linear Dimensions, Inc. 445 East Ohio Street, Chicago, IL 60611 p 312.3211810 f 312.321.1830 (SO, SI) (1,1) V1 V2 V3 V4 ADVANCED DISPLAY CONTROLLER IC PROPOSED DATA SHEET ADVANCED DISPLAY CONTROLLER IC PROPOSED DATA SHEET