ESMT AD8256A 2x16W Stereo Digital Audio Amplifier with Headphone Driver Features Anti-pop design 2 16/18/20/24-bit input with I S, Left-alignment Over-temperature protection and Right-alignment data format Under-voltage shutdown PSNR & DR(A-weighting) Short-circuit protection Loudspeaker: 93dB (PSNR), 98dB (DR) 2 I C control interface Headphone: 86dB (PSNR), 96dB (DR) Applications Multiple sampling frequencies (Fs) 32kHz / 44.1kHz / 48kHz and CD and DVD 64kHz / 88.2kHz / 96kHz TV audio System clock = 64x, 128x, 192x, 256x, 384x, Car audio 512x, 576x, 768x, 1024x Fs Boom-box Supply voltage MP3 docking systems 3.0~12V for loudspeaker driver Portable / Handheld 3.0~3.3V for others Powered speaker 2.5~5.5V tolerant input interface Wireless audio Loudspeaker output power USB speaker 2×10W(Full,8Ω) @ 1kHz and 10% THD+N 2×12.5W(Full,6Ω) @ 1kHz and 10% THD+N Description 2×16W(Full,4Ω) @ 1kHz and 10% THD+N This is a stereo fully digital audio amplifier with Headphone power output power which can deliver up to 2×16W to 4Ω 34mW into 32Ω@1kHz and 1% THD+N load with 12V supply voltage. Using I2C digital 65mW into 16Ω@1kHz and 1% THD+N control interface, AD8256A provides sound 110mW into 8Ω@1kHz and 1% THD+N processing functions including Volume, Bass, Treble, 200mW into 4Ω@1kHz and 1% THD+N EQ, Mixing and Dynamic Range Control (DRC). Sound processing including： Bass (+18dB~-12dB, 3dB frequency is 250Hz), ORDERING INFORMATION Treble (+18dB~-12dB, 3dB frequency is 7kHz), 5 bands parametric EQ, Volume control (+24dB~-103dB, 1dB/step) and Product Number Package AD8256A-KG 7x7 48L QFN Dynamic range control Comments Pb-free I2C Control Interface BCLK SDATA0 SDATA1 SDATA2 LRCIN Input Interface Audio Signal Processing MCLK SA1 SA0 SCL Reset HPSPK PD SDA Functional Block Diagram PLL_Byp PLL HPL HPR Internal System Clock Protection Circuits PCM to PWM Loudspeaker Driver Elite Semiconductor Memory Technology Inc. or Headphone Driver ERROR L R Publication Date : Nov. 2005 Revision : 1.0 1/3 ESMT AD8256A HP-SPK 37 VDDLB2 38 LB2 39 GNDL2 40 LA2 41 VDDLA2 42 VDDLA1 43 LA1 44 GNDL1 45 LB1 46 VDDLB1 47 PLL_Byp 48 Pin Assignment MCLK 1 36 HPL PLLGND 2 35 HPR PLLVDD 3 34 AGND CLK_OUT 4 33 AVDD 32 PWMSA DVDD 5 DGND2 6 31 DEF DGND1 7 30 SDA N.C. 8 29 SCL SDATA0 9 28 SA1 SDATA1 10 27 SA0 SDATA2 11 26 ERROR 25 PD LRCIN 12 24 Reset 23 VDDRB2 21 GNDR2 22 RB2 20 RA2 19 VDDRA2 18 VDDRA1 17 RA1 16 GNDR1 15 RB1 14 VDDRB1 13 BCLK Pin Description PIN NAME TYPE DESCRIPTION CHARACTERISTICS 1 MCLK I Master clock input 5V tolerant Schmitt trigger TTL input buffer 2 PLLGND P Ground for PLL 3 PLLVDD P Supply for PLL (Note1) 4 CLK_OUT O PLL output 5V tolerant TTL output buffer 5 DVDD P Digital Power (Note1) 6 DGND2 P Digital Ground2 7 DGND1 P Digital Ground1 8 N.C. 9 SDATA0 I Serial audio data input 0 5V tolerant Schmitt trigger TTL input buffer 10 SDATA1 I Serial audio data input 1 5V tolerant Schmitt trigger TTL input buffer 11 SDATA2 I Serial audio data input 2 5V tolerant Schmitt trigger TTL input buffer 12 LRCIN I Left/Right clock input (Fs) 5V tolerant Schmitt trigger TTL input buffer 13 BCLK I Bit clock input (64Fs) 5V tolerant Schmitt trigger TTL input buffer 14 VDDRB1 P Supply1 for right channel B (Note2) 15 RB1 O Right channel output1 (-) 16 GNDR1 P Ground1 for right channel 17 RA1 O Right channel output1 (+) 18 VDDRA1 P Supply1 for right channel A (Note2) 19 VDDRA2 P Supply2 for right channel A (Note2) 20 RA2 O Right channel output2 (+) 21 GNDR2 P Ground2 for right channel 22 RB2 O Right channel output2 (-) No Connection Elite Semiconductor Memory Technology Inc. Publication Date : Nov. 2005 Revision : 1.0 2/3 ESMT AD8256A 23 VDDRB2 P Supply2 for right channel B (Note2) 24 Re set I Reset, low active 5V tolerant Schmitt trigger TTL input buffer 25 PD I Power down, low active 5V tolerant Schmitt trigger TTL input buffer 26 ERROR O ERROR output Open-drain output 2 27 SA0 I I C select address 0 5V tolerant Schmitt trigger TTL input buffer 28 SA1 I I2C select address 1 5V tolerant Schmitt trigger TTL input buffer 2 29 SCL I I C serial clock input 5V tolerant Schmitt trigger TTL input buffer 30 SDA I I2C serial data input 31 DEF I Default volume, 0=Mute, 1=Un-Mute 5V tolerant Schmitt trigger TTL input buffer 32 PWMSA O Half-bridge, sub-woofer channel output 5V tolerant TTL output buffer 33 AVDD P Analog supply (Note1) 34 AGND P Analog ground 35 HPR O Headphone right channel output 36 HPL O Headphone left channel output 37 HP-SPK I Headphone detection 38 VDDLB2 P Supply2 for left channel B 39 LB2 O Left channel output2 (-) 40 GNDL2 P Ground2 for left channel 41 LA2 O Left channel output2 (+) 42 VDDLA2 P Supply2 for left channel A (Note2) 43 VDDLA1 P Supply1 for left channel A (Note2) 44 LA1 O Left channel output1 (+) 45 GNDL1 P Ground1 for left channel 46 LB1 O Left channel output1 (-) 47 VDDLB1 P Supply1 for left channel B (Note2) 48 PLL_Byp I PLL Bypass 5V tolerant Schmitt trigger TTL input buffer 5V tolerant Schmitt trigger TTL input buffer with open-drain output (Note2) Note1：These pins provide the supply for digital PWM controller, headphone drivers, built-in PLL and protection circuits except for loudspeaker short-circuit protection circuits. Note2：These pins provide the supply for loudspeaker driver stages, which are known as “PVDD” Available Package Package Type Device No. θja(℃/W) Ψjt(℃/W) θjc(℃/W) Exposed Thermal Pad 7x7 48L QFN AD8256A 23.5 1.6 12.5 Yes Note3：The thermal pad is at the bottom for QFN package. To optimize the performance of thermal dissipation, solder the thermal pad to PCB’s ground plane is suggested. Elite Semiconductor Memory Technology Inc. Publication Date : Nov. 2005 Revision : 1.0 3/3