ESMT
F59L512M81A
Flash
512Mbit (64M x 8)
3.3V NAND Flash Memory
FEATURES
Voltage Supply: 2.7V ~ 3.6V
Organization
- Memory Cell Array: (64M + 2M) x 8bit
- Data Register: (2K + 64) x 8bit
Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
Page Read Operation
- Page Size: (2K + 64) Byte
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 250us (Typ.)
- Block Erase time: 2ms (Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
- ECC Requirement: 4 bit/512 Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program Operation for High Performance Program
Cache Read Operation
Copy-Back Operation
EDO mode
OTP Operation
Bad-Block-Protect
ORDERING INFORMATION
Product ID
F59L512M81A -25TG
Speed
Package
Comments
25 ns
48 pin TSOPI
Pb-free
GENERAL DESCRIPTION
The device is a 64Mx8bit with spare 2Mx8bit capacity. The
device is offered in 3.3V VCC Power Supply. Its NAND cell
provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 512 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 2,112-Byte page in
typical 300us and an erase operation can be performed in typical
3ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per
Byte. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
Elite Semiconductor Memory Technology Inc.
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Publication Date: May 2014
Revision: 1.0
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ESMT
F59L512M81A
PIN CONFIGURATION (TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)
NC
NC
NC
NC
NC
NC
R/B
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VCC
VSS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
Pin Description
Symbol
I/O0~I/O7
CLE
ALE
Pin Name
Data Inputs / Outputs
Command Latch
Enable
Address Latch Enable
Functions
The I/O pins are used to input command, address and data, and to output data
during read operations. The I/O pins float to Hi-Z when the chip is deselected or
when the outputs are disabled.
The CLE input controls the activating path for commands sent to the internal
command registers. Commands are latched into the command register through the
I/O ports on the rising edge of the WE signal with CLE high.
The ALE input controls the activating path for address sent to the internal address
registers. Addresses are latched into the address register through the I/O ports on
the rising edge of WE with ALE high.
The CE input is the device selection control. When the device is in the Busy state,
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
CE high is ignored, and the device does not return to standby mode in program or
erase operation. Regarding CE control during read operation, refer to ’Page read’
section of Device operation.
The RE input is the serial data-out control, and when it is active low, it drives the
data onto the I/O bus. Data is valid tREA after the falling edge of RE which also
increments the internal column address counter by one.
The WE input controls writes to the I/O port. Commands, address and data are
latched on the rising edge of the WE pulse.
The WP pin provides inadvertent write/erase protection during power transitions.
The internal high voltage generator is reset when the WP pin is active low.
Ready / Busy Output
The R/ B output indicates the status of the device operation. When low, it indicates
that a program, erase or random read operation is in process and returns to high
state upon completion. It is an open drain output and does not float to Hi-Z
condition when the chip is deselected or when outputs are disabled.
VCC
Power
VCC is the power supply for device.
VSS
Ground
NC
No Connection
R /B
Lead is not internally connected.
Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
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ESMT
F59L512M81A
BLOCK DIAGRAM
ARRAY ORGANIZATION
Address Organization
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
A0
A1
A2
A3
A4
A5
A6
1st cycle
2nd cycle
A8
A9
A10
A11
L*
L*
L*
3rd cycle
A12
A13
A14
A15
A16
A17
A18
4th cycle
A20
A21
A22
A23
A24
A25
A26
Note:
Column Address: Starting Address of the Register.
*L must be set to “Low”.
* The device ignores any additional input of address cycles than required.
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I/O7
A7
L*
A19
L*
Address
Column Address
Column Address
Row Address
Row Address
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ESMT
F59L512M81A
Product Introduction
The device is a 528Mbit memory organized as 32K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column
address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The program and read operations are executed on a page basis,
while the erase operation is executed on a block basis. The memory array consists of 512 separately erasable 128K-byte blocks. It
indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address Latch
Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory.
Command Set
Function
Read
Read for Copy Back
Read ID
Reset
Page Program
Copy-Back Program
Block Erase
Random Data Input(1)
Random Data Output(1)
Read Status
Cache Program
Cache Read
Read Start For Last Page Cache Read
1st Cycle
00h
00h
90h
FFh
80h
85h
60h
85h
05h
70h
80h
31h
3Fh
Acceptable Command
during Busy
2nd Cycle
30h
35h
10h
10h
D0h
E0h
15h
-
O
O
Note:
1. Random Data Input / Output can be executed in a page.
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Publication Date: May 2014
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ESMT
F59L512M81A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Temperature Under Bias
VCC
VIN
VI/O
TBIAS
-0.6 to +4.6
-0.6 to +4.6
-0.6 to VCC + 0.3 (< 4.6)
-40 to +125
℃
Storage Temperature
TSTG
-65 to +150
℃
Short Circuit Current
IOS
5
mA
Voltage on any pin relative to VSS
V
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA = 0 to 70℃)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
2.7
0
3.3
0
3.6
0
V
V
Supply Voltage
Supply Voltage
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Parameter
Page Read with
Serial Access
Operating
Program
Current
Erase
Symbol
Test Conditions
Min.
Typ.
ICC1
tRC=25ns, CE =VIL, IOUT=0mA
-
15
ICC2
ICC3
-
-
15
15
Stand-by Current (TTL)
ISB1
CE =VIH, WP =0V/VCC
-
Stand-by Current (CMOS)
ISB2
CE = VCC -0.2, WP =0V/ VCC
ILI
VIN=0 to VCC (max)
ILO
VOUT=0 to VCC (max)
Input Leakage Current
Output Leakage Current
VIH(1)
(1)
VIL
VOH
VOL
Input High Voltage
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current (R/ B )
IOL (R / B )
IOH=-400uA
IOL=2.1mA
VOL=0.4V
Max.
Unit
30
mA
-
1
mA
-
10
50
uA
-
-
±10
uA
-
-
±10
uA
0.8 x VCC
-0.3
2.4
-
-
VCC +0.3
0.2 x VCC
0.4
V
V
V
V
8
10
-
mA
Note:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
2. Typical value are measured at VCC =3.3V, TA=25℃. And not 100% tested.
VALID BLOCK
Symbol
Min.
Typ.
Max.
Unit
NVB
502
-
512
Blocks
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The
number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain
one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad
blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to
be a valid block up to 1K program/erase cycles with 4bit/512Byte ECC.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
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ESMT
F59L512M81A
AC TEST CONDITION
(TA=0 to 70℃, VCC=2.7V~3.6V, unless otherwise noted)
Parameter
Condition
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
0V to VCC
5 ns
VCC /2
1 TTL Gate and CL=50pF
Note: Refer to Ready/ Busy section, R/ B output’s Busy to Ready time is decided by the pull-up resistor (RP) tied to the R/ B pin.
CAPACITANCE
(TA=25℃, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min.
Max.
Unit
CI/O
CIN
VIL = 0V
VIN = 0V
-
8
8
pF
pF
Input / Output Capacitance
Input Capacitance
Note: Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
H
L
L
WE
Mode
RE
WP
L
H
X
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
X
X
X
X
X
X
X
X
X(1)
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
H
H
L
0V/VCC(2)
Read Mode
Write Mode
Command Input
Address Input (4 clock)
Command Input
Address Input (4 clock)
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
Stand-by
Note:
1. X can be VIL or VIH.
2.
WP should be biased to CMOS high or CMOS low for stand-by.
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Publication Date: May 2014
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ESMT
F59L512M81A
Program / Erase Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Average Program Time
Dummy Busy Time for Cache Program
Number of Partial Program Cycles in the
Same Page
Block Erase Time
tPROG
tCBSY
-
300
3
750
750
us
us
NOP
-
-
4
Cycle
tBERS
-
3
10
ms
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V VCC and 25℃
temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program time variation from page to page is
possible.
3. Max. time of tCBSY depends on timing between internal program completion and data in.
AC Timing Characteristics for Command / Address / Data Input
Symbol
Min.
Max.
Unit
CLE Setup Time
CLE Hold Time
Parameter
tCLS(1)
tCLH
12
5
-
ns
ns
CE Setup Time
tCS
20
-
ns
CE Hold Time
tCH
5
-
ns
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
tWP
12
-
ns
tALS
tALH
tDS(1)
tDH
tWC
12
5
12
5
25
-
ns
ns
ns
ns
ns
tWH
10
-
ns
100
-
ns
WE High Hold Time
Address to Data Loading Time
(1)
tADL
(2)
Note:
1.
The transition of the corresponding control pins must occur only once while WE is held low.
2.
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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ESMT
F59L512M81A
AC Characteristics for Operation
Symbol
Min.
Max.
Unit
Data Transfer from Cell to Register
Parameter
tR
-
25
us
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
12
-
ns
WE High to Busy
tWB
-
100
ns
WP Low to WE Low (disable mode)
tWW
100
WP High to WE Low (enable mode)
Read Cycle Time
tRC
25
-
ns
RE Access Time
tREA
-
20
ns
CE Access Time
tCEA
-
25
ns
RE High to Output Hi-Z
tRHZ
-
100
ns
CE High to Output Hi-Z
tCHZ
-
30
ns
CE High to ALE or CLE Don’t Care
tCSD
0
-
ns
RE High to Output Hold
tRHOH
15
-
ns
RE Low to Output Hold
tRLOH
5
-
ns
CE High to Output Hold
tCOH
15
-
ns
RE High Hold Time
tREH
10
-
ns
Output Hi-Z to RE Low
tIR
0
-
ns
RE High to WE Low
tRHW
100
-
ns
tWHR
60
-
ns
tRST
-
5
10
500
5(1)
us
us
us
us
tDCBSYR
-
30
us
WE High to RE Low
Device Resetting
Time during ...
Cache Busy in Read Cache
(following 31h and 3Fh)
Read
Program
Erase
Ready
ns
Note:
1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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ESMT
F59L512M81A
NAND Flash Technical Notes
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The
information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the
same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not
affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The
system design must be able to mask out the initial invalid block(s) via address mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4bit/512Byte
ECC.
Identifying Initial Invalid Block(s) and Replacement Management
All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the 1st byte column address in the spare area.
Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information
and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop
with Flash memory usage.
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ESMT
F59L512M81A
Algorithm for Bad Block Scanning
Check “FFh” at the 1st Byte column address
in the spare area of the 1st and 2nd page in
the block.
For (i=0; i<Num_of_LUs; i++)
{
For (j=0; j<Blocks_Per_LU; j++)
{
Defect_Block_Found=False;
Read_Page(lu=i, block=j, page=0);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh)
Defect_Block_Found=True;
Read_Page(lu=i, block=j, page=1);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh)
Defect_Block_Found=True;
If (Defect_Block_Found) Mark_Block_as_Defective(lu=i, block=j);
}
}
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ESMT
F59L512M81A
Error in write or read operation
Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.
The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and
reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To
improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by
ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
Detection and Countermeasure sequence
Erase failure
Program failure
Up to 4 bits failure
Read Status after Erase → Block Replacement
Read Status after Program → Block Replacement
Verify ECC → ECC Correction
Note: Error Correcting Code --> RS Code or BCH Code etc.
Example: 4bit correction / 512 Byte
Program Flow Chart
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F59L512M81A
Erase Flow Chart
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F59L512M81A
Read Flow Chart
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F59L512M81A
Block Replacement
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page of the block to MSB (Most
Significant Bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.
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F59L512M81A
System Interface Using CE don’t-care
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio
applications that use slow cycle time on the order of μ-seconds, de-activating CE during the data-loading and serial access would
provide significant savings in power consumption.
Program/Read Operation with “ CE not-care”
Address Information
I/O
I/Ox
DATA
Data In / Out
Col. Add1
I/O0~7
2112 Byte
A0 ~ A7
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ADDRESS
Col. Add2
Row Add1
Row Add2
A8 ~ A11
A20 ~ A26
A12 ~ A19
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ESMT
F59L512M81A
Command Latch Cycle
Address Latch Cycle
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F59L512M81A
Input Data Latch Cycle
Serial access Cycle after Read (CLE = L, ALE = L, WE = H)
Note:
1. Dout transition is measured at ±200mV from steady state voltage at I/O with load.
2. tRHOH starts to be valid when frequency is lower than 33MHz.
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F59L512M81A
Serial access Cycle after Read ( EOD Type CLE = L, ALE = L, WE = H)
NOTE:
1.
Transition is measured at +/-200mV from steady state voltage with load.
This parameter is sample and not 100% tested. (tCHZ, tRHZ)
2.
tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
Status Read Cycle
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F59L512M81A
Read Operation
Read Operation (Intercepted by CE )
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F59L512M81A
Random Data Output In a Page
1
1
Page Program Operation
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F59L512M81A
Page Program Operation with Random Data Input
1
1
Note: tADL is the time from WE rising edge of final address cycle to the WE rising edge of first data cycle.
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F59L512M81A
Copy-Back Operation with Random Data Input
1
1
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F59L512M81A
Cache Program Operation
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F59L512M81A
Cache Read Operation
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F59L512M81A
Block Erase Operation
Read ID Operation
ID Definition Table
ID Access command = 90h
1st Cycle
(Maker Code)
2nd Cycle
(Device Code)
3rd Cycle
4th Cycle
5th Cycle
C8h
D0h
90h
95h
30h
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Maker Code
Device Code
Internal Chip Number, Cell Type, etc
Page Size, Block Size, etc
Plane Number, Plane Size, ECC Level
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F59L512M81A
3rd ID Data
Internal Chip Number
Cell Type
Reserved
Interleave Program
Between multiple chips
Cache Program
Description
1
2
4
8
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Reserved
Not Support
Support
Not Support
Support
I/O7
Description
1KB
2KB
4KB
8KB
8
16
64KB
128KB
256KB
512KB
x8
x16
45ns
Reserved
25ns
Reserved
I/O7
Description
I/O7
I/O6
I/O5
I/O4
0
1
I/O5
I/O4
I/O3
I/O2
0
0
1
1
0
1
0
1
I/O3
I/O2
I/O1
0
0
1
1
I/O0
0
1
0
1
I/O1
0
0
1
1
I/O0
0
1
0
1
I/O1
I/O0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
4th ID Data
Page Size
(w/o redundant area)
Redundant Area Size
(byte/512byte)
Block Size
(w/o redundant area)
Organization
Serial Access Time
I/O6
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
5th ID Data
ECC Level
Plane Number
Plane Size
(w/o redundant area)
Reserved
4bit/512B
2bit/512B
1bit/512B
Reserved
1
2
4
8
64Kb
128Kb
256Kb
512Kb
1Gb
2Gb
4Gb
8Gb
Reserved
I/O6
I/O5
I/O4
I/O3
0
0
1
1
0
0
0
0
1
1
1
1
0
Elite Semiconductor Memory Technology Inc.
0
0
1
1
0
0
1
1
I/O2
0
1
0
1
0
1
0
1
0
1
0
1
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ESMT
F59L512M81A
DEVICE OPERATION
Page Read
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h command, four-cycle
address, and 30h command. After initial power up, the 00h command can be skipped because it has been latched in the command
register. The 2,112Byte of data on a page are transferred to cache registers via data registers within 25us (tR). Host controller can
detect the completion of this data transfer by checking the R/ B output. Once data in the selected page have been loaded into cache
registers, each Byte can be read out in 25ns cycle time by continuously pulsing RE . The repetitive high-to-low transitions of RE
clock signal make the device output data starting from the designated column address to the last column address.
The device can output data at a random column address instead of sequential column address by using the Random Data Output
command. Random Data Output command can be executed multiple times in a page.
After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.
A page read sequence is illustrated in the figure below, where column address, page address are placed in between commands 00h
and 30h. After tR read time, the R/ B de-asserts to ready state. Read Status command (70h) can be issued right after 30h. Host
controller can toggle RE to access data starting with the designated column address and their successive bytes.
Read Operation
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F59L512M81A
Random Data Output In a Page
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F59L512M81A
Page Program
The device is programmed based on the unit of a page, and consecutive partial page programming on one page without intervening
erase operation is strictly prohibited. Addressing of page program operations within a block should be in sequential order. A complete
page program cycle consists of a serial data input cycle in which up to 2,112byte of data can be loaded into data register via cache
register, followed by a programming period during which the loaded data are programmed into the designated memory cells.
The serial data input cycle begins with the Serial Data Input command (80h), followed by a four-cycle address input and then serial
data loading. The bytes not to be programmed on the page do not need to be loaded. The column address for the next data can be
changed to the address follows Random Data Input command (85h). Random Data Input command may be repeated multiple times in
a page. The Page Program Confirm command (10h) starts the programming process. Writing 10h alone without entering data will not
initiate the programming process. The internal write engine automatically executes the corresponding algorithm and controls timing for
programming and verification, thereby freeing the host controller for other tasks. Once the program process starts, the host controller
can detect the completion of a program cycle by monitoring the R/ B output or reading the Status bit (I/O6) using the Read Status
command. Only Read Status and Reset commands are valid during programming. When the Page Program operation is completed,
the host controller can check the Status bit (I/O0) to see if the Page Program operation is successfully done. The command register
remains the Read Status mode unless another valid command is written to it.
A page program sequence is illustrated in the figure below, where column address, page address, and data input are placed in
between 80h and 10h. After tPROG program time, the R/ B de-asserts to ready state. Read Status command (70h) can be issued right
after 10h.
Program & Read Status Operation
Random Data Input In a page
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Cache Program
Cache Program is an extension of Page Program, which is executed with 2,112 byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
After writing the first set of data up to 2,112 bytes into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache
registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail status of only the
previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5)
for internal Ready/Busy may be polled to identity the completion of internal programming. If the system monitors the progress of
programming only with R/ B , the last page of the target programming sequence must be programmed with actual Page Program
command (10h).
Cache Program (available only within a block)
Note:
1. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after
completion of the previous cycle, which can be expressed as the following formula.
2. tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command cycle time + Last page data
loading time)
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F59L512M81A
Copy-Back Program
Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is
no bit error detected in the stored data. The benefit is particularly obvious when a portion of a block is updated and the rest of the block
needs to be copied to a newly assigned empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of
Copy-Back Program with Destination address. A Read for Copy-Back operation with “35h” command and the Source address moves
the whole 2,112byte data into the internal buffer. The host controller can detect bit errors by sequentially reading the data output.
Copy-Back Program is initiated by issuing Page-Copy Data-Input command (85h) with Destination address. If data modification is
necessary to correct bit errors and to avoid error propagation, data can be reloaded after the Destination address. Data modification
can be repeated multiple times as shown in Figure 33. Actual programming operation begins when Program Confirm command (10h) is
issued. Once the program process starts, the Read Status command (70h) may be entered to read the status register. The host
controller can detect the completion of a program cycle by monitoring the R/ B output, or the Status bit (I/O6) of the Status Register.
When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The command register remains Read Status mode
until another valid command is written to it.
Page Copy-Back Program Operation
Page Copy-Back Program Operation with Random Data Input
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F59L512M81A
Block Erase
The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a two-cycle row address, in which only
Plane address and Block address are valid while Page address is ignored. The Erase Confirm command (D0h) following the row
address starts the internal erasing process. The two-step command sequence is designed to prevent memory content from being
inadvertently changed by external noise.
At the rising edge of WE after the Erase Confirm command input, the internal control logic handles erase and erase-verify. When the
erase operation is completed, the host controller can check Status bit (I/O0) to see if the erase operation is successfully done. Figure
30 illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in between
commands 60h and D0h. After tBERS erase time, the R/ B de-asserts to ready state. Read Status command (70h) can be issued right
after D0h to check the execution status of erase operation.
Block Erase Operation
Read Status
A status register on the device is used to check whether program or erase operation is completed and whether the operation is
completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the status register to
I/O pins on the falling edge of CE or RE , whichever occurs last. These two commands allow the system to poll the progress of each
device in multiple memory connections even when R/ B pins are common-wired. RE or CE does not need to toggle for status
change.
The command register remains in Read Status mode unless other commands are issued to it. Therefore, if the status register is read
during a random read cycle, a read command (00h) is needed to start read cycles.
Status Register Definition for 70h Command
I/O
Page Program
Block Erase
I/O0
Pass / Fail
Pass / Fail
I/O1
NA
NA
I/O2
NA
(Pass / Fail, OTP)
NA
I/O3
NA
NA
I/O4
NA
NA
I/O5
NA
NA
True Ready / Busy
NA
I/O6
Ready / Busy
Ready / Busy
Ready / Busy
Write Protect
Ready / Busy
I/O7
Write Protect
Write Protect
Cache Program
Chip
Pass / Fail (N)
Plane 0
Pass / Fail (N)
Plane 1
Pass / Fail (N)
Plane 0
Pass / Fail (N-1)
Plane 1
Pass / Fail (N-1)
Read
Cache Read
NA
NA
Pass: ”0”
NA
NA
Don’t cared
NA
NA
Don’t cared
NA
NA
Don’t cared
NA
NA
Don’t cared
Write Protect
True Ready /
Busy
Ready / Busy
Write Protect
Definition
Busy: ”0”
Fail: ”1”
Ready: ”1”
Busy: ”0”
Ready: ”1”
Protected: ”0”
Not Protected: ”1”
Note:
1. I/Os defined ’NA’ are recommended to be masked out when Read Status is being executed.
2. n: current page, n-1: previous page.
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ESMT
F59L512M81A
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h.
Four read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th and 5th cycle ID respectively. The
command register remains in Read ID mode until further commands are issued to it.
Read ID Operation
ID Definition Table
ID Access command = 90h
1st Cycle
(Maker Code)
2nd Cycle
(Device Code)
3rd Cycle
4th Cycle
5th Cycle
C8h
D0h
90h
95h
30h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the
Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/ B pin changes to low for tRST after the Reset command is written. Refer to Figure below.
Device Status
Operation mode
After Power-up
After Reset
00h Command is latched
Waiting for next command
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F59L512M81A
Cache Read
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always
issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are
transferred from data registers to cache registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is
transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and
achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used
to complete data transfer from memory cells to data registers.
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F59L512M81A
READY/ BUSY
The device has an R/ B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/ B pin is normally high but transitions to low after program or erase command is written to the command
register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/ B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/ B )
and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart. Its value can be
determined by the following guidance.
where IL is the sum of the input currents of all devices tied to the R/ B pin.
RP (max) is determined by maximum permissible limit of tr
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F59L512M81A
Data Protection & Power-up sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the
initialization the device R/ B signal indicates the Busy state as shown in the figure below. In this time period, the acceptable
commands are 70h.
The WP signal is useful for protecting against data corruption at power on/off.
AC Waveforms for Power Transition
Write Protect Operation
Enable WP during erase and program busy is prohibited. The erase and program operations are enabled and disable as follows.
Enable Programming:
Note: WP keeps “High” until programming finish.
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F59L512M81A
Disable Programming:
Enable Erasing:
Note: WP keeps “High” until erasing finish.
Disable Erasing:
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ESMT
F59L512M81A
PACKING
DIMENSION
48-LEAD
TSOP(I) ( 12x20 mm )
Symbol
A
A1
A2
b
b1
c
c1
Dimension in mm
Min Norm Max
------- ------- 1.20
0.05 ------- 0.15
0.95 1.00
1.05
0.17 0.22
0.27
0.17 0.20
0.23
0.10 ------- 0.21
0.10 ------- 0.16
Dimension in inch
Dimension in mm
Symbol
Min Norm Max
Min Norm Max
------- ------- 0.047
D
20.00 BSC
0.006 ------- 0.002
D1
18.40 BSC
0.037 0.039 0.041
E
12.00 BSC
0.007 0.009 0.011
0.50 BSC
e
0.007 0.008 0.009
L
0.50 0.60
0.70
0.004 ------- 0.008
θ
0O
------8O
0.004 ------- 0.006
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min Norm Max
0.787 BSC
0.724 BSC
0.472 BSC
0.020 BSC
0.020 0.024 0.028
0O
------8O
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ESMT
F59L512M81A
Revision History
Revision
Date
0.1
2013.03.27
0.2
2013.05.07
0.3
2014.01.29
1.0
2014.05.27
Elite Semiconductor Memory Technology Inc.
Description
Original
1. Add Bad-Bloack-Protect
2. Modify the typical value of tPROG and tBERS
3. Modify the description of Identifying Initial Invalid
Block(s)
4. Modify 3rd and 5th ID Data of ID Definition
1. Correct typo
2. Add Cache Program into Status Register Definition for
70h Command table
3. Delete tDBSY
1. Delete "Preliminary"
2. Modify the description of Identifying Initial Invalid
Block(s) and Block Replacement Management
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F59L512M81A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
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