ESMT F25L32QA (2S) Flash 32 Mbit Serial Flash Memory with Dual and Quad FEATURES y y Single supply voltage 2.65~3.6V Standard, Dual and Quad SPI y Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz / 86MHz / 104MHz - Fast Read Dual/Quad max frequency: 50MHz / 86MHz / 104MHz (100MHz / 172MHz / 208MHz equivalent Dual SPI; 200MHz / 344MHz / 416MHz equivalent Quad SPI) y y y Low power consumption - Active current: 25 mA (max.) - Standby current: 30 μ A (max.) - Deep Power Down current: 10 μ A (max.) Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Page programming time: 1.5 ms (typical) y Erase - Chip Erase time 10 sec (typical) - 64K bytes Block Erase time 1 sec (typical) - 32K bytes Block Erase time 500 ms (typical) - 4K bytes Sector Erase time 120 ms (typical) y Page Programming - 256 byte per programmable page y Program / Erase Suspend y Lockable 512 bytes OTP security sector y SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 y End of program or erase detection y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID Speed F25L32QA –50PAG2S 50MHz F25L32QA –86PAG2S 86MHz F25L32QA –100PAG2S 104MHz F25L32QA –50PHG2S 50MHz F25L32QA –86PHG2S 86MHz Package Comments 8-lead SOIC 200 mil Pb-free 16-lead SOIC 300 mil Pb-free 8-contact WSON 6x5 mm Pb-free F25L32QA –100PHG2S 104MHz F25L32QA –50HG2S 50MHz F25L32QA –86HG2S 86MHz F25L32QA –100HG2S 104MHz Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 1/50 ESMT F25L32QA (2S) GENERAL DESCRIPTION The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 16,384 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device features sector erase architecture. The memory array is divided into 1,024 uniform sectors with 4K byte each; 128 uniform blocks with 32K byte each; 64 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. FUNCTIONAL BLOCK DIAGRAM Page Address Latch / Counter Memory Array High Voltage Generator Page Buffer Status Register Byte Address Latch / Counter Y-Decoder Command and Conrol Logic Serial Interface CE SCK SI (SIO0) SO WP HOLD (SIO1) (SIO2) (SIO3) Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 2/50 ESMT F25L32QA (2S) PIN CONFIGURATIONS 8-Lead SOIC (SOIC 8L, 208mil Body, 1.27mm Pin Pitch) CE 1 8 VDD SO / SIO1 2 7 HOLD / SIO3 WP / SIO2 3 6 SCK VSS 4 5 SI / SIO0 16-Lead SOIC (SOIC 16L, 300mil Body, 1.27mm Pin Pitch) HOLD / SIO3 1 16 SCK VDD 2 15 SI / SIO0 NC 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC CE 7 10 VSS 8 9 WP / SIO2 SO / SIO1 Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 3/50 ESMT F25L32QA (2S) 8- Contact WSON (WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch) CE 1 8 VDD SO / SIO1 2 7 HOLD / SIO3 WP / SIO2 3 6 SCK VSS 4 5 SI / SIO 0 PIN DESCRIPTION Symbol Pin Name SCK Serial Clock SI / SIO0 Serial Data Input / Serial Data Input Output 0 SO / SIO1 Serial Data Output / Serial Data Input Output 1 CE Chip Enable WP / SIO2 Write Protect / Serial Data Input Output 2 The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). HOLD / SIO3 Hold / Serial Data Input Output 3 To temporality stop serial communication with SPI flash memory without resetting the device. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). VDD Power Supply VSS Ground Elite Semiconductor Memory Technology Inc. Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK(for Dual/Quad mode). To transfer data serially out of the device. Data is shifted out on the falling edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Dual/Quad mode). To activate the device when CE is low. To provide power. Publication Date: Sep. 2012 Revision: 1.3 4/50 ESMT F25L32QA (2S) SECTOR STRUCTURE Table 1: Sector Address Table 64KB Block 32KB Block 127 63 126 125 62 124 123 61 122 121 60 120 119 59 118 117 58 116 Sector Sector Size (Kbytes) Address range 1023 4KB 3FF000H – 3FFFFFH : : : 1016 4KB 3F8000H – 3F8FFFH 1015 4KB 3F7000H – 3F7FFFH : : : 1008 4KB 3F0000H – 3F0FFFH 1007 4KB 3EF000H – 3EFFFFH : : : 1000 4KB 3E8000H – 3E8FFFH 999 4KB 3E7000H – 3E7FFFH : : : 992 4KB 3E0000H – 3E0FFFH 991 4KB 3DF000H – 3DFFFFH : : : 984 4KB 3D8000H – 3D8FFFH 983 4KB 3D7000H – 3D7FFFH : : : 976 4KB 3D0000H – 3D0FFFH 975 4KB 3CF000H – 3CFFFFH : : : 968 4KB 3C8000H – 3C8FFFH 967 4KB 3C7000H – 3C7FFFH : : : 960 4KB 3C0000H – 3C0FFFH 959 4KB 3BF000H – 3BFFFFH : : : 952 4KB 3B8000H – 3B8FFFH 951 4KB 3B7000H – 3B7FFFH : : : 944 4KB 3B0000H – 3B0FFFH 943 4KB 3AF000H – 3AFFFFH : : : 936 4KB 3A8000H – 3A8FFFH 935 4KB 3A7000H – 3A7FFFH : : : 928 4KB 3A0000H – 3A0FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 0 Publication Date: Sep. 2012 Revision: 1.3 5/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued I 64KB Block 32KB Block 115 57 114 113 56 112 111 55 110 109 54 108 107 53 106 105 52 104 103 51 102 Sector Sector Size (Kbytes) Address range 927 4KB 39F000H – 39FFFFH : : : 920 4KB 398000H – 398FFFH 919 4KB 397000H – 397FFFH : : : 912 4KB 390000H – 390FFFH 911 4KB 38F000H – 38FFFFH : : : 904 4KB 388000H – 388FFFH 903 4KB 387000H – 387FFFH : : : 896 4KB 380000H – 380FFFH 895 4KB 37F000H – 37FFFFH : : : 888 4KB 378000H – 378FFFH 887 4KB 377000H – 377FFFH : : : 880 4KB 370000H – 370FFFH 879 4KB 36F000H – 36FFFFH : : : 872 4KB 368000H – 368FFFH 871 4KB 367000H – 367FFFH : : : 864 4KB 360000H – 360FFFH 863 4KB 35F000H – 35FFFFH : : : 856 4KB 358000H – 358FFFH 855 4KB 357000H – 357FFFH : : : 848 4KB 350000H – 350FFFH 847 4KB 34F000H – 34FFFFH : : : 840 4KB 348000H – 348FFFH 839 4KB 347000H – 347FFFH : : : 832 4KB 340000H – 340FFFH 831 4KB 33F000H – 33FFFFH : : : 824 4KB 338000H – 338FFFH 823 4KB 337000H – 337FFFH : : : 816 4KB 330000H – 330FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 0 0 1 1 Publication Date: Sep. 2012 Revision: 1.3 6/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued II 64KB Block 32KB Block 101 50 100 99 49 98 97 48 96 95 47 94 93 46 92 91 45 90 89 44 88 Sector Sector Size (Kbytes) Address range 815 4KB 32F000H – 32FFFFH : : : 808 4KB 328000H – 328FFFH 807 4KB 327000H – 327FFFH : : : 800 4KB 320000H – 320FFFH 799 4KB 31F000H – 31FFFFH : : : 792 4KB 318000H – 318FFFH 791 4KB 317000H – 317FFFH : : : 784 4KB 310000H – 310FFFH 783 4KB 30F000H – 30FFFFH : : : 776 4KB 308000H – 308FFFH 775 4KB 307000H – 307FFFH : : : 768 4KB 300000H – 300FFFH 767 4KB 2FF000H – 2FFFFFH : : : 760 4KB 2F8000H – 2F8FFFH 759 4KB 2F7000H – 2F7FFFH : : : 752 4KB 2F0000H – 2F0FFFH 751 4KB 2EF000H – 2EFFFFH : : : 744 4KB 2E8000H – 2E8FFFH 743 4KB 2E7000H – 2E7FFFH : : : 736 4KB 2E0000H – 2E0FFFH 735 4KB 2DF000H – 2DFFFFH : : : 728 4KB 2D8000H – 2D8FFFH 727 4KB 2D7000H – 2D7FFFH : : : 720 4KB 2D0000H – 2D0FFFH 719 4KB 2CF000H – 2CFFFFH : : : 712 4KB 2C8000H – 2C8FFFH 711 4KB 2C7000H – 2C7FFFH : : : 704 4KB 2C0000H – 2C0FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 Publication Date: Sep. 2012 Revision: 1.3 7/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued III 64KB Block 32KB Block 87 43 86 85 42 84 83 41 82 81 40 80 79 39 78 77 38 76 75 37 74 Sector Sector Size (Kbytes) Address range 703 4KB 2BF000H – 2BFFFFH : : : 696 4KB 2B8000H – 2B8FFFH 695 4KB 2B7000H – 2B7FFFH : : : 688 4KB 2B0000H – 2B0FFFH 687 4KB 2AF000H – 2AFFFFH : : : 680 4KB 2A8000H – 2A8FFFH 679 4KB 2A7000H – 2A7FFFH : : : 672 4KB 2A0000H – 2A0FFFH 671 4KB 29F000H – 29FFFFH : : : 664 4KB 298000H – 298FFFH 663 4KB 297000H – 297FFFH : : : 656 4KB 290000H – 290FFFH 655 4KB 28F000H – 28FFFFH : : : 648 4KB 288000H – 288FFFH 647 4KB 287000H – 287FFFH : : : 640 4KB 280000H – 280FFFH 639 4KB 27F000H – 27FFFFH : : : 632 4KB 278000H – 278FFFH 631 4KB 277000H – 277FFFH : : : 624 4KB 270000H – 270FFFH 623 4KB 26F000H – 26FFFFH : : : 616 4KB 268000H – 268FFFH 615 4KB 267000H – 267FFFH : : : 608 4KB 260000H – 260FFFH 607 4KB 25F000H – 25FFFFH : : : 600 4KB 258000H – 258FFFH 599 4KB 257000H – 257FFFH : : : 592 4KB 250000H – 250FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 0 1 Publication Date: Sep. 2012 Revision: 1.3 8/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued IV 64KB Block 32KB Block 73 36 72 71 35 70 69 34 68 67 33 66 65 32 64 63 31 62 61 30 60 Sector Sector Size (Kbytes) Address range 591 4KB 24F000H – 24FFFFH : : : 584 4KB 248000H – 248FFFH 583 4KB 247000H – 247FFFH : : : 576 4KB 240000H – 240FFFH 575 4KB 23F000H – 23FFFFH : : : 568 4KB 238000H – 238FFFH 567 4KB 237000H – 237FFFH : : : 560 4KB 230000H – 230FFFH 559 4KB 22F000H – 22FFFFH : : : 552 4KB 228000H – 228FFFH 551 4KB 227000H – 227FFFH : : : 544 4KB 220000H – 220FFFH 543 4KB 21F000H – 21FFFFH : : : 536 4KB 218000H – 218FFFH 535 4KB 217000H – 217FFFH : : : 528 4KB 210000H – 210FFFH 527 4KB 20F000H – 20FFFFH : : : 520 4KB 208000H – 208FFFH 519 4KB 207000H – 207FFFH : : : 512 4KB 200000H – 200FFFH 511 4KB 1FF000H – 1FFFFFH : : : 504 4KB 1F8000H – 1F8FFFH 503 4KB 1F7000H – 1F7FFFH : : : 496 4KB 1F0000H – 1F0FFFH 495 4KB 1EF000H – 1EFFFFH : : : 488 4KB 1E8000H – 1E8FFFH 487 4KB 1E7000H – 1E7FFFH : : : 480 4KB 1E0000H – 1E0FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 Publication Date: Sep. 2012 Revision: 1.3 9/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued V 64KB Block 32KB Block 59 29 58 57 28 56 55 27 54 53 26 52 51 25 50 49 24 48 47 23 46 Sector Sector Size (Kbytes) Address range 479 4KB 1DF000H – 1DFFFFH : : : 472 4KB 1D8000H – 1D8FFFH 471 4KB 1D7000H – 1D7FFFH : : : 464 4KB 1D0000H – 1D0FFFH 463 4KB 1CF000H – 1CFFFFH : : : 456 4KB 1C8000H – 1C8FFFH 455 4KB 1C7000H – 1C7FFFH : : : 448 4KB 1C0000H – 1C0FFFH 447 4KB 1BF000H – 1BFFFFH : : : 440 4KB 1B8000H – 1B8FFFH 439 4KB 1B7000H – 1B7FFFH : : : 432 4KB 1B0000H – 1B0FFFH 431 4KB 1AF000H – 1AFFFFH : : : 424 4KB 1A8000H – 1A8FFFH 423 4KB 1A7000H – 1A7FFFH : : : 416 4KB 1A0000H – 1A0FFFH 415 4KB 19F000H – 19FFFFH : : : 408 4KB 198000H – 198FFFH 407 4KB 197000H – 197FFFH : : : 400 4KB 190000H – 190FFFH 399 4KB 18F000H – 18FFFFH : : : 392 4KB 188000H – 188FFFH 391 4KB 187000H – 187FFFH : : : 384 4KB 180000H – 180FFFH 383 4KB 17F000H – 17FFFFH : : : 376 4KB 178000H – 178FFFH 375 4KB 177000H – 177FFFH : : : 368 4KB 170000H – 170FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 0 1 1 1 Publication Date: Sep. 2012 Revision: 1.3 10/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued VI 64KB Block 32KB Block 45 22 44 43 21 42 41 20 40 39 19 38 37 18 36 35 17 34 33 16 32 Sector Sector Size (Kbytes) Address range 367 4KB 16F000H – 16FFFFH : : : 360 4KB 168000H – 168FFFH 359 4KB 167000H – 167FFFH : : : 352 4KB 160000H – 160FFFH 351 4KB 15F000H – 15FFFFH : : : 344 4KB 158000H – 158FFFH 343 4KB 157000H – 157FFFH : : : 336 4KB 150000H – 150FFFH 335 4KB 14F000H – 14FFFFH : : : 328 4KB 148000H – 148FFFH 327 4KB 147000H – 147FFFH : : : 320 4KB 140000H – 140FFFH 319 4KB 13F000H – 13FFFFH : : : 312 4KB 138000H – 138FFFH 311 4KB 137000H – 137FFFH : : : 304 4KB 130000H – 130FFFH 303 4KB 12F000H – 12FFFFH : : : 296 4KB 128000H – 128FFFH 295 4KB 127000H – 127FFFH : : : 288 4KB 120000H – 120FFFH 287 4KB 11F000H – 11FFFFH : : : 280 4KB 118000H – 118FFFH 279 4KB 117000H – 117FFFH : : : 272 4KB 110000H – 110FFFH 271 4KB 10F000H – 10FFFFH : : : 264 4KB 108000H – 108FFFH 263 4KB 107000H – 107FFFH : : : 256 4KB Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 100000H – 100FFFH Publication Date: Sep. 2012 Revision: 1.3 11/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued VII 64KB Block 32KB Block 31 15 30 29 14 28 27 13 26 25 12 24 23 11 22 21 10 20 19 9 18 Sector Sector Size (Kbytes) 255 4KB : : : 248 4KB 0F8000H – 0F8FFFH 247 4KB 0F7000H – 0F7FFFH : : : Address range A21 A20 A19 A18 A17 A16 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 0 0 1 0FF000H – 0FFFFFH 240 4KB 0F0000H – 0F0FFFH 239 4KB 0EF000H – 0EFFFFH : : : 232 4KB 0E8000H – 0E8FFFH 231 4KB 0E7000H – 0E7FFFH : : 224 4KB 0E0000H – 0E0FFFH 223 4KB 0DF000H – 0DFFFFH : : : : 216 4KB 0D8000H – 0D8FFFH 215 4KB 0D7000H – 0D7FFFH : : : 208 4KB 0D0000H – 0D0FFFH 207 4KB 0CF000H – 0CFFFFH : : : 200 4KB 0C8000H – 0C8FFFH 199 4KB 0C7000H – 0C7FFFH : : : 192 4KB 0C0000H – 0C0FFFH 191 4KB 0BF000H – 0BFFFFH : : : 184 4KB 0B8000H – 0B8FFFH 183 4KB 0B7000H – 0B7FFFH : : 176 4KB 0B0000H – 0B0FFFH 175 4KB 0AF000H – 0AFFFFH : : : : 168 4KB 0A8000H – 0A8FFFH 167 4KB 0A7000H – 0A7FFFH : : : 160 4KB 0A0000H – 0A0FFFH 159 4KB 09F000H – 09FFFFH : : : 152 4KB 098000H – 098FFFH 151 4KB 097000H – 097FFFH : : : 144 4KB 090000H – 090FFFH Elite Semiconductor Memory Technology Inc. Block Address Publication Date: Sep. 2012 Revision: 1.3 12/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued VIII 64KB Block 32KB Block 17 8 16 15 7 14 13 6 12 11 5 10 9 4 8 7 3 6 5 2 4 Sector Sector Size (Kbytes) Address range 143 4KB 08F000H – 08FFFFH : : : 136 4KB 088000H – 088FFFH 135 4KB 087000H – 087FFFH : : : 128 4KB 080000H – 080FFFH 127 4KB 07F000H – 07FFFFH : : : 120 4KB 078000H – 078FFFH 119 4KB 077000H – 077FFFH : : : 112 4KB 070000H – 070FFFH 111 4KB 06F000H – 06FFFFH : : : 104 4KB 068000H – 068FFFH 103 4KB 067000H – 067FFFH : : : 96 4KB 060000H – 060FFFH 95 4KB 05F000H – 05FFFFH : : : 88 4KB 058000H – 058FFFH 87 4KB 057000H – 057FFFH : : : 80 4KB 050000H – 050FFFH 79 4KB 04F000H – 04FFFFH : : : 72 4KB 048000H – 048FFFH 71 4KB 047000H – 047FFFH : : : 64 4KB 040000H – 040FFFH 63 4KB 03F000H – 03FFFFH : : : 56 4KB 038000H – 038FFFH 55 4KB 037000H – 037FFFH : : : 48 4KB 030000H – 030FFFH 47 4KB 02F000H – 02FFFFH : : : 40 4KB 028000H – 028FFFH 39 4KB 027000H – 027FFFH : : : 32 4KB 020000H – 020FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 Publication Date: Sep. 2012 Revision: 1.3 13/50 ESMT F25L32QA (2S) Table 1: Sector Address Table – Continued VIIII 64KB Block 32KB Block 3 1 2 1 0 0 Sector Sector Size (Kbytes) Address range 31 4KB 01F000H – 01FFFFH : : : 24 4KB 018000H – 018FFFH 23 4KB 017000H – 017FFFH : : : 16 4KB 010000H – 010FFFH 15 4KB 00F000H – 00FFFFH : : : 8 4KB 008000H – 008FFFH 7 4KB 007000H – 007FFFH : : : 0 4KB 000000H – 000FFFH Elite Semiconductor Memory Technology Inc. Block Address A21 A20 A19 A18 A17 A16 0 0 0 0 0 1 0 0 0 0 0 0 Publication Date: Sep. 2012 Revision: 1.3 14/50 ESMT F25L32QA (2S) STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit Name Function Default at Power-up Read/Write 0 R 0 R 0 0 0 0 R/W R/W R/W R/W 0 R/W 0 R/W Default at Power-up Read/Write 0 0 R N/A Status Register -1 0 BUSY 1 WEL 2 3 4 5 BP0 BP1 BP2 BP3 6 QE 7 BPL Bit Name Status Register -2 8 SUS 9~15 Reserved 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) 1 = Quad enabled 0 = Quad disabled 1 = BP3, BP2,BP1,BP0 are read-only bits 0 = BP3, BP2,BP1,BP0 are read/writable Function Suspend Status Reserved for future use Note: 1. BUSY and WEL are read only. 2. BP0~3, QE and BPL bits are non-volatile. 3. All area are not protected at power-on (BP3=BP2=BP1=BP0=0) Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: • • • • • • • BUSY The BUSY bit determines whether there is an internal Erase or Program operation in progress. A “1” for the BUSY bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instructions Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 15/50 ESMT F25L32QA (2S) Table 3: F25L32QA Block Protection Table Protection Level Status Register Bit BP3 BP2 BP1 Protected Memory Area BP0 64KB Block Range Address Range 0 0 0 0 0 None None Upper 1/64 0 0 0 1 Block 63 3F0000H – 3FFFFFH Upper 1/32 0 0 1 0 Block 62~63 3E0000H – 3FFFFFH Upper 1/16 0 0 1 1 Block 60~63 3C0000H – 3FFFFFH Upper 1/8 0 1 0 0 Block 56~63 380000H – 3FFFFFH Upper 1/4 0 1 0 1 Block 48~63 300000H – 3FFFFFH Upper 1/2 0 1 1 0 Block 32~63 200000H – 3FFFFFH All Blocks 0 1 1 1 Block 0~63 000000H – 3FFFFFH All Blocks 1 0 0 0 Block 0~63 000000H – 3FFFFFH Bottom 32/64 1 0 0 1 Block 0~31 000000H – 1FFFFFH Bottom 48/64 1 0 1 0 Block 0~47 000000H – 2FFFFFH Bottom 56/64 1 0 1 1 Block 0~55 000000H –37FFFFH Bottom 60/64 1 1 0 0 Block 0~59 000000H – 3BFFFFH Bottom 62/64 1 1 0 1 Block 0~61 000000H – 3DFFFFH Bottom 63/64 1 1 1 0 Block 0~62 000000H – 3EFFFFH All Blocks 1 1 1 1 Block 0~63 000000H – 3FFFFFH Block Protection (BP3, BP2, BP1, BP0) Block Protection Lock-Down (BPL) The Block-Protection (BP3, BP2, BP1, BP0) bits define the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When BP3, BP2, BP1 and BP0 bits as long as WP is high or the Block- Protection-Look (BPL) bit is 0. Chip Erase can only be executed if BP3, BP2, BP1 and BP0 bits are all 0. After power-up, BP3, BP2, BP1 and BP0 bits are set to 0. the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Quad Enable (QE) Program / Erase Suspend Status (SUS) When the Quad Enable bit is reset to “0” (factory default), WP The Suspend Status bit is a read only bit in the status register that is set to 1 after executing a Program / Erase Suspend (75H) instruction. The SUS Status bit is cleared to 0 by Program / Erase Resume (7AH) instruction as well as a power-down, power-up cycle. and HOLD pins are enabled. When QE pin is set to “1”, Quad SIO2 and SIO3 are enabled. (The QE should never be set to “1” during standard and Dual SPI operation if the WP and HOLD pins are tied directly to the VDD or VSS.) Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 16/50 ESMT F25L32QA (2S) HOLD OPERATION HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. HOLD mode begins when the SCK active low state coincides If CE is driven active high during a Hold condition, it resets the with the falling edge of the HOLD signal. The HOLD mode ends internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 35 for Hold timing. The HOLD function is only available for Standard SPI and Dual SPI operation, not during Quad SPI because this pin is used for SIO3 when the QE bit of Status Register-1 is set for Quad I/O. S CK HO L D A ctive A ctive Ho ld Ho ld A ctive Figure 1: HOLD Condition Waveform WRITE PROTECTION The device provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0 and BPL) in the status register provide Write protection to the memory array and the status register. When the QE bit of Status Register-1 is set for Quad I/O, the WP pin function is not available since this pin is used for SIO2. Table 4: Conditions to Execute Write-Status- Register (WRSR) Instruction WP BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed Write Protect Pin ( WP ) The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 17/50 ESMT F25L32QA (2S) INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L32QA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. significant bit. CE must be driven low before an instruction is Table 5: Device Operation Instruction Max. Freq Operation Read Fast Read 12,13 Fast Read Dual Output 12, 14 Fast Read Dual I/O Fast Read Quad 12, 15 Output Fast Read Quad I/O12, 16 Sector Erase4 (4K Byte) Block Erase5 (32K Byte) Block Erase5 (64K Byte) 1 2 SIN SOUT SIN SOUT 33 MHz 03H Hi-Z A23-A16 Hi-Z 0BH Hi-Z A23-A16 Hi-Z 3BH A23-A16 BBH A23-A8 Program / Erase Suspend Program / Erase Resume 50MHz Mode Bit Reset ~ Deep Power Down (DP) Read Status Register-1 (RDSR-1) 7 Read Status Register-2 104MHz 7 (RDSR-2) Write Status Register 10 (WRSR) Write Enable (WREN) 10 Write Disable (WRDI)/ Exit secured OTP mode Enter secured OTP mode (ENSO) Release from Deep Power Down (RDP) Read Electronic Signature (RES) 8 RES in secured OTP mode & not lock down RES in secured OTP mode & lock down Hi-Z A23-A16 02H Quad Page Program17 18 A15-A8 EBH A23-A0, M7-M0 20H Hi-Z A23-A16 Hi-Z 52H Hi-Z A23-A16 Hi-Z D8H Hi-Z A23-A16 Hi-Z 60H / Hi-Z C7H 75H Hi-Z 7AH Hi-Z - Chip Erase Page Program (PP) 6 A23-A16 6BH 32H Hi-Z A23-A16 FFH B9h Hi-Z Hi-Z FFH - 05H Hi-Z X 35H Hi-Z X 01H Hi-Z 06H Hi-Z DIN (S7-S0) - 04H Hi-Z B1H Bus Cycle 1~3 3 4 SIN SOUT SIN SOUT A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 A7-A0 A7-A0, M7-M0 DOUT0~1 SOUT DOUT0 X X cont. A7-A0 X X, DOUT0~1 DOUT2~6 A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z 6 SIN SOUT X DOUT1 X DOUT0 DOUT0~1 - cont. SOUT cont. cont. cont. - cont. - - - - - - - - - - - - - - - - - - - - - - - DIN0 Hi-Z Hi-Z A7-A0 Hi-Z X X - - A15-A8 N SIN DOUT0~3 - A15-A8 A7-A0 DIN0~3 Up to DIN1 Hi-Z 256 Hi-Z bytes Up to 256 DIN4~7 byte - - - - - - - - - - - - - - - - - - - - - - - - - - - Hi-Z - - -. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Hi-Z - - - - -. - - - - - - - ABH Hi-Z - - - - - - - - - - - - ABH Hi-Z X X X X X X X 15H - - - - ABH Hi-Z X X X X X X X 35H - - - - ABH Hi-Z X X X X X X X 75H - - - - Elite Semiconductor Memory Technology Inc. Hi-Z DOUT (S7-S0) DOUT (S15-S8) 5 SIN X X Publication Date: Sep. 2012 Revision: 1.3 18/50 ESMT F25L32QA (2S) Table 5: Device Operation Instruction - Continued Max. Freq Operation Jedec Read ID 9 (JEDEC-ID) Read ID (RDID) 11 1 2 Bus Cycle 1~3 3 4 SOUT SIN SOUT SIN SOUT SIN SOUT SIN 50MHz 9FH ~ 104MHz 90H Hi-Z X 8CH X 41H X Hi-Z 00H Hi-Z 00H Hi-Z 00H 01H 5 6 N SIN SOUT SIN SOUT SIN SOUT 16H - - - - - - Hi-Z Hi-Z X X 8CH 15H X X 15H 8CH - - Notes: 1. 2. 3. 4. 5. 6. 7. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous One bus cycle is eight clock periods. 4K byte Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH. 32K byte Block Earse addresses: use AMS -A15, remaining addresses can be VIL or VIH 64K byte Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . The JEDEC-Read-ID is output first byte 8CH as manufacture ID; second byte 41 as memory type; third byte 16H as memory capacity. 10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. A successful WRSR can reset WREN. 8. 9. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual and Quad commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 13. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1) DOUT0 DOUT1 14. M7-M0: Mode bits. Dual input address: IO0 = (A22, A20, A18, A16, A14, A12, A10, A8) IO1 = (A23, A21, A19, A17, A15, A13, A11, A9) Bus Cycle-2 (A6, A4, A2, A0, M6, M4, M2, M0) (A7, A5, A3, A1, M7, M5, M3, M1) Bus Cycle-3 15. Quad output data: IO0 = (D4, D0), (D4, D0), (D4, D0), (D4, D0) IO1 = (D5, D1), (D5, D1), (D5, D1), (D5, D1) IO2 = (D6, D2), (D6, D2), (D6, D2), (D6, D2) IO3 = (D7, D3), (D7, D3), (D7, D3), (D7, D3) DOUT0 DOUT1 DOUT2 DOUT3 Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 19/50 ESMT F25L32QA (2S) 16. M7-M0: Mode bits. Quad input address: IO0 = (A20, A16, A12, A8, A4, A0, M4, M0) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3) Bus Cycle-2 Fast Read Quad I/O data: IO0 = (X, X), (X, X), (D4, D0), (D4, D0) IO1 = (X, X), (X, X), (D5, D1), (D5, D1) IO2 = (X, X), (X, X), (D6, D2), (D6, D2) IO3 = (X, X), (X, X), (D7, D3), (D7, D3) DOUT0 DOUT1 (D4, D0), (D4, D0), (D4, D0), (D4, D0) (D5, D1), (D5, D1), (D5, D1), (D5, D1) (D6, D2), (D6, D2), (D6, D2), (D6, D2) (D7, D3), (D7, D3), (D7, D3), (D7, D3) DOUT2 Bus Cycle-3 DOUT3 DOUT4 DOUT5 Bus Cycle-4 17. The instruction is initiated by executing command code, followed by address bits into SI (SIO0) before DIN, and then input data to bidirectional IO pins (SIO0 ~ SIO3). Quad input data: IO0 = (D4, D0), (D4, D0), (D4, D0), (D4, D0) IO1 = (D5, D1), (D5, D1), (D5, D1), (D5, D1) IO2 = (D6, D2), (D6, D2), (D6, D2), (D6, D2) IO3 = (D7, D3), (D7, D3), (D7, D3), (D7, D3) DIN0 DIN1 DIN2 DIN3 18. This instruction is recommended when using the Dual or Quad Mode bit feature. Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 20/50 ESMT F25L32QA (2S) Read (33MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a the data from address location 3FFFFFH had been read, the next output will be from address location 000000H. low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 32Mbit density, once The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2: Read Sequence Fast Read (50 MHz ~ 104 MHz) The Fast Read instruction supporting up to 104 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 32Mbit density, once the data from address location 3FFFFFH has been read, the next output will be from address location 000000H. [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 ADD. 0B SI MSB SO 15 16 23 24 ADD. 31 32 ADD. 39 40 47 48 55 56 63 64 71 72 80 X MSB HIGH IMPENANCE N N+1 N+2 N+3 N+4 DOUT DOUT DOUT DOUT DOUT MSB Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3: Fast Read Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 21/50 ESMT F25L32QA (2S) Fast Read Dual Output (50 MHz ~ 104 MHz) The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A23 -A0] and a The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruction except the data is output on bidirectional I/O pins (SIO0 and SIO1). This allows data to be transferred from the device at twice the rate of standard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution. dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 3B MSB SIO1 ADD. MSB HIGH IMPENANCE ADD. ADD. 55 56 51 52 IO0 switches from In put to Ouput Dummy SIO0 47 48 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 D OUT DOUT D OU T D OU T D OUT N N+1 N+2 N+3 N+4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 Note: The input data durin g the dummy clocks is “don’t care”. However , the IO0 pin should be high-impefance piror to th e falling edge of the first data clock. Figure 4: Fast Read Dual Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 22/50 ESMT F25L32QA (2S) Fast Read Dual I/O (50 MHz ~ 104 MHz) The Fast Read Dual I/O (BBH) instruction is similar to the Fast Read Dual Output (3BH) instruction, but with the capability to input address bits [A23 -A0] two bits per clock. If [M7 –M0] = “AxH”, the next Fast Read Dual I/O instruction (after To set mode bits [M7 -M0] after the address bits [A23 -A0] can further reduce instruction overhead (See Figure 5). The upper mode bits [M7 –M4] controls the length of next Fast Read Dual I/O instruction with/without the first byte command code (BBH). The lower mode bits [M3 –M0] are “don’t care”. clocks and allows to enter address immediately after CE is asserted low. If [M7 –M0] are the value other than “AxH”, the next instruction need the first byte command code, thus returning to normal operation. A Mode Bit Reset (FFH) also can be used to reset mode bits [M7 –M0] before issuing normal instructions. CE is raised and the lowered) doesn’t need the command code (See Figure 6). This way let the instruction sequence reduce 8 CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 31 32 35 36 39 40 IO0 switches from Input to Ouput SIO0 22 20 18 16 14 12 10 8 BB 6 4 2 0 6 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 4 MSB HIG H IMPENANCE SIO1 23 21 19 17 15 13 11 9 A23-16 7 5 A15-8 3 1 A7- 0 7 DOUT D OU T DOUT DOUT DOUT N N+1 N+2 N+3 N+4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 5 M7- 0 Note: The mode bits [M3 -M0] are “d on’t care”. However , the IO pins sh ould be high-impefance piror to the falling edge of the first data clock. Figure 5: Fast Read Dual I/O Sequence ([M7 -M0] = 0xH or NOT AxH) CE MODE3 SCK MODE0 IO0 switches from In put to Ouput SIO0 SIO1 22 20 18 16 14 12 10 8 23 21 19 17 15 13 11 A23- 16 A15- 8 9 6 7 4 5 2 3 A7-0 0 1 6 7 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 4 5 DOUT DOUT D OU T D OUT D OUT N N+1 N+2 N+3 N+4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 M 7-0 Note: The mode bits [M3 -M0] are “don’t care”. However , the IO pins sh ould be high-impe fance piror to the fa ll ing edge of the fi rst data clock. Figure 6: Fast Read Dual I/O Sequence ([M7 -M0] = AxH) Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 23/50 ESMT F25L32QA (2S) Fast Read Quad Output (50 MHz ~ 104 MHz) The Fast Read Quad Output (6B) instruction is similar to the Fast Read Dual Output (3BH) instruction except the data is output on bidirectional I/O pins (SIO0, SIO1, SIO2 and SIO3). A Quad Enable (QE) bit of Status Register-1 must be set “1” to enable Quad function. This allows data to be transferred from the device at four times the rate of standard SPI devices. The Fast Read Quad Output instruction is initiated by executing an 8-bit command, 6BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 7 for the Fast Read Quad Output sequence. CE MODE3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 4142 43 44 45 46 47 48 MODE0 Dummy 6B SIO0 ADD. MSB MSB SIO1 SIO2 SIO3 HIGH IMPENANCE ADD. A DD. IO0 switches from Input to Ouput 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 HIGH IMPENANCE 6 2 HIGH IMPENANCE 7 3 N N+1 N+2 N+3 N+4 D OU T DOUT DOUT D OU T D OUT Note: The input data du ring the dummy clocks is “don’t care”. However , the IO pins should be high-impefance piror to the fal ling edge o f the first data clock. Figure 7: Fast Read Quad Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 24/50 ESMT F25L32QA (2S) Fast Read Quad I/O (50 MHz ~ 104 MHz) The Fast Read Quad I/O (EBH) instruction is similar to the Fast Read Quad Output (6BH) instruction, but with the capability to input address bits [A23 -A0] four bits per clock. A Quad Enable (QE) bit of Status Register-1 must be set “1” to enable Quad function. If [M7 –M0] = “AxH”, the next Fast Read Quad I/O instruction (after CE is raised and the lowered) doesn’t need the command code (See Figure 9). This way let the instruction sequence reduce 8 clocks and allows to enter address immediately after CE is asserted low. If [M7 –M0] are the value other than “AxH”, the next instruction need the first byte command code, thus returning to normal operation. A Mode Bit Reset (FFH) also can be used to reset mode bits [M7 –M0] before issuing normal instructions. To set mode bits [M7 -M0] after the address bits [A23 -A0] can further reduce instruction overhead (See Figure 8). The upper mode bits [M7 –M4] controls the length of next Fast Read Quad I/O instruction with/without the first byte command code (EBH). The lower mode bits [M3 –M0] are “don’t care”. CE 0 1 2 3 4 5 6 7 8 MODE3 SCK MODE0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 IO0 switches from Input to Ouput Dummy EB SIO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 21 17 13 9 5 1 5 1 5 1 5 1 5 1 22 18 14 10 6 2 6 2 6 2 6 2 6 2 23 19 15 11 7 3 7 3 7 3 7 3 7 3 MSB HIGH IMPE NANCE SIO1 HIGH IMPENANCE SIO2 HIGH IMP ENANCE SIO3 A 23- 0 M7 -0 N N+1 N+2 DOUT DOUT DOUT Note: The mode bits [M3 -M0] are “don’t care”. However , the IO pins sh ould be high-impe fance piror to the fall ing edge of the fi rst data clock. Figure 8: Fast Read Quad I/O Sequence ([M7 -M0] = 0xH or NOT AxH) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Dummy IO0 switches from Input to Oup ut 20 16 12 8 4 0 4 0 4 0 4 0 4 0 SIO1 21 1 7 13 9 5 1 5 1 5 1 5 1 5 1 SIO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 SIO3 23 19 15 11 3 7 3 7 3 7 3 7 3 SIO0 7 A23-0 M7-0 N N+1 N+2 D OUT D OUT D OU T Note: The mode bits [M3 -M0] are “don’t care”. However , the IO pins sh ould be high-imp efance piror to the falling edge of the fi rst data clock. Figure 9: Fast Read Quad I/O Sequence ([M7 -M0] = AxH) Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 25/50 ESMT F25L32QA (2S) Page Program (PP) The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Prior to any Write operation, the Write Enable (WREN) instruction CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the software status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register-1 is cleared to 0. See Figure 10 for the Page Program sequence. must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A7-A0] are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are sent to the device, previously Figure 10: Page Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 26/50 ESMT F25L32QA (2S) Quad Page Program the clock speed <20MHz. The Quad Page Program instruction allows many bytes to be programmed in the memory by using four I/O pins (SIO0, SIO1, SIO2 and SIO3). The instruction can improve programmer performance and the effectiveness of application that have slow clock speed <20MHz. For system with faster clock, this instruction can’t provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that user can execute this command while Prior to Quad Page Program operation, the Write Enable (WREN) instruction must be executed and Quad Enable (QE) bit of Status Register-1 must be set “1”. The other function descriptions are as same as standard Page Program. See Figure 11 for the Quad Page Program sequence. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 15 1 6 23 24 31 32 33 34 35 36 37 3839 SS 32 SIO0 MSB SIO1 ADD. MSB ADD. A DD. 4 0 4 0 4 0 4 0 SS 4 0 5 1 5 1 5 1 5 1 SS 5 1 SS 6 2 SS 7 3 SIO2 SIO3 D IN 0 D IN 1 DIN2 DIN3 DIN2 55 Figure 11: Quad Page Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 27/50 ESMT F25L32QA (2S) Mode Bit Reset Mode bits [M7 –M0] are issued to further reduce instruction overhead for Fast Read Dual/Quad I/O operation. If [M7 –M0] = “AxH”, the next Fast Read Dual/Quad I/O instruction doesn’t need the command code. However, the device doesn’t have a hardware reset pin, so if [M7 –M0] = “AxH”, the device will not recognize any standard SPI instruction. After a system reset, it is recommended to issue a Mode Bit Reset instruction first to release the status of [M7 –M0] = “AxH” and allow the device to recognize standard SPI instruction. See Figure 12 for the Mode Bit Reset instruction. If the system controller is reset during operation, it will send a standard instruction (such as Read ID) to the Flash memory. Mode bit Reset for Dual I/O Mode bit Reset for Quad I/O CE MODE3 SCK MODE0 0 1 SIO0 2 3 4 FF 5 6 7 8 9 10 11 12 13 14 15 FF SIO 1 SIO2 SIO3 Note: To reset mode bits dur ing Quad I/O operation, only eight cl ocks are needed. The command code is “FFH”. To reset mode bits durin g Dua l I/O operation, sixteen clocks are needed to shift in command code “FFFFH”. Figure 12: Mode Bit Reset Instruction Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 28/50 ESMT F25L32QA (2S) 64K Byte Block Erase The 64K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23 -A0]. Address bits [AMS -A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 13 for 64K Byte Block Erase sequence. CE MODE3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 SCK MODE0 ADD. D8 SI MSB ADD. ADD. MSB HIGH IMPENANCE SO Figure 13: 64K-byte Block Erase Sequence 32K Byte Block Erase The 32K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23 -A0]. Address bits [AMS -A15] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 14 for 32K Byte Block Erase sequence. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 ADD. 52 SI MSB SO 15 16 23 24 ADD. 31 ADD. MSB HIGH IMPENANCE Figure 14: 64K-byte Block Erase Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 29/50 ESMT F25L32QA (2S) 4K Byte Sector Erase The Sector Erase instruction clears all bits in the selected sector to FFH. A Sector Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23 -A0]. Address bits [AMS -A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 15 for the Sector Erase sequence. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 ADD. 20 SI 15 16 MSB 23 24 ADD. 31 ADD. MSB HIGH IMPENANCE SO Figure 15: 4K-byte Sector Erase Sequence Chip Erase The Chip Erase instruction clears all bits in the device to FFH. A Chip Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip Erase instruction sequence. The Chip Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TCE for the completion of the internal self-timed Chip Erase cycle. See Figure 16 for the Chip Erase sequence. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 60 or C7 SI MSB SO HIGH IMPENANCE Figure 16: Chip Erase Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 30/50 ESMT F25L32QA (2S) Program / Erase Suspend The Program/Erase Suspend instruction allows the system to interrupt a Sector or Block Erase and page or Quad page program operation and then read from, any other sector or block. The Write Status Register instruction and Program instruction and Sector/Block Erase instructions are not allowed during suspend. Program/Erase Suspend is valid only during the Program and Sector or Block Erase operation. If written during the Chip Erase, the Program/Erase Suspend instruction is ignored. A maximum of TSUS is required to suspend the program / erase operation. The BUSY bit in the Software Status Register will clear to “0” after Erase Suspend. A power-off during the suspend period will reset the device and release the suspend status. CE 0 MODE3 SCK MODE0 1 2 3 4 5 6 7 TSUS 75 SI MSB HIGH IMPEDANCE SO Accept Read or Program/Erase Instruction Figure 17: Program/Erase Suspend Instruction Program / Erase Resume The Program/Erase Resume instruction must be written to resume the Page or Quad page program and Sector or Block Erase operation after Program/Erase Suspend. After issued the BUSY bit in the Software Status Register will be set to “1” and the sector or block will complete the program/erase operation. Program/Erase Resume instruction will be ignored unless an Program/Erase Suspend operation is active. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 7A SI MSB Resume Sector or Block Program/Erase Figure 18: Program/Erase Resume Instruction Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 31/50 ESMT F25L32QA (2S) Write Enable (WREN) The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. CE 0 1 2 3 4 5 6 7 MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE SO Figure 19: Write Enable (WREN) Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring or exits from OTP mode to normal mode. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 04 SI MSB SO HIGH IMPENANCE Figure 20: Write Disable (WRDI) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 32/50 ESMT F25L32QA (2S) Write Status Register (WRSR) The Write Status Register instruction writes new values to the BP3, BP2, BP1, BP0, QE and BPL (Status Register-1) bits of the When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1, BP2 and BP3 bits in the status status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the before the WRSR instruction is executed. CE must be driven high after the eighth bit of data that is clocked in. If it is not done, the WRSR instruction will not be issued. See Figure 21 for WREN and WRSR instruction sequences. CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0; BP1, BP2 and BP3 bits at the same time. See Table 4 for a summary description of Executing the Write Status Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lock down the status register, but cannot be reset from “1” to “0”. WP and BPL functions. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Stauts Register - 1 Data In 06 SI 7 6 5 4 3 2 1 0 01 MSB MSB HIGH IMPENANCE SO Figure 21: Write Enable (WREN) and Write Status Register (WRSR) Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the BUSY bit may be checked before sending any new commands to assure that the new commands are properly received by the device. and remain low until the status data is read. The RDSR-1 instruction code is “05H” for Status Register-1. The RDSR-2 instruction code is “35H” for Status Register-2. Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 22 for the RDSR instruction sequence. CE must be driven low before the RDSR instruction is entered CE MODE3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK MODE0 05 or 3 5 SI MSB SO HIGH IMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB Status Register -1 or -2 Data Out Figure 22: Read Status Register (RDSR-1 or RDSR-2) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 33/50 ESMT F25L32QA (2S) Enter OTP Mode (ENSO) The ENSO (B1H) instruction is for entering the additional 512 bytes secured OTP mode. The additional 512 bytes secured OTP sector is independent from main array, which may use to store unique serial number for system identifier. User must unprotect whole array (BP0=BP1=BP2=BP3=0), prior to any Program operation in OTP sector. After entering the secured OTP mode, only the secured OTP sector can be accessed and user can only follow the Read or Program procedure with OTP address range (address bits [A23 –A9] must be “0”). The secured OTP data cannot be updated again once it is lock down or has been programmed. In secured OTP mode, WRSR command will ignore the input data and lock down the secured OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6. Figure 23: Enter OTP Mode (ENSO) Sequence OTP Sector Address Size Address Range 512 bytes 000000H ~ 0001FFH Note: The OTP sector is an independent Sector. Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 34/50 ESMT F25L32QA (2S) Deep Power Down (DP) Once the device is in deep power down status, all instructions will be ignored except the Release from Deep Power Down instruction (RDP) and Read Electronic Signature instruction (RES). The device always power-up in the normal operation with the standby current (ISB1). See Figure 24 for the Deep Power Down instruction. The Deep Power Down instruction is for minimizing power consumption (the standby current is reduced from ISB1 to ISB2.). This instruction is initiated by executing an 8-bit command, B9H, and then CE must be driven high. After CE is driven high, the device will enter to deep power down within the duration of TDP. CE MODE3 0 1 2 3 4 5 6 SCK MODE0 7 T DP B9 SI MSB Standard Current Deep Power Down Current (ISB2) Figure 24: Deep Power Down Instruction Release from Deep Power Down (RDP) and Read Electronic-Signature (RES) The Release form Deep Power Down and Read Electronic-Signature instruction is a multi-purpose instruction. The instruction can be used to release the device from the deep power down status. This instruction is initiated by driving CE low and executing an 8-bit command, ABH, and then drive CE high. See Figure 25 for RDP instruction. Release from the deep power down will take the duration of TRES1 before the device will resume normal operation and other instructions are accepted. CE must remain high during TRES1. The instruction also can be used to read the 8-bit ElectronicSignature of the device on the SO pin. It is initiated by driving Elite Semiconductor Memory Technology Inc. CE low and executing an 8-bit command, ABH, followed by 3 dummy bytes. The Electronic-Signature byte is then output from the device. The Electronic-Signature can be read continuously until CE go high. See Figure 26 for RES sequence. After driving CE high, it must remain high during for the duration of TRES2, and then the device will resume normal operation and other instructions are accepted. The instruction is executed while an Erase, Program or WRSR cycle is in progress is ignored and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status of OTP. Publication Date: Sep. 2012 Revision: 1.3 35/50 ESMT F25L32QA (2S) CE MODE3 0 1 2 3 4 5 6 7 T RES1 SCK MODE0 AB SI MSB HIGH IMPEDANCE SO Standby Current Deep Power Down Current (ISB2) Figure 25: Release from Deep Power Down (RDP) Instruction CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 30 9 31 32 33 34 35 36 37 38 TRES2 SS 3 Dummy Bytes SS AB SI MSB SO HIGH IMPEDANCE SS Electronic-Signature Data Out MSB Deep Power Down Current (ISB2) Standby Current Figure 26: Read Electronic -Signature (RES) Sequence Table 6: Electronic Signature Data Command RES Mode Electronic Signature Data Normal 15H In secured OTP mode & non lock down (OTP_lock =0) 35H In secured OTP mode & lock down (OTP_lock =1) 75H Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 36/50 ESMT F25L32QA (2S) JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as F25L32QA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 41H, identifies the memory type as SPI Flash. Byte3, 16H, identifies the device as F25L32QA. The instruction sequence is shown in Figure 27. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). Figure 27: JEDEC Read-ID Sequence Table 7: JEDEC Read-ID Data Manufacturer’s ID (Byte 1) 8CH Elite Semiconductor Memory Technology Inc. Device ID Memory Type (Byte 2) Memory Capacity (Byte 3) 41H 16H Publication Date: Sep. 2012 Revision: 1.3 37/50 ESMT F25L32QA (2S) Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L32QA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A23 -A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 000000H and the device ID is located in address 000001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on CE . CE MODE3 SCK MODE0 15 16 0 1 2 3 4 5 6 7 8 SI 90 00 39 40 47 4 8 55 56 63 1 00 ADD MSB MSB SO 31 32 23 24 HIGH IMPENANCE 8C 15 8C 15 HIGH IMPENA NCE MSB Note: The Manufacture’s an d Device ID o utput stream i s continu ous until terminated by a low to high transition on CE. 1. 00H will output the Manufacture’s ID first a nd 01H will output Device ID first b efore toggling between the two. . Figure 28: Read ID Sequence Table 8: Product ID Data Address 000000H 000001H Elite Semiconductor Memory Technology Inc. Byte1 Byte2 8CH 15H Manufacturer’s ID Device ID ESMT F25L32QA 15H 8CH Device ID ESMT F25L32QA Manufacturer’s ID Publication Date: Sep. 2012 Revision: 1.3 38/50 ESMT F25L32QA (2S) ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA ( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. ) TABLE 9: AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz See Figures 34 and 35 TABLE 10: OPERATING RANGE Parameter Symbol Value Unit Operating Supply Voltage VDD 2.65 ~ 3.6 V Ambient Operating Temperature TA -40 ~ +85 ℃ TABLE 11: DC OPERATING CHARACTERISTICS Symbol IDDR1 IDDR2 IDDR3 IDDR4 IDDW Parameter Min Standard Dual Quad Standard Read Current Dual @ 50MHz Quad Standard Read Current Dual @ 86MHz Quad Standard Read Current Dual @ 104MHz Quad Program and Write Status Register Current Sector and Block Erase Current Read Current @ 33MHz Limits Max 9 10.5 12 10 12 13.5 15 16.5 18 22 23.5 25 Test Condition Unit mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =0.1 VDD/0.9 VDD, SO=open 15 mA CE =VDD 15 mA CE =VDD Chip Erase Current 20 mA CE =VDD ISB1 Standby Current 30 µA CE =VDD, VIN =VDD or VSS ISB2 Deep Power Down Current 10 µA ILI ILO VIL VIH VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1 1 0.3 x VDD VDD +0.4 0.4 µA µA V V V V CE =VDD, VIN =VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max IDDE -0.5 0.7 x VDD VDD-0.2 Elite Semiconductor Memory Technology Inc. IOL=1.6 mA IOH=-100 µA Publication Date: Sep. 2012 Revision: 1.3 39/50 ESMT F25L32QA (2S) TABLE 12: LATCH UP CHARACTERISTIC Symbol 1 ILTH Parameter Latch Up Minimum Unit Test Method 100 + IDD mA JEDEC Standard 78 Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open) Parameter COUT 1 1 CIN Description Test Condition Maximum VOUT = 0V 8 pF VIN = 0V 6 pF Output Pin Capacitance Input Capacitance Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14: AC OPERATING CHARACTERISTICS Normal 33MHz Symbol Fast 50 MHz Fast 86 MHz Min Min Fast 104 MHz Parameter Unit Min Max Min TSCKH Serial Clock High Time 13 9 6 4 ns TSCKL Serial Clock Low Time 13 9 6 4 ns TCLCH2 Clock Rise Time (Slew Rate) 0.1 0.1 0.1 0.1 V/ns TCHCL2 Clock Fall Time (Slew Rate) 0.1 0.1 0.1 0.1 V/ns CE Active Setup Time 5 5 5 5 ns CE Active Hold Time 5 5 5 5 ns TCHS CE Not Active Setup Time 5 5 5 5 ns 1 TCHH CE Not Active Hold Time 5 5 5 5 ns TCPH CE High Time 10 10 10 10 ns TCHZ CE High to High-Z Output TCLZ SCK Low to Low-Z Output 0 0 0 0 ns TDS Data In Setup Time 2 2 2 2 ns TDH Data In Hold Time 1 1 1 1 ns THLS HOLD Low Setup Time 5 5 5 5 ns THHS HOLD High Setup Time 5 5 5 5 ns THLH HOLD Low Hold Time 5 5 5 5 ns THHH HOLD High Hold Time 5 5 5 5 ns 1 TCEH 1 3 7 86 Max Serial Clock Frequency TCES 50 Max FCLK 1 33 Max 7 104 7 7 MHz ns THZ HOLD Low to High-Z Output 8 8 8 8 ns 3 TLZ HOLD High to Low-Z Output 8 8 8 8 ns Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 40/50 ESMT F25L32QA (2S) TABLE 14: AC OPERATING CHARACTERISTICS - Continued Normal 33MHz Symbol Fast 50 MHz Fast 86 MHz Min Min Fast 104 MHz Parameter Unit Min Max Max TV Output Valid from SCK 12 8 8 8 ns 4 TWHSL Write Protect Setup Time before CE Low 20 20 20 20 ns TSHWL Write Protect Hold Time after CE High 100 100 100 100 ns 3 TDP CE High to Deep Power Down Mode 3 3 3 3 us TRES13 CE High to Standby Mode ( for DP) 3 3 3 3 us CE High to Standby Mode (for RES) 1.8 1.8 1.8 1.8 us CE High to next Instruction after Suspend 20 20 20 20 us 3 TSUS 3 0 Min Output Hold from SCK Change TRES2 0 Max TOH 4 0 Max 0 ns Note: 1. 2. 3. 4. Relative to SCK. TSCKH + TSCKL must be less than or equal to 1/ FCLK. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a Write status Register instruction when Block- Protection-Look (BPL) bit is set at 1. TABLE 15: ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Symbol Typ 2 Max3 Unit Sector Erase Time (4KB) TSE 120 250 ms Block Erase Time (32KB) TBE1 500 1000 ms Block Erase Time (64KB) TBE2 1 2 s Chip Erase Time TCE 10 50 s Write Status Register Time TW 10 15 ms Page Programming Time TPP 1.5 5 ms 100,000 - Cycles 20 - Years Erase/Program Cycles1 Data Retention Notes: 1. 2. 3. Not 100% Tested, Excludes external system level over head. Typical values measured at 25°C, 3V. Maximum values measured at 85°C, 2.65V. Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 41/50 ESMT F25L32QA (2S) Figure 29: Serial Input Timing Diagram Figure 30: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 42/50 ESMT F25L32QA (2S) CE SCK SO SI HOLD Figure 31: HOLD Timing Diagram WP T WHSL TSHWL CE SCK SI HIGH IMPENANCE SO Figure 32: Write Protect setup and hold timing during WRSR when BPL = 1 Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 43/50 ESMT F25L32QA (2S) VDD VDD (max) Program, Erase and Write command is ignored CE must track VDD VDD (min) TVSL Reset State Read command is allowed Device is fully accessible VWI TPUW Time Figure 33: Power-Up Timing Diagram Table 16: Power-Up Timing and VWI Threshold Parameter Unit Symbol Min. VDD(min) to CE low TVSL 10 Time Delay before Write instruction TPUW 1 10 ms VWI 1 2.5 V Write Inhibit Threshold Voltage Max. us Note: These parameters are characterized only. Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 44/50 ESMT F25L32QA (2S) Input timing reference level Output timing reference level 0.8VDD 0.7VDD 0.3VDD 0.2VDD AC Measurement Level 0.5VDD Note : Input pulse rise and fall time are <5ns Figure 34: AC Input/Output Reference Waveforms Figure 35: A Test Load Example Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 45/50 ESMT F25L32QA (2S) PACKING DIMENSIONS 8-LEAD SOIC 200 mil ( official name – 208 mil ) 5 1 4 E1 8 E θ b e A A2 D L A1 L1 SEATING PLANE Dimension in mm Dimension in inch Symbol DETAIL "X" Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A --- --- 2.16 --- --- 0.085 E 7.70 7.90 8.10 0.303 0.311 0.319 A1 0.05 0.15 0.25 0.002 0.006 0.010 E1 5.18 5.28 5.38 0.204 0.208 0.212 A2 1.70 1.80 1.91 0.067 0.071 0.075 L 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0.014 0.016 0.020 e c 0.19 0.20 0.25 0.007 0.008 0.010 L1 1.27 1.37 1.47 0.050 0.054 0.058 D 5.13 5.23 5.33 0.202 0.206 0.210 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 46/50 ESMT F25L32QA (2S) PACKING DIMENSIONS 16-LEAD SOIC ( 300 mil ) 9 GAUGE PLANE 0 0.25 E E1 A 16 L DETAIL "X" 1 8 e b A2 A C D "X" A1 SEATING PLANE Dimension in mm Dimension in inch Symbol Dimension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Min A --- --- 2.65 --- --- 0.104 E 10.30 BSC 0.406 BSC A1 0.1 --- 0.3 0.004 --- 0.012 E1 7.50 BSC 0.295 BSC A2 2.05 --- --- 0.081 --- --- L b 0.31 --- 0.51 0.012 --- 0.020 e c 0.20 --- 0.33 0.008 --- 0.013 θ D 10.10 10.30 10.50 0.400 0.406 0.413 0.40 Norm --- Max 1.27 Min 0.016 1.27 BSC 0° --- Norm --- Max 0.050 0.050 BSC 8° 0° --- 8° Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 47/50 ESMT F25L32QA (2S) PACKING DIMENSIONS 8-CONTACT WSON ( 6x5 mm ) D E A PIN# 1 A1 L DETAIL : "B" "A" E2 b e D2 DETAIL : "A" "B" PIN# 1 Symbol A A1 b D D2 E E2 e L Min 0.70 0.00 0.35 5.90 2.50 4.90 2.10 0.55 Dimension in mm Norm 0.75 0.02 0.40 6.00 2.60 5.00 2.20 1.27 BSC 0.60 Max 0.80 0.05 0.45 6.10 2.70 5.10 2.30 Min 0.028 0.000 0.014 0.232 0.098 0.193 0.083 0.65 0.022 Dimension in inch Norm 0.030 0.001 0.016 0.236 0.102 0.197 0.087 0.050 BSC 0.024 Max 0.031 0.002 0.018 0.240 0.106 0.201 0.091 0.026 Controlling dimension : millimeter Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 48/50 ESMT F25L32QA (2S) Revision History Revision Date 0.1 2011.01.27 Description Original 1. Ordering information : add 2S 2. Remove Byte program time 3. Discriminate between status register -1 and status register -2 4. Modify WSON 6x5mm dimension : D2 2.5(min), 2.60(norm), 2.70(max) and E2 2.10(min), 2.20(norm), 2.30(max) 1. Add 32KB Block into sector address table 2. Delete SOIC (150mil) and PDIP package 3. Correct WRSR, Status Register-2 and block protection table 4. Add RDSR-2 5. Modify the specification of TCE(max) 1. Correct command code of RDSR-2 in device operation instruction table 2. Correct WRSR command 0.2 2011.03.03 0.3 2011.07.04 0.4 2011.09.14 0.5 2011.09.15 Correct Status Register-2 in Software Status Register table 0.6 2011.10.13 Modify minimum voltage from 2.7V to 2.65V 1.0 2012.02.20 Delete “Preliminary” 1.1 2012.04.18 Modify the range of TA 1.2 2012.07.20 Modify 100MHz to 104MHz for speed grade -100 1.3 2012.09.21 Modify Ambient Operating Temperature Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 49/50 ESMT F25L32QA (2S) Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Sep. 2012 Revision: 1.3 50/50