BCM8702 Product Brief

BCM8702
®
SERIAL 10-GIGABIT ETHERNET TRANSCEIVER WITH XAUI INTERFACE
SUMMARY OF BENEFITS
FEATURES
• IEEE 802.3ae compliant
• Support for XENPAK and XGP Standards
• Power supplies: core, LVPECL, CML, and XAUI at 1.8V,
MDIO at 1.2V, and CMOS at 1.8 or 3.3V.
• Low power consumption eliminates external heat sinks, fans
• Xenpak support optimized for Xenpak/XGP layout and thermal
• Fully integrated CMU, CDR, and SerDes
• PMD interface with serial 10.3125 Gbps CML
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for system airflow, and expensive high current power supplies.
• Reduces design cycle and time to market.
• Uses the most effective silicon economy of scale for CMOSbased devices.
PSC 64B/66B scrambler/descrambler
XGXS 8B/10B error detection ENDEC
XAUI link synchronization/deskew
Four-lane, 3.125-Gbps XAUI interface
Loss-of-signal detection
APPLICATIONS
Loopback modes
802.3 clause 45 management interface extended indirect
address access
• Built-In Self-Test (BIST)
• Built-in jitter tests for XAUI and PMD
• EEPROM interface support
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LAN/WAN switches
Switch/router backbones
Hubs and repeaters
Network Interface Cards (NICs)
Test equipment
BCM8702 Application Block Diagram
XAUI
3.125 Gbps
PCS/PMA
MAC
XGXS
XGXS
RS
Media
Access
Controller
Interface
BCM8702
MDC MDIO
Management
Interface
OTX
10.3125 Gbps
ORX
Optical
PMD
EEPROM
OVERVIEW
8B/10B
Encoder
XDOP
XDON
Serializer
8B/10B
Encoder
64B/66B
Synchronizer
Descrambler
Decoder
Gearbox
Serializer
Elastic FIFO
XAOP
XAON
3.125 Gbps
Differential
XAUI
Randomizer
PCDRLK
PLOSB
CDR &
Deserializer
PDIP
PDIN
AC-coupled
10.3125 Gbps
Differential
CML
CMU
AC-coupled
Differential
LVPECL
156.25 MHz
XEXTCLKP
XEXTCLKN
XPDOUT
XPLLLK
Receive Path
Clock
Management
PEXTCLKP
PEXTCLKN
PPDOUT
PPLLLK
PVCOXP
PVCOXN
CDR &
Deserializer
CDR &
Deserializer
XDIP
XDIN
Sync Detect
Lane Sync
8B/10B
Decoder
Sync Detect
Lane Sync
8B/10B
Decoder
Lane
Alignment
FIFO
Lane
Alignment
FIFO
64B/66B
Encoder
Scrambler
Gearbox
XAIP
XAIN
Elastic FIFO
AC-coupled
3.125 Gbps
Differential
XAUI
10.3125 Gbps
Differential
CML
PDOP
CMU &
Serializer
PDON
PCOP
PCON
Transmit Path
RSTB
MDC
MDIO
PHYAD[4:0]
SYSRST
TXON/OFF
TRST
JTCK
TMS
TDI
TDO
Management
Registers
Optics
Control
and
Status
10.3125 GHz
Differential
CML
OPTXENB
OPTXRST
OPTXALARM
OPRXALARM
OPRXLOS
OPTXFLT
OPOUTLVL
OPINLVL
JTAG
EPROM
Interface
Controls
The BCM8702 Ethernet LAN PHY is a fully integrated serialization/
deserialization (10.3125 Gbps) interface device performing the
extension functions for a 10.3125 Gbps Serial Ethernet Reconciliation
Sublayer (RS) interface. The XGXS, PCS, and PMA functions include
8B/10B coding, 64B/66B coding, SerDes, Clock Multiplication Unit
(CMU), and Clock and Data Recovery (CDR).
SDA
SCL
On-chip clock synthesis is performed by the high-frequency, low-jitter,
phase-locked loops for the PMD and XAUI output retimers. Individual
PMD and XAUI clock recovery is performed on the device by
synchronizing the on-chip VCOs directly to their respective incoming
data streams. Elastic buffers allow the XAUI and PMD interfaces to
operate in either a synchronous or asynchronous configuration. An
external 156.25- MHz VCXO is required for synchronous mode
operation or for asynchronous mode with clock cleanup.
The BCM8702 is packaged in a 19 x 19 x 1.86 mm BGA with a 1-mm
ball pitch.
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
8702-PB04-R
04/30/04
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com