IS65WV25616ALL IS65WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES SEPTEMBER 2008 DESCRIPTION The ISSI IS65WV25616ALL/IS65WV25616BLL are high- • • • • • High-speed access time: 55ns, 70ns CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby TTL compatible interface levels Single power supply 1.65V--2.2V Vdd (65WV25616ALL) 2.5V--3.6V Vdd (65WV25616BLL) Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • TEMPERATURE OFFERINGS: speed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS1 is low, and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs.The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS65WV25616BALL/65WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm). Option A1: -40°C to +85°C Option A2: -40°C to +105°C Option A3: -40°C to +125°C • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS1 OE WE UB LB CONTROL CIRCUIT 25616LL_BLK.eps Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 1 IS65WV25616ALL, IS65WV25616BLL 44-Pin mini TSOP (Type II) (Package Code T) PIN CONFIGURATIONS 48- ball mini BGA (6mm x 8mm) (Package Code B) 123456 A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CSI I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CS1 OE WE LB UB NC Vdd GND 2 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 IS65WV25616ALL, IS65WV25616BLL TRUTH TABLE I/O PIN Mode WE CS1 OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X High-Z High-Z X X X X X High-Z High-Z X X X H H High-Z High-Z Output Disabled H L H L X High-Z High-Z H L H X L High-Z High-Z Read H L L L H Dout High-Z H L L H L High-Z Dout H L L L LDoutDout Write L L X L H Din High-Z L L X H L High-Z Din L L X L LDinDin Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 Vdd Current Isb1, Isb2 Isb1, Isb2 Isb1, Isb2 Icc Icc Icc Icc 3 IS65WV25616ALL, IS65WV25616BLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Related to GND Storage Temperature Power Dissipation Value –0.2 to Vdd+0.3 –0.2 to Vdd+0.3 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (Vdd) Range A1 A2 A3 Ambient Temperature -40°C to +85°C –40°C to +105°C –40°C to +125°C IS65WV25616ALL 1.65V - 2.2V 1.65V - 2.2V 1.65V - 2.2V IS65WV25616BLL 2.5V-3.6V 2.5V-3.6V 2.5V-3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Voh Output HIGH Voltage Vol Output LOW Voltage Vih Input HIGH Voltage Vil(1) Input LOW Voltage Ili Input Leakage Ilo Output Leakage Test Conditions Vdd Ioh = -0.1 mA 1.65-2.2V Ioh = -1 mA 2.5-3.6V Iol = 0.1 mA 1.65-2.2V Iol = 2.1 mA 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 2.2 — — 1.4 2.2 –0.2 –0.2 –2 –2 Max. — — 0.2 0.4 Vdd + 0.2 Vdd + 0.3 0.4 0.6 2 2 Unit V V V V V V V V µA µA Notes: 1. Vil (min.) = –1.0V for pulse width less than 10 ns. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 IS65WV25616ALL, IS65WV25616BLL IS65WV25616ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., A1 Supply Current Iout = 0 mA, f = fmax A2, A3 Icc1 Operating Supply Vdd = Max., CS1 = 0.2V A1 Current WE = Vdd-0.2V A2, A3 f=1mhz Isb1 TTL Standby Current Vdd = Max., A1 (TTL Inputs) Vin = Vih or Vil A2, A3 CS1 = Vih , f = 1 MHz OR ULB Control Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Isb2 CMOS Standby Current (CMOS Inputs) Vdd = Max., A1 CS1 ≥ Vdd – 0.2V, A2 Vin ≥ Vdd – 0.2V, or A3 Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Max. 70 25 30 10 15 Unit 0.5 0.6 mA 15 30 50 µA mA mA IS65WV25616BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., A1 Supply Current Iout = 0 mA, f = fmax A2, A3 Icc1 Operating Supply Vdd = Max., CS1 = 0.2V A1 Current WE = Vdd-0.2V, A2, A3 f=1mhz Isb1 TTL Standby Current Vdd = Max., A1 A2, A3 (TTL Inputs) Vin = Vih or Vil CS1 = Vih , f = 1 MHz OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., A1 CS1 ≥ Vdd – 0.2V, A2 Vin ≥ Vdd – 0.2V, or A3 Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 Max. 55 40 — 15 — Max. 70 — 40 — 20 Unit 0.45 — — 0.45 mA 20 — — — 55 90 µA mA mA 5 IS65WV25616ALL, IS65WV25616BLL CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load R1(Ω) R2(Ω) Vref Vtm IS65WV25616ALL (Unit) 0.4V to Vdd-0.2V 5 ns Vref IS65WV25616BLL (Unit) 0.4V to Vdd-0.3V 5ns Vref See Figures 1 and 2 IS65WV25616ALL 1.65V-2.2V 3070 3150 0.9V 1.8V See Figures 1 and 2 IS65WV25616BLL 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope R2 5 pF Including jig and scope 25616l_tst1c.eps 62WV5126ALL tst1a.eps Figure 1 6 R2 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 IS65WV25616ALL, IS65WV25616BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toha tacs1 tdoe thzoe(2) tlzoe(2) thzcs1 tlzcs1 tba thzb tlzb Parameter Read Cycle Time Address Access Time Output Hold Time CS1 Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CS1 to High-Z Output CS1 to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output 55 ns Min. Max. 55 — — 55 10 — — 55 — 25 — 20 5 — 0 20 10 — — 55 0 0 20 — 70 ns Min. Max. 70 — — 70 10 — — 70 — 35 — 25 5 — 0 25 10 — — 70 0 0 25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 7 IS65WV25616ALL, IS65WV25616BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, WE = Vih, UB or LB = Vil) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID 25616R1.eps READ CYCLE NO. 2(1,3) (CS1, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE CS1 tLZOE tACE1/tACE2 tLZCE1 tHZCS1 LB, UB tLZB DOUT tBA tHZB HIGH-Z DATA VALID 51216LL Read 2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = Vil. WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW transition. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 IS65WV25616ALL, IS65WV25616BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 55 ns Symbol Parameter Min. Max. twc Write Cycle Time 55 — tscs1 CS1 to Write End 45 — taw Address Setup Time to Write End 45 — tha Address Hold from Write End 0 — tsa Address Setup Time 0 — tpwb LB, UB Valid to End of Write 45 — tpwe WE Pulse Width 40 — tsd Data Setup to Write End 25 — thd Data Hold from Write End 0 — thzwe(3) WE LOW to High-Z Output — 20 tlzwe(3) WE HIGH to Low-Z Output 5 — 70 ns Min. Max. 70 — 60 — 60 — 0 — 0 — 60 — 50 — 30 — 0 — — 20 5 — Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 9 IS65WV25616ALL, IS65WV25616BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 tAW tPWE WE tPWB LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID 51216LLWRITE 1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1, WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID 51216LL WR2.eps 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 IS65WV25616ALL, IS65WV25616BLL WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 tAW t PWE WE LB, UB tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID 51216LL WR3.eps WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps UB_CSWR4.eps Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 11 IS65WV25616ALL, IS65WV25616BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Vdr Idr tsdr trdr Parameter Vdd for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vdd = 1.2V, CS1 ≥ Vdd – 0.2V A1 A2 A3 See Data Retention Waveform See Data Retention Waveform Min. 1.2 — — — 0 trc Max. 3.6 20 40 60 — — Unit V µA µA µA ns ns DATA RETENTION WAVEFORM (CS1 Controlled) tSDR Data Retention Mode tRDR VDD 1.65V 1.4V VDR CS1 GND CS1 ≥ VDD - 0.2V 51216LT_DR.eps 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 IS65WV25616ALL, IS65WV25616BLL ORDERING INFORMATION: IS65WV25616ALL (1.65V-2.2V) Temperature Range (A1): –40°C to +85°C Speed (ns) 70 Order Part No. IS65WV25616ALL-70TA1 Package 44-pin TSOP-II Temperature Range (A2): –40°C to +105°C Speed (ns) 70 Order Part No. IS65WV25616ALL-70TA2 Package 44-pin TSOP-II Temperature Range (A3): –40°C to +125°C Speed (ns) 70 Order Part No. IS65WV25616ALL-70TA3 Package 44-pin TSOP-II ORDERING INFORMATION: IS65WV25616BLL (2.5V-3.6V) Temperature Range (A1): –40°C to +85°C Speed (ns) 55 Order Part No. IS65WV25616BLL-55TA1 IS65WV25616BLL-55TLA1 IS65WV25616BLL-55CTLA1 IS65WV25616BLL-55BA1 IS65WV25616BLL-55BLA1 Package 44-pin TSOP-II 44-pin TSOP-II, Lead-free 44-pin TSOP-II, Copper Leadframe, Lead-free 48-ball BGA 48-ball BGA, Lead-free Package 44-pin TSOP-II 48-ball BGA 48-ball BGA, Lead-free Package 44-pin TSOP-II 44-pin TSOP-II, Lead-free 48-ball BGA 48-ball BGA, Lead-free Temperature Range (A2): –40°C to +105°C Speed (ns) 70 Order Part No. IS65WV25616BLL-70TA2 IS65WV25616BLL-70BA2 IS65WV25616BLL-70BLA2 Temperature Range (A3): –40°C to +125°C Speed (ns) 70 Order Part No. IS65WV25616BLL-70TA3 IS65WV25616BLL-70TLA3 IS65WV25616BLL-70BA3 IS65WV25616BLL-70BLA3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/16/08 13 PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View Bottom View φ b (48x) 1 2 3 4 5 6 6 A 4 3 2 1 A e B B C C D D 5 D D1 E E F F G G H H e E E1 A2 Notes: 1. Controlling dimensions are in millimeters. A A1 SEATING PLANE mBGA - 6mm x 8mm mBGA - 8mm x 10mm MILLIMETERS INCHES MILLIMETER Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 Sym. Min. Typ. Max. N0. Leads 48 INCHES Min. Typ. Max. A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 7.90 — 8.10 0.311 — 0.319 D 9.90 — 10.10 0.390 — 0.398 D1 E 5.25 BSC 5.90 — 6.10 0.207 BSC 0.232 — 0.240 D1 E 5.25 BSC 7.90 — 0.207 BSC 8.10 0.311 — 0.319 E1 3.75 BSC 0.148 BSC E1 3.75 BSC 0.148 BSC e 0.75 BSC 0.030 BSC e 0.75 BSC 0.030 BSC 0.012 0.014 0.016 b b 0.30 0.35 0.40 0.30 0.35 0.40 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) N N/2+1 E1 1 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. E N/2 D SEATING PLANE A ZD . b e Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° A1 Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° L α Millimeters Min Max C Inches Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03