IS61QDB41M36

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
.
I
April 2009
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Separate read and write ports with concurrent
read and write operations.
• Synchronous pipeline read with late write operation.
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Double data rate (DDR) interface for read and
write input ports.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Fixed 4-bit burst for read and write operations.
• Byte write capability.
• Clock stop support.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Two input clocks (K and K) for address and control registering at rising edges only.
• Two input clocks (C and C) for data output control.
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb IS61QDB41M36 and
IS61QDB42M18 are synchronous, high-performance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic operations of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
•
•
•
•
•
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be registered one cycle after the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from
the first and third bursts are updated from output
registers off the second and fourth rising edges of
the C clock (starting 1.5 cycles later). The data-outs
from the second and fourth bursts are updated with
the third and fifth rising edges of the C clock. The K
and K clocks are used to time the data-outs whenever the C and C clocks are tied high. Two full clock
cycles are required to complete a read operation
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
1
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
x36 FBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/SA
NC/SA*
W
BW2
K
BW1
R
SA
VSS/SA
CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
NC
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Note: The following pins are reserved for higher densities: A3 for 72Mb, 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Pinout (Top View)
A
1
2
3
4
5
6
7
8
9
10
11
CQ
VSS/SA*
SA
W
BW1
K
NC
R
SA
VSS/SA*
CQ
NC
K
BW0
SA
NC
NC
Q8
B
NC
Q9
D9
SA
C
NC
NC
D10
VSS
SA
NC
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Note: The following pins are reserved for higher densities: 10A for 72Mb and 2A for 144Mb.
2
Inte grated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Pin Description
Symbol
Pin Number
Description
K, K
6B, 6A
Input clock.
C, C
6P, 6R
Input clock for output data control.
CQ, CQ
11A, 1A
Output echo clock.
Doff
1H
DLL disable when low.
SA
9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R,
8R, 9R
1M x 36 address inputs.
SA
3A, 9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R, 8R, 9R
2M x 18 address inputs.
D0–D8
D9–D17
D18–D26
D27–D35
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P
1M x 36 data inputs.
Q0–Q8
Q9–Q17
Q18–Q26
Q27–Q35
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P
1M x 36 data outputs.
D0–D8
D9–D17
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
2M x 18 data inputs.
Q0–Q8
Q9–Q17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 2D, 3E, 2F, 3G, 2K, 2L, 3N, 3P
2M x 18 data outputs.
W
4A
Write control, active low.
R
8A
Read control, active low.
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B
1M x 36 byte write control, active low.
BW0, BW1
7B, 5A
2M x 18 byte write control, active low.
VREF
2H, 10H
Input reference level.
VDD
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
Power supply.
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output power supply.
VSS
2A, 10A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
Power supply.
6K, 5L, 6L, 7L, 4M, 8M, 4N, 8N
ZQ
11H
Output driver impedance control.
TMS, TDI, TCK
10R, 11R, 2R
IEEE 1149.1 test inputs (1.8V LVTTL levels).
TDO
1R
IEEE 1149.1 test output (1.8V LVTTL level).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
3
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Block Diagram
D (Data-In)
36 (or 18)
Data
Reg
36 (or 18)
36 (or 18)
BWx
4 (or 2)
1M x 36
(2M x 18)
Memory
Array
72
(or 36)
Output Driver
W
Control
Logic
72
(or 36)
Output Reg
R
Add
Reg
Sense Amps
19 (or 20)
Write/Read Decode
Address
Output Select
Write Driver
19 (or 20)
36 (or 18)
Q (Data-Out)
CQ, CQ
(Echo Clock Out)
K
K
C
Clock
Gen
Select Output Control
C
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. R can be activated every other cycle because two full cycles are
required to complete the burst of four in DDR mode. A second set of clocks, C and C, are used to control the
timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings
identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is
clocked by the subsequent rising edge of the K clock.
A NOP operation (R is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever W is low. The write
address is provided simultaneously. Again, the write always occurs in bursts of four.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K. The third data-in is clocked by the
subsequent rising edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the
K clock.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI
®
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into
the array on the third write cycle. A read cycle to the last two write addresses produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see X18/X36 Write Truth Tables on page 10 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 16. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never
be connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock
mode to minimize power and requires only 1024 cycles to restart.
No clocks can be issued until VDD reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differential clocks
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.
In the following application example, the second pair of C and C clocks is delayed such that the return data
meets the data setup and hold times at the bus master.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
5
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Application Example
2M x 18
SRAM #1
SRAM #4
ZQ
D0–17
Vt
R
SA
Q0–17
R W BW0 BW1 C C K K
R=250Ω
ZQ
D0–17
R=250Ω
Q0–17
R W BW0 BW1 C C K K
SA
Data In 0–71
Data Out 0–71
Vt
Address 0–75
R
R
Vt
W
BW0–7
Memory
Controller
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Ω Vt=VREF
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
.
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
State Diagram
Power-Up
Read NOP
Read
Read
Read
D count = 2
Load New
Read Address
D count = 0
Always
Read
D count = 2
DDR-II Read
D count =
D count + 1
Read
D count = 1
Always
Increment
Read Address
Write
Write NOP
Write
Load New
Write Address
D count = 0
Always
Write
D count = 2
Write
D count = 2
DDR-II Write
D count =
D count + 1
Write
D count = 1
Always
Increment
Write Address
Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst addresses are
A0+1, A0+2, and A0+3
.
to read inactive status with R = high.
2. Read refers to read active status with R = low. Read refers
3. Write refers to write active status with W = low. Write refers to write inactive status with W = high.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle “t”.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
7
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Timing Reference Diagram for Truth Table
Cycle
t
t+1
Read A
t+2
t+3
Write B
K Clock
K Clock
R
W
BWX
Address
A
B
Data-In
DB
DB+1
DB+2
DB+3
Data-Out
QA
QA+1
QA+2
QA+3
C Clock
C Clock
CQ Clock
CQ Clock
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Clock
Controls
Data In
Data Out
Mode
DB
DB+1
DB+2
QA
QA+1
QA+2
QA+3
Previous
State
Previous
State
Previous
State
Previous
State
X
High-Z
High-Z
High-Z
High-Z
X
X
Dout at C
(t + 1.5)
Dout at C
(t + 2)
Dout at C
(t + 2.5)
Dout at C
(t + 3)
Din at K
(t + 2)
Din at K
(t + 2.5)
X
X
X
X
K
R
W
Stop Clock
Stop
X
X
No Operation (NOP)
L→H
H
H
X
X
X
Read B
L →H
L
X
X
X
Write A
L →H
X
L
Din at K
(t + 1)
Din at K
(t + 1.5)
DB+3
Previous Previous Previous Previous
State
State
State
State
Notes:
1. Internal burst counter is always fixed as four-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R is active low
4. A write operation is started when control signal W is active low. Before entering into stop clock, all pending read and write commands must be completed.
5. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are
issued in consecutive K clock rising edges, the second one will be ignored.
6. If both R and W are active low after a NOP operation, the write operation will be ignored.
7. For timing definitions, refer to the AC Characteristics on page 17. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K, K, C, and C.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
9
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
Operation
K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW0
BW1
BW2 BW3
DB
Write Byte 0
L→H
L
H
H
H
D0-8 (t+1)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+1)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+1)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+1)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+1)
Abort Write
L→H
H
H
H
H
Don’t care
DB+1
Write Byte 0
L→H
L
H
H
H
D0-8 (t+1.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+1.5)
Write Byte 2
L→H
H
H
L
H
Write Byte 3
L→H
H
H
H
L
Write All Bytes
L→H
L
L
L
L
D0-35 (t+1.5)
Abort Write
L→H
H
H
H
H
Don’t care
DB+2
DB+3
D18-26
(t+1.5)
D27-35
(t+1.5)
Write Byte 0
L→H
L
H
H
H
D0-8 (t+2)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+2)
Write Byte 2
L→H
H
H
L
H
Write Byte 3
L→H
H
H
H
L
Write All Bytes
L→H
L
L
L
L
D0-35 (t+2)
Abort Write
L→H
H
H
H
H
Don’t care
D18-26
(t+2)
D27-35
(t+2)
Write Byte 0
L→H
L
H
H
H
D0-8 (t+2.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+2.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+2.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+2.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+2.5)
Abort Write
L→H
H
H
H
H
Don’t care
Notes;
1. For all cases, W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications wit respect to switching
clocks K and K.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
Operation
K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW0
BW1
DB
Write Byte 0
L→H
L
H
D0-8 (t+1)
Write Byte 1
L→H
H
L
D9-17 (t+1)
Write All Bytes
L→H
L
L
D0-17 (t+1)
Abort Write
L→H
H
H
Don’t care
DB+1
Write Byte 0
L→H
L
H
D0-8 (t+1.5)
Write Byte 1
L→H
H
L
D9-17 (t+1.5)
Write All Bytes
L→H
L
L
D0-17 (t+1.5)
Abort Write
L→H
H
H
Don’t care
DB+2
Write Byte 0
L→H
L
H
D0-8 (t+2)
Write Byte 1
L→H
H
L
D9-17 (t+2)
Write All Bytes
L→H
L
L
D0-17 (t+2)
Abort Write
L→H
H
H
Don’t care
DB+3
Write Byte 0
L→H
L
H
D0-8 (t+2.5)
Write Byte 1
L→H
H
L
D9-17 (t+2.5)
Write All Bytes
L→H
L
L
D0-17 (t+2.5)
Abort Write
L→H
H
H
Don’t care
Notes;
1. For all cases. W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching
clocks K and K.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
11
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Absolute Maximum Ratings
Item
Symbol
Rating
Units
Power supply voltage
VDD
-0.5 to 2.6
V
Output power supply voltage
VDDQ
-0.5 to 2.6
V
VIN
-0.5 to 2.6
V
VDOUT
-0.5 to 2.6
V
Operating temperature
TA
0 to 70
°C
Junction temperature
TJ
110
°C
Storage temperature
TSTG
-55 to +125
°C
Input voltage
Data out voltage
Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Recommended DC Operating Conditions (TA = 0 to +70° C)
Parameter
Maximum
Units
Notes
1.8 - 5%
1.8 + 5%
V
1
VDDQ
1.4
1.9
V
1
Input high voltage
VIH
VREF +0.1
VDDQ + 0.2
V
1, 2
Input low voltage
VIL
-0.2
VREF - 0.1
V
1, 3
VREF
0.68
0.95
V
1, 5
VIN - CLK
-0.2
VDDQ + 0.2
V
1, 4
Supply voltage
Output driver supply voltage
Input reference voltage
Clocks signal voltage
1.
2.
3.
4.
5.
Symbol
Minimum
VDD
Typical
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
VIH(Max) AC = See 0vershoot and Undershoot Timings.
VIL(Min) AC = See 0vershoot and Undershoot Timings.
VIN-CLK specifies the maximum allowable DC excursions of each clock (K, K, C, and C).
Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
0vershoot and Undershoot Timings
20% Min Cycle Time
VIL(Min) AC
VDDQ+0.6V
Undershoot Timing
VDDQ
GND
VIH(Max) AC
Overshoot Timing
GND-0.6V
20% Min Cycle Time
PBGA Thermal Characteristics
Item
Symbol
Rating
Units
Thermal resistance junction to ambient (airflow = 1m/s)
RΘJA
TBD
° C/W
Thermal resistance junction to case
RΘJC
TBD
° C/W
Thermal resistance junction to pins
RΘJB
TBD
° C/W
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
13
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Capacitance (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter
Symbol
Test Condition
Maximum
Units
Input capacitance
CIN
VIN = 0V
4
pF
Data-in capacitance (D0–D35)
CDIN
VDIN = 0V
4
pF
Data-out capacitance (Q0–Q35)
COUT
VOUT = 0V
4
pF
Clocks Capacitance (K, K, C, C)
CCLK
VCLK = 0V
4
pF
DC Electrical Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
Units
Notes
IDD50
—
500
mA
1
IDD50
—
500
mA
1
Power supply standby current
(R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0)
ISB
—
200
mA
1
Input leakage current, any input (except JTAG)
(VIN = VSS or VDD)
ILI
-2
+2
µA
Output leakage current
(VOUT = VSS or VDDQ, Q in High-Z)
ILO
-5
+5
µA
Output “high” level voltage (IOH = -6mA)
VOH
VDDQ -.4
VDDQ
V
2, 3
Output “low” level voltage (IOL = +6mA)
VOL
VSS
VSS+.4
V
2, 3
ILIJTAG
-100
+100
x36 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
x18 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
JTAG leakage current
(VIN = VSS or VDD)
µA
4
1. IOUT = chip output current.
2. Minimum impedance output driver.
3. JEDEC Standard JESD8-6 Class 1 compatible.
4. For JTAG inputs only.
5. Currents are estimates only and need to be verified.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Typical AC Input Characteristics
Item
Symbol
Minimum
AC input logic high
VIH (ac)
VREF + 0.4
AC input logic low
VIL (ac)
Clock input logic high (K, K, C, C)
VIH-CLK (ac)
Clock input logic low (K, K, C, C)
VIL-CLK (ac)
1.
2.
3.
4.
Maximum
Notes
1, 2, 3, 4
VREF - 0.4
VREF + 0.4
1, 2, 3, 4
1, 2, 3
VREF - 0.4
1, 2, 3
The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
Performance is a function of VIH and VIL levels to clock inputs.
See the AC Input Definition diagram.
See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K
VREF
K
VRAIL
VIH (AC)
VREF
Setup
Time
Hold
Time
VIL (AC)
V-RAIL
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Minimum
Maximum
Units
Notes
Output “high” level voltage
VOH
VDDQ / 2
VDDQ
V
1, 3
Output “low” level voltage
VOL
VSS
VDDQ / 2
V
2, 3
 VDDQ-
1. IOH =  ----------------2 
⁄
 RQ
--------
 5  ± 15% @ VOH = VDDQ / 2 For: 175Ω ≤RQ ≤350Ω.
RQ
 VDDQ- ⁄  -------2. IOL =  ---------------- 5  ± 15% @ VOL = VDDQ / 2 For: 175Ω ≤RQ ≤350Ω.
2 
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
15
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Conditions
Units
VDDQ
1.5, 1.8
V
Input high level
VIH
VREF+0.5
V
Input Low Level
VIL
VREF-0.5
V
VREF
0.75, 0.9
V
Input rise time
TR
0.35
ns
Input fall time
TF
0.35
ns
Output timing reference level
VREF
V
Clocks reference level
VREF
V
Output driver supply voltage
Input reference voltage
Output load conditions
Notes
1, 2
1. See AC Test Loading.
2. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.
AC Test Loading
50 Ω
Q
50 Ω
0.75, 0.9V
5pF
Test
Comparator
0.75, 0.9V
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
AC Characteristics (TA = 0 to + 70oC, VDD = 1.8V -5%, +5%)
Parameter
Symbol
50
(200MHz)
Units
Min
Max
5.0
7.5
ns
0.2
ns
Notes
Clock
Cycle time (K, K, C, C)
tKHKH
Clock phase jitter (K, K, C, C)
tKC-VAR
Clock high pulse (K, K, C, C)
tKHKL
2.0
ns
Clock low pulse (K, K, C, C)
tKLKH
2.0
ns
Clock to clock (KH>KH, CH>CH)
tKHKH
2.2
2.75
ns
Clock to data clock (KH>CH, KH>CH)
tKHCH
0.0
2.3
ns
DLL lock (K, C)
tKC-lock
1024
cycle
K static to DLL reset
tKC-reset
30
cycle
Output Times
C, C high to output valid
tCHQV
C, C high to output hold
tCHQX
C, C high to echo clock valid
tCHCQV
C, C high to echo clock hold
tCHCQX
CQ, CQ High to output valid
tCQHQV
CQ, CQ high to output hold
tCQHQX
0.38
-0.38
0.36
-0.36
0.38
-0.4
0.38
ns
1, 3
ns
1, 3
ns
3
ns
3
ns
1, 3
ns
1, 3
ns
1, 3
ns
1, 3
C High to output high-Z
tCHQZ
C High to output low-Z
tCHQX1
-0.38
Address valid to K, K rising edge
tAVKH
0.4
—
ns
2
Control inputs valid to K rising edge
tIVKH
0.4
—
ns
2
Data-in valid to K, K rising edge
tDVKH
0.4
—
ns
2
K rising edge to address hold
tKHAX
0.4
—
ns
2
K rising edge to control inputs hold
tKHIX
0.4
—
ns
2
K, K rising edge to data-in hold
tKHDX
0.4
—
ns
2
Setup Times
Hold Times
1. See AC Test Loading on page 16.
2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.
17
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Read and Deselect Cycles Timing Diagram
Read
Read
NOP
NOP
tKHKH
tKHKL tKLKH
K
tKHKH
K
tAVKH
tKHAX
SA
A1
A2
tIVKH tKHIX
R
Q1-1
Q (Data-Out)
tKHKH
tKHKL tKLKH
tCHQX
tCHQV
Q1-2
Q1-3
Q1-4
Q2-1
Q2-2
tCHQX
Q2-3
Q2-4
tCHQZ
C
tKHCH
tCHQV
C
tCQHQX
tCHCQX
tCQHQV
tCHCQV
CQ
tCHCQX
CQ
tCHCQV
Don’t Care
Undefined
Note: 1. Q1-1 refers to the output from address A1+0, Q1-2, Q1-3, Q1-4 refers to the output from address A1+1, A1+2, A1+3,
which is the nex internal burst addresses following A1+0.
2. Outputs are disabled one cycle after a NOP.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
18
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Write and NOP Timing Diagram
Write
Write
NOP
NOP
tKLKH
tKHKH
tKHKL
K
tKHKH
K
tAVKH
SA
A1
tIVKH
tKHAX
A2
tKHIX
tKHIX
W
BWX
B1-1
B1-2
B1-3
B1-4
B2-1
D (Data-In)
D1-1
D1-2
D1-3
D1-4
D2-1
B2-2
19
B2-4
tKHDX
tDVKH
NOTE: (B1-1 refers to all BWX byte controls for D1-1)
B2-3
D2-2
D2-3
Don’t Care
D2-4
Undefined
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Read, Write, and NOP Timing Diagram
Read
Write
Read
Read
NOP
Write
NOP
K
K
SA
A1
A2
A3
A4
B2-1
B2-2
B2-3
B2-4
D (Data-In)
D2-1
D2-2
D2-3
D2-4
D (Data-Out)
Q1-1
Q1-2
Q1-3
Q1-4
BWX
B4-1
B4-2
B4-3
D4-1
D4-2
D4-3
Q3-1
Q3-2
Q3-3
R
W
C
C
CQ
CQ
Note: If address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2, data Q3-3=D2-3, and
data Q3-4=D2-4, then write data is forwarded immediately as read results.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
Don’t Care
Undefined
20
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.
Signal List
•
•
•
•
TCK: test clock
TMS: test mode select
TDI: test data-in
TDO: test data-out
JTAG DC Operating Characteristics (TA = 0 to +70° C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
JTAG input high voltage
VIH1
1.3
—
VDD+0.3
V
1
JTAG input low voltage
VIL1
-0.3
—
0.5
V
1
JTAG output high level
VOH1
VDD-0.4
—
VDD
V
1, 2
JTAG output low level
VOL1
VSS
—
0.4
V
1, 3
1.
2.
3.
All JTAG inputs and outputs are LVTTL-compatible.
IOH1 ≥ -|2mA|
IOL1 ≥ +|2mA|.
JTAG AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Conditions
Units
Input pulse high level
VIH1
1.3
V
Input pulse low level
VIL1
0.5
V
Input rise time
TR1
1.0
ns
Input fall time
TF1
1.0
ns
0.9
V
Input and output timing reference level
21
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
JTAG AC Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
Units
TCK cycle time
tTHTH
20
—
ns
TCK high pulse width
tTHTL
7
—
ns
TCk low pulse width
tTLTH
7
—
ns
TMS setup
tMVTH
4
—
ns
TMS hold
tTHMX
4
—
ns
TDI setup
tDVTH
4
—
ns
TDI hold
tTHDX
4
—
ns
TCK low to valid data
tTLOV
—
7
ns
Notes
1
1. See AC Test Loading on page 16.
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tTHMX
TMS
tMVTH
tTHDX
TDI
tDVTH
TDO
tTLOV
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
22
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Scan Register Definition
Register Name
Bit Size x18 or x36
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
ID Register Definition
Field Bit Number and Description
Part
Revision Number
(31:29)
Part Configuration
(28:12)
2M x 18
000
00def0wx0t0q0b0s0
000 101 001 00
1
1M x 36
000
00def0wx0t0q0b0s0
000 101 001 00
1
JEDEC Code
(11:1)
Start Bit
(0)
Part Configuration Definition:
def = 010 for 36Mb
wx = 11 for x36, 10 for x18
t = 1 for DLL, 0 for non-DLL
q = 1 for QUADB4, 0 for DDR-II
b = 1 for burst of 4, 0 for burst of 2
s = 1 for separate I/0, 0 for common I/O
23
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Instruction Set
Code
Instruction
TDO Output
Notes
000
EXTEST
Boundary Scan Register
2,6
001
IDCODE
32-bit Identification Register
010
SAMPLE-Z
Boundary Scan Register
1, 2
011
PRIVATE
Do not use
5
100
SAMPLE
Boundary Scan Register
4
101
PRIVATE
Do not use
5
110
PRIVATE
Do not use
5
111
BYPASS
Bypass Register
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,
Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR
state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations
•
•
•
•
•
7.2.1.b, e
7.7.1.a-f
10.1.1.b, e
10.7.1.a-d
6.1.1.d
JTAG Block Diagram
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
TDO
Instruction Register (3 bits)
Control Signals
TMS
TAP Controller
TCK
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
24
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
TAP Controller State Machine
1
Test Logic Reset
0
0
Run Test Idle
1
1
Select DR
0
0
1
1
Select IR
1
Capture IR
Capture DR
0
0
0
Shift IR
0
Shift DR
1
1
1
1
Exit1 IR
Exit1 DR
0
0
0
0
Pause DR
Pause IR
1
1
Exit2 DR
Exit2 IR
0
0
1
1
Update DR
0
25
1
Update IR
1
0
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
ISSI
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
®
Boundary Scan Exit Order The same length is used for x18 and x36 I/O configuration.
Order
Pin ID
Order
Pin ID
Order
Pin ID
1
6R
37
10D
73
2C
2
6P
37
9E
74
3E
3
6N
39
10C
75
2D
4
7P
40
11D
76
2E
5
7N
41
9C
77
1E
6
7R
42
9D
78
2F
7
8R
43
11B
79
3F
8
8P
44
11C
80
1G
9
9R
45
9B
81
1F
10
11P
46
10B
82
3G
11
10P
47
11A
83
2G
12
10N
48
10A
84
1H
13
9P
49
9A
85
1J
14
10M
50
8B
86
2J
15
11N
51
7C
87
3K
16
9M
52
6C
88
3J
17
9N
53
8A
89
2K
18
11L
54
7A
90
1K
19
11M
55
7B
91
2L
20
9L
56
6B
92
3L
21
10L
57
6A
93
1M
22
11K
58
5B
94
1L
23
10K
59
5A
95
3N
24
9J
60
4A
96
3M
25
9K
61
5C
97
1N
26
10J
62
4B
98
2M
27
11J
63
3A
99
3P
28
11H
64
2A
100
2N
29
10G
65
1A
101
2P
30
9G
66
2B
102
1P
31
11F
67
3B
103
3R
32
11G
68
1C
104
4R
33
9F
69
1B
105
4P
34
10F
70
3D
106
5P
35
11E
71
3C
107
5N
36
10E
72
1D
108
5R
109
Internal
Note:
1) NC pins as defined on FBGA pinouts on page 2 are read as “don’t cares”.
2) State of Internal pin (#109) is loaded via JTAG
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
26
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI
®
11 x 15 FBGA Dimensions
27
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
36 Mb (1M x 36 & 2M x 18) ®
QUAD (Burst of 4) Synchronous SRAMs
ORDERING INFORMATION:
Commercial Range: 0°C to +70°C
Speed
250 MHz
200 MHz
Order Part No.
IS61QDB41M36-250M3
IS61QDB41M36-250M3L
IS61QDB41M36-200M3
IS61QDB42M18-200M3
Organization
1Mx36
1Mx36
1Mx36
2Mx18
Package
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA
Organization
1Mx36
1Mx36
2Mx18
2Mx18
Package
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
Industrial Range: -40°C to +85°C
Speed
250 MHz
250 MHz
Order Part No.
IS61QDB41M36-250M3I
IS61QDB41M36-250M3LI
IS61QDB42M18-250M3I
IS61QDB42M18-250M3LI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. F
04/22/09
28