ADVANCED DATASHEET

IS34MC01GA08/16
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IS34MC01GA08/16
3.3V 1Gb SLC NAND Flash
Memory Specification and
Technical Notes
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ADVANCED DATASHEET
Page 1
IS34MC01GA08
IS34MC01GA16
128M x 8bit / 64M x 16bit NAND Flash Memory
PRODUCT LIST
Part Number
VCC Range
Organization
IS34MC01GA08
IS34MC01GA16
2.7V ~ 3.6V
2.7V ~ 3.6V
X8
X16
PKG Type
48-TSOP I, 63-BGA
48-TSOP I, 63-BGA
FEATURES
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 Voltage Supply:

3.3V Device:
2.7 V ~ 3.6V
 Operating Temperature:
 Industrial: -40 ~ 85℃
/ (64M + 2M) x 16bit
/ (1K + 32) x 16bit
 Automatic Program and Erase

Page Program:
(2K + 64) bytes

Block Erase:
(128K + 4K) bytes
/ (1K + 32) words
/ (64K + 2K) words
 Memory Cell: 1bit/Memory Cell
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 Fast Write Cycle Time

Program time: 200us (Typ.)

Block Erase time: 1.5ms (Typ.)
/ (1K + 32) words
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(2K + 64) bytes
25us (Max.)
25ns (Min.)
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 Page Read Operation

Page Size:

Random Read:

Serial Access:
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 Organization

Memory Cell Array: (128M + 4M) x 8bit

Data Register:
(2K + 64) x 8bit
 Command/Address/Data Multiplexed I/O Port
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 Hardware Data Protection

Program/Erase Lockout During Power Transitions
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 Reliable CMOS Floating Gate Technology
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 Endurance:

100K Program/Erase Cycles (with 1 bit/528 bytes ECC)

Data Retention: 10 Years
 Command Driven Operation
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 Cache Program Operation for High Performance Program
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 Copy-Back Operation
 Unique ID for Copyright Protection
 Package:
48-Pin TSOP I
63-BGA
Pb-Free Packages
Page 2
IS34MC01GA08
IS34MC01GA16
GENERAL DESCRIPTION
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Offered in 128Mx8 / 64Mx16 bits, this device is 1Gbit with spare 32Mbit capacity. The device is offered in 3.3V VCC. Its NAND cell
provides the most cost effective solution for the solid state mass storage market. A program operation can be performed in typical
200us on the 2,112-byte(x8) or 1,056-word(x16) page and an erase operation can be performed in typical 1.5ms on a (128K+4K)
bytes(x8) or (64K+2K) words(x16) block. Data in the data register can be read out at 25ns cycle time per byte(x8) or word(x16). The
I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all
program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the writeintensive systems can take advantage of this device’s extended reliability of 100K program/erase cycles by providing ECC (Error
Correcting Code) with real time mapping-out algorithm.
This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
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PIN ASSIGNMENT (TSOP I)
Page 3
IS34MC01GA08/16
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ADVANCED DATASHEET
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Pin-Out Diagram of x8 63-BGA Device
(Top View, Balls Down)
Pin-Out Diagram of x16 63-BGA Device
(Top View, Balls Down)
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
05/17/2013 Integrated Silicon Solution, Inc. - www.issi.com
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IS34MC01GA08
IS34MC01GA16
PIN DISCRIPTION
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to Hi-Z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15(2)
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to Hi-Z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE#
signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE# with ALE high.
CE#
CHIP ENABLE
The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored,
and the device does not return to standby mode.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE# which also increments the internal column address counter by one.
WE#
WRITE ENABLE
The WE# input controls writes to the I/O port. Commands, address and data are latched on the rising edge
of the WE# pulse.
WP#
WRITE PROTECT
The WP# pin provides inadvertent program/erase protection during power transitions. The internal high
voltage generator is reset when the WP# pin is active low.
R/B#
READY/BUSY OUTPUT
The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase
or random read operation is in process and returns to high state upon completion. It is an open drain output
and does not float to Hi-Z condition when the chip is deselected or when outputs are disabled.
VCC
POWER
VCC is the power supply for device.
VSS
GROUND
N.C.
NO CONNECTION
Lead is not internally connected.
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Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
I/O8 ~ I/O15 are only defined within IS34MC01GA16 and must keep Low while input address or command cycle.
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Pin Name
Page 5
IS34MC01GA08
IS34MC01GA16
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FUNCTION BLOCK DIAGRAM(x8)
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ARRAY ORGANIZATION(x8)
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Address Cycle Map(x8)
Note:
1.
2.
3.
Column Address: Starting Address of the Register.
*L must be set to “Low”
*The device ignores any additional input of address cycles than required.
Page 6
IS34MC01GA08
IS34MC01GA16
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FUNCTION BLOCK DIAGRAM(x16)
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ARRAY ORGANIZATION(x16)
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Address Cycle Map(x16)
Note:
1.
2.
3.
Column Address: Starting Address of the Register.
*L must be set to “Low”
*The device ignores any additional input of address cycles than required.
Page 7
IS34MC01GA08
IS34MC01GA16
Product Introduction
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This device is a 1,056Mbits (1,107,296,256 bits) memory organized as 65,539 rows (pages) by 2,112-byte(x8) or 1,056-word(x16)
columns. Spare 64-byte(x8) or 32-word(x16) columns are located from column address of 2,048 to 2,111(x8) or 1,024 to 1,055(x16).
A 2,112-byte(x8) or 1,056-word(x16) data register and 2,112-byte(x8) or 1,056-word(x16) cache register are serially connected to each
other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers
and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected
to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND
structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page
basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte(x8) or
64K-word(x16) blocks. It indicates that the bit by bit erase operation is prohibited on the device.
This device uses addresses multiplexed scheme. This scheme dramatically reduces pin counts and allows systems upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE# to low while CE# is low. Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable
(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example,
Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and
page program, require two cycles: one cycle for setup and the other cycle for execution. The total physical space requires 28(x8) or
27(x16) addresses, thereby requiring four cycles for addressing: 2 cycle of column address, 2 cycles of row address, in that order. Page
Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however,
only the 2 cycles of row address are used. Device operations are selected by writing specific commands into the command register.
Below table defines the specific commands of this device.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are
being programmed into memory cells in cache program mode. The program performance may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and datainput cycles are removed, system performance for solid-state disk application is significantly increased.
Command Set
2nd Cycle
00h
00h
90h
FFh
80h
80h
85h
60h
85h
05h
70h
30h
35h
10h
15h
10h
D0h
E0h
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Read
Read for Copy Back
Read ID
Reset
Page Program
Cache Program
Copy-Back Program
Block Erase
Random Data Input(1)
Random Data Output(1)
Read Status
1st Cycle
ED
Function
Acceptable Command during Busy
O
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Note:
1.
Random Data Input/ Output can be executed in a page.
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Caution:
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Any undefined command inputs are prohibited except for above command set of above table.
Page 8
IS34MC01GA08
IS34MC01GA16
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VCC
VIN
VI/O
-0.6 to +4.6
V
-0.6 to VCC+0.3(<4.6)
℃
Temperature Under Bias
Industrial
TBIAS
-40 to +125
Industrial
TSTG
-65 to +150
IOS
EE
Short Circuit Current
T
℃
Storage Temperature
5
mA
Note:
2.
Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for industrial periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
TA
(Voltage reference to GND Industrial: TA=-40 to 85℃)
Symbol
Min.
VCC
VSS
2.7
0
Typ.
3.3
0
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Supply Voltage
Supply Voltage
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Max.
Unit
3.6
0
V
V
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Sequential Read
Program
Erase
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
Test Conditions
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
ILO
VIH
VIL
VOH
VOL
IOL(R/B#)
tRC=25ns, CE#=VIL, IOUT=0mA
CE#=VIH, WP#=0V/VCC
CE#=VCC-0.2, WP#=0V/VCC
VIN=0 to VCC(max)
VOUT=0 to VCC(max)
IOH=-400uA
IOL=2.1mA
VOL=0.4V
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Operating
Current
Symbol
IS34MC01GA08/16
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Parameter
Unit
Min.
Typ.
Max.
0.8xVCC
-0.3
2.4
8
15
15
15
10
10
30
30
30
1
50
±10
±10
VCC+0.3
0.2xVCC
0.4
-
mA
mA
uA
V
mA
Note:
VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
Typical value are measured at VCC=3.3V, TA=25℃. And not 100% tested.
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VALID BLOCK
Parameter
Symbol
Min.
Typ.
Max.
Unit
IS34MC01GAXX
NVB
1,004
-
1,024
Blocks
Note:
1.
2.
The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The
number of valid blocks is presented as first shipped. Invalid blocks are defined as blocks that contain one or more bad bits which
cause status failure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached
technical notes for appropriate management of initial invalid blocks.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1
bit/528 bytes ECC.
Page 9
IS34MC01GA08
IS34MC01GA16
AC TEST CONDITION
Industrial: TA=-40 to 85℃, VCC=2.7V~3.6V, unless otherwise noted)
IS34MC01GA08/16
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
0V to VCC
5 ns
VCC /2
1 TTL Gate and CL=50pF
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CAPACITANCE
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(TA=25℃, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min.
Max.
Unit
Input/ Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
-
8
8
pF
pF
Note:
Capacitance is periodically sampled and not 100% tested.
SH
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MODE SELECTION
ALE
CE#
WE#
RE#
WP#
Mode
H
L
H
L
L
L
X
X
X
X
X
L
H
L
H
L
L
X
X
X
X(1)
X
L
L
L
L
L
L
X
X
X
X
H
Rising
Rising
Rising
Rising
Rising
H
X
X
X
X
X
H
H
H
H
H
Falling
H
X
X
X
X
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Read Mode
Write Mode
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Data Input
Data Output
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
Stand-by
ED
Note:
1.
2.
Command Input
Address Input (4 clock)
Command Input
Address Input (4 clock)
TA
CLE
X can be VIL or VIH.
WP# should be biased to CMOS high or CMOS low for stand-by.
Parameter
C
Program / Erase Characteristics
VA
N
Program Time
Dummy Busy Time for Cache Program
Number of Partial Program Cycles in the
Same Page
Block Erase Time
Symbol
Min.
Typ.
Max.
Unit
tPROG(1)
tCBSY(2)
NOP
-
200
3
-
700
700
4
us
us
cycle
tBERS
-
1.5
10
ms
Note:
Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V VCC and
25℃ temperature.
Max. time of tCBSY depends on timing between internal program completion and data in.
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Page 10
IS34MC01GA08
IS34MC01GA16
AC Timing Characteristics for Command / Address / Data Input
Symbol
Min.
Max.
Unit
CLE Setup Time
CLE Hold Time
CE# Setup Time
CE# Hold Time
WE# Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE# High Hold Time
ALE to Data Loading Time
tCLS(1)
tCLH
tCS
tCH
tWP
tALS(1)
tALH
tDS(1)
tDH
tWC
tWH
tADL(2)
12
5
20
5
12
12
5
12
5
25
10
100
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The transition of the corresponding control pins must occur only once while WE# is held low.
tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
AC Characteristics for Operation
tR
tAR
tCLR
tRR
tRP
tWB
tRC
tREA
tCEA
tRHZ
tCHZ
tCSD
tRHOH
tRLOH
tCOH
tREH
tIR
tRHW
tWHR
tRST
ED
C
N
VA
Min.
Max.
Unit
25
100
20
25
100
30
5(1)
10(1)
500(1)
5(1)
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
us
TA
Symbol
Data Transfer from Cell to Register
ALE to RE# Delay
CLE to RE# Delay
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
Read Cycle Time
RE# Access Time
CE# Access Time
RE# High to Output Hi-Z
CE# High to Output Hi-Z
CE# High to ALE or CLE Don’t Care
RE# High to Output Hold
RE# Low to Output Hold
CE# High to Output Hold
RE# High Hold Time
Output Hi-Z to RE# Low
RE# High to WE# Low
WE# High to RE# Low
Device Resetting
Read
Time during ...
Program
Erase
Ready
10
10
20
12
25
0
15
5
15
10
0
100
60
-
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Parameter
SH
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2.
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Note :
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Parameter
Note:
If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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Page 11
IS34MC01GA08
IS34MC01GA16
NAND Flash Technical Notes
Initial Invalid Block(s)
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Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by PFC.
Information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1 bit/528
bytes ECC.
Identifying Initial Invalid Block(s)
N
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TA
SH
All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 1st byte(x8) or 1st word(x16) in the spare area. PFC makes sure that either the 1st or 2nd
page of every initial invalid block has non-FFh data at the 1st byte(x8) or 1st word(x16) column address in the spare area. Since the
initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased.
Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the
initial invalid block table via the following suggested flow chart. Any intentional erasure of the initial invalid block information is
prohibited.
VA
Error in write or read operation
A
D
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the
block failure rate. The following possible failure modes should be considered to implement a highly reliable system. In the case of
status read failure after erase or program, block replacement should be done. Because program status fail during a page program does
not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an
erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must
be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be
reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed
blocks.
Failure
Write
Read
Detection and Countermeasure sequence
Erase Failure
Program Failure
Single Bit Failure
Status Read after Erase  Block Replacement
Status Read after Program  Block Replacement
Verify ECC  ECC Correction
ECC:
1.
2.
Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bits detection
Page 12
IS34MC01GA08
IS34MC01GA16
Program Flow Chart
Erase Flow Chart
Start
CMD 80h
T
Write Address
EE
Write Data
SH
CMD 10h
Read Status Register
If program operation results in an error,
map out the block including the page in
error and copy the target data to
another block
No
TA
I/O6 = 1 ?
or R/B# = 1 ?
No
I/O0 = 0 ?
Program Error
Yes
Read Flow Chart
A
D
VA
N
C
ED
Program Completed
D
A
Yes
Page 13
IS34MC01GA08
IS34MC01GA16
Block Replacement
Block A
1st
~
(n-1) th
An error occurs.
page
1
Block B
2
An error occurs.
* Step 1
When an error happens in the nth page of the Block 'A' during erase or program
operation.
* Step 2
Copy the data in the 1st ~ (n-1)th page to the same location of another free
block. (Block 'B')
* Step 3
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth
page of the Block 'B'
* Step 4
Do not erase or program to Block 'A' by creating an 'invalid block' table or
other appropriate scheme.
TA
n th
SH
1st
~
(n-1) th
Buffer memory of the
controller
EE
T
n th
ED
D
A
page
Addressing for program operation
A
D
VA
N
C
Within a block, the pages must be programmed consecutively from the LSB(Least Significant Bit) page of the block to MSB(Most
Significant Bit) pages of the block. Random page address programming is prohibited.
Page 14
IS34MC01GA08
IS34MC01GA16
System Interface Using CE# don’t-care
A
D
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D
A
TA
SH
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For an easier system interface, CE# may be inactive during the data-loading or sequential data-reading as shown below. The internal
2,112 bytes(x8) or 1,056 words(x16) page registers are utilized as separate buffers for this operation and the system design gets more
flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE# during the
data-loading and reading would provide significant savings in power consumption. Below are the figures of Program Operation and
Read Operation with CE# don’t-care respectively.
Page 15
IS34MC01GA08
IS34MC01GA16
Address Information
I/O
DATA
ADDRESS
I/Ox
Data In/Out
Col. Add1
Col. Add2
Row Add1
Row Add2
I/O0~7
I/O0~15
~ 2112 bytes
~ 1056 words
A0 ~ A7
A0 ~ A7
A8 ~ A11
A8 ~ A10
A12 ~ A19
A11 ~ A18
A20 ~ A27
A19 ~ A26
Parameter
T
IS34MC01GA08
IS34MC01GA16
D
A
TA
SH
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Command Latch Cycle
A
D
VA
N
C
ED
Address Latch Cycle
Page 16
IS34MC01GA08
IS34MC01GA16
Note:
N
Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tRLOH is valid when frequency is higher than 33MHz.
tRHOH starts to be valid when frequency is lower than 33MHz.
A
D
VA
1.
2.
3.
4.
C
ED
D
A
Serial access Cycle after Read (CLE=L,ALE=L,WE#=H)
TA
SH
EE
T
Input Data Latch Cycle
Page 17
IS34MC01GA08
IS34MC01GA16
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D
VA
N
C
ED
D
A
TA
SH
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Status Read Cycle
Page 18
IS34MC01GA08
IS34MC01GA16
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READ Operation
1
A
D
VA
N
C
ED
Random Data Output In a Page
D
A
TA
SH
READ Operation (Intercepted by CE#)
1
Page 19
IS34MC01GA08
IS34MC01GA16
EE
T
Page Program Operation
Notes:
1.
tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
1
N
C
ED
D
A
TA
SH
Page Program Operation with Random Data Input
VA
1
Notes:
tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
A
D
1.
Page 20
IS34MC01GA08
IS34MC01GA16
EE
T
Copy-Back Program Operation with Random Data Input
TA
SH
1
D
A
1
Notes:
1.
tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
A
D
VA
N
C
ED
Cache Program Operation (available only within a block)
Page 21
IS34MC01GA08
IS34MC01GA16
SH
EE
T
Block Erase Operation (Erase One Block)
92h
92h
F1h
C1h
4th
Cycle
5th
Cycle
95h
D5h
40h
40h
80h
80h
Note
C
x8
x16
ED
ID Definition Table
ID Access command = 90h
Option
Maker Device 3rd
Code
Code
Cycle
D
A
TA
Read ID Operation
Description
N
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc.
Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum
Plane Number, Plane Size
VA
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
3rd ID Data
Description
A
D
Internal Chip Number
Cell Type
Number of
Simultaneously
Programmed Page
Interleave Program
1
2
4
8
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
1
2
4
8
Not Support
I/O7
I/O6
I/O5
I/O4
I/O3
0
0
1
1
0
0
1
1
I/O2
I/O1
I/O0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Page 22
IS34MC01GA08
IS34MC01GA16
Between multiple chips
Cache Program
Support
Not Support
Support
0
1
1
Description
I/O7
4th ID Data
Redundant Area Size
(byte/512byte)
Organization
Serial Access Minimum
Description
I/O7
I/O5
0
1
I/O1
I/O0
0
0
1
1
0
1
0
1
0
0
1
1
TA
I/O6
I/O5
I/O4
D
A
1
2
4
8
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
I/O3
I/O2
0
0
1
1
0
1
0
1
I/O1
I/O0
0
0
0
1
0
1
0
1
0
1
A
D
VA
N
C
Reserved
I/O2
0
1
ED
Plane Size
(w/o redundant Area)
I/O3
0
1
0
1
0
0
1
1
5th ID Data
Plane Number
I/O4
T
0
1
0
1
I/O6
EE
Block Size
(w/o redundant area)
1KB
2KB
4KB
8KB
64KB
128KB
256KB
512KB
8
16
x8
x16
50ns/30ns
25ns
Reserved
Reserved
SH
Page Size
(w/o redundant area)
Page 23
IS34MC01GA08
IS34MC01GA16
DEVICE OPERATION
Page Read
Page read is initiated by writing 00h-30h to the command register along with four address cycles. After initial power up, 00h command
is latched. Therefore only four address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes(x8) or
1,056 words(x16) of data within the selected page are transferred to the data registers in less than tR. The system controller can detect
the completion of this data transfer (tR) by analyzing the output of R/B# pin. Once the data in a page is loaded into the data registers,
they may be read out in 25ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the
device output the data starting from the selected column address up to the last column address.
EE
T
The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The
column address of next data, which is going to be out, may be changed to the address which follows random data output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
Read Operation
SH
CE#
CLE
TA
ALE
WE#
tR
R/B#
I/Ox
D
A
RE#
00h
Address (4cycles)
30h
Col. Add. 1,2 & Row Add. 1,2
Data Output( Serial Access)
ED
(00h Command)
Spare Field
A
D
VA
N
C
Data Field
Page 24
IS34MC01GA08
IS34MC01GA16
A
D
VA
N
C
ED
D
A
TA
SH
EE
T
Random Data Output In a Page
Page 25
IS34MC01GA08
IS34MC01GA16
Page Program
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive
bytes up to 2,112(x8) or words up to 1,056(x16), in a single page program cycle. The number of consecutive partial page programming
operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing
should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112
bytes(x8) or 1,056 words(x16) of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
EE
T
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data
input command (85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
SH
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial
data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered, with RE# and CE# low, to read the status register. The system controller can detect the
completion of a program cycle by monitoring the R/B output, or the Status bit (I/O6) of the Status Register. Only the Read Status
command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit
(I/O0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The
command register remains in Read Status command mode until another valid command is written to the command register.
A
D
VA
N
C
Random Data Input In a page
ED
D
A
TA
Program & Read Status Operation
Page 26
IS34MC01GA08
IS34MC01GA16
Cache Program
Cache Program is an extension of Page Program, which is executed with 2,112 byte(x8) or 1,056 words(x16) data registers, and is
available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data
register are programmed into memory cell.
SH
EE
T
After writing the first set of data up to 2,112 bytes(x8) or 1,056 words(x16) into the selected cache registers, Cache Program command
(15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer
data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers
ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command
(70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail status of only
the previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5)
for internal Ready/Busy may be polled to identity the completion of internal programming. If the system monitors the progress of
programming only with R/B#, the last page of the target programming sequence must be programmed with actual Page Program
command (10h).
Note:
A
D
2.
Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after
completion of the previous cycle, which can be expressed as the following formula.
tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command cycle time + Last page data
loading time)
VA
1.
N
C
ED
D
A
TA
Cache Program (available only within a block)
Page 27
IS34MC01GA08
IS34MC01GA16
Copy-Back Program
During coy-back program, data modification is possible using random data input command (85h).
TA
D
A
Note:
1.
2.
SH
Page Copy-Back Program Operation
EE
T
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data store in one page. The benefit is
especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free
block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page
address. A read operation with “35h” command and the address of the source page moves the whole 2,112-byte(x8) or 1,056-word(x16)
data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the
data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h)
with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the
program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can
detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. When the
Copy-Back Program is completed, the Write Status Bit (I/O0) may be checked. The command register remains in Read Status
command mode until another valid command is written to the command register.
This operation is allowed only within the same memory plane.
It’s prohibited to operate Copy-Back program from an odd address page (source page) to an even address (target page) or from an
even address page (source page) to an odd address page (target page). Therefore, the Copy-Back program is permitted just
between odd address pages or even address pages.
A
D
VA
N
C
ED
Page Copy-Back Program Operation with Random Data Input
Page 28
IS34MC01GA08
IS34MC01GA16
Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup
command (60h). Only address A18 to A27(x8) or A17 to A26(x16) is valid while A12 to A17(x8) or A11 to A16(x16) is ignored. The Erase
Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
T
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit (I/O0) may be checked.
A
D
VA
N
C
ED
D
A
TA
SH
EE
Block Erase Operation
Page 29
IS34MC01GA08
IS34MC01GA16
Read Status
Pass/Fail
Not Use
Not Use
Not Use
Not Use
Ready/Busy
I/O6
I/O7
Ready/Busy
Write Protect
Ready/Busy
Write Protect
Pass/Fail(N)
Pass/Fail(N-1)
Not Use
Not Use
Not Use
True
Ready/Busy
Ready/Busy
Write Protect
Note:
Definition
Not Use
Not Use
Not Use
Not Use
Not Use
Ready/Busy
Pass:”0” Fail:”1”
Pass:”0” Fail:”1”
Don’t cared
Don’t cared
Don’t cared
Busy:”0” Ready:”1”
Ready/Busy
Write Protect
Busy:”0” Ready:”1”
Protected:”0” Not Protected:”1”
True Ready/Busy represents internal program operation status which is being executed in cache program mode.
I/Os defined ’Not Use’ are recommended to be masked out when Read Status is being executed.
A
D
VA
N
C
ED
D
A
1.
2.
Read
EE
Pass/Fail
Not Use
Not Use
Not Use
Not Use
Ready/Busy
TA
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
SH
Status Register Definition for 70h Command
I/O
Page
Block
Cache
T
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the
program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the
content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last. This two line control allows the
system to poll the progress of each device in multiple memory connections even when R/B# pins are common-wired. RE# or CE# does
not need to be toggled for updated status. Refer to below table for specific Status Register definitions. The command register remains
in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the
read command (00h) should be given before starting read cycles.
Page 30
IS34MC01GA08
IS34MC01GA16
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacturer code (92h), and the device code and 3rd, 4th and 5th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it.
x8
x16
92h
92h
F1h
C1h
80h
80h
4th
Cycle
5th
Cycle
95h
D5h
40h
40h
Description
D
A
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc.
Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum
Plane Number, Plane Size
A
D
VA
N
C
ED
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Note
TA
ID Definition Table
ID Access command = 90h
Option
Maker Device 3rd
Code
Code
Cycle
SH
EE
T
Read ID Operation
Page 31
IS34MC01GA08
IS34MC01GA16
RESET
Device Status
After Reset
00h Command is latched
Waiting for next command
SH
After Power-up
A
D
VA
N
C
ED
D
A
TA
Operation mode
EE
T
The device offers a reset feature, executed by writing FFh to the command register. When the device is in busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset command will be accepted by the
command register. The R/B# pin changes to low for tRST after the Reset command is written. Refer to Figure below.
Page 32
IS34MC01GA08
IS34MC01GA16
READY/BUSY#
TA
SH
EE
T
The device has an R/B# output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B# pin is normally high but transitions to low after program or erase command is written to the command
register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied.
N
C
ED
D
A
RP vs tRHOH vs CL
VA
RP value guidance
A
D
where IL is the sum of the input currents of all devices tied to the R/B# pin.
RP (max) is determined by maximum permissible limit of tr
Page 33
IS34MC01GA08
IS34MC01GA16
Data Protection & Power-up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever VCC is below about 2V. WP# pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down. A recovery time of minimum 100us is required before internal circuit gets ready for any command
sequences as below. The two step command sequence for program/erase provides additional software protection.
TA
SH
EE
T
AC Waveforms for Power Transition
Note:
During the initialization, the device consumes a maximum current of ICC1.
D
A
1.
WP# AC Timing guide
Enable WP# during erase and program busy is prohibited. The erase and program operations are enabled and disable as follows.
VA
N
C
ED
Program enable mode:
A
D
Program disable mode:
Page 34
IS34MC01GA08
IS34MC01GA16
SH
EE
T
Erase enable mode:
A
D
VA
N
C
ED
D
A
TA
Erase disable mode:
Page 35
A
TA
SH
EE
T
48-TSOP1 dimensions
D
TSOP1 48-Lead Package Dimensions
A
D
VA
N
C
ED
63-BGA (11x9 mm) dimensions
BGA 63-Ball Package Dimensions
Page 36
T
EE
SH
TA
A
D
VA
N
C
ED
D
A
BGA 63-Ball Package Dimensions
Page 37
T
EE
SH
TA
D
A
Vcc Range
Package
IS34MC01GA08-TSLI
2.7V-3.6V
x8
48-TSOP1
2.7V-3.6V
x8
63-BGA (9x11mm) - Call factory
2.7V-3.6V
x16
48-TSOP1
x16
63-BGA (9x11mm) - Call factory
IS34MC01GA08-BSLI
C
IS34MC01GA16-TSLI
ED
Part Number
2.7V-3.6V
A
D
VA
N
IS34MC01GA16-BSLI
Organization
Page 38