IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation – 30 mW (typical) operating – 6 µW (typical) CMOS standby TTL compatible interface levels Single power supply –1.65V-2.2V VDD (IS62/65WV5128EALL) – 2.2V-3.6V VDD (IS62/65WV5128EBLL) – 3.3V +/-5% VDD (IS62/65WV5128ECLL) Three state outputs Industrial and Automotive temperature support Lead-free available PRELIMINARY AUGUST 2015 DESCRIPTION The ISSI IS62/65WV5128EALL/BLL/CLL are highspeed, 4M bit static RAMs organized as 512K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS# is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. The IS62/65WV5128EALL/EBLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I/II), sTSOP (TYPE I),SOP and 36-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM DECODER A 0 – A18 512 K x 8 MEMORY ARRAY VDD GND I/ O DATA CIRCUIT I/O 0 – I/O7 CS # OE# WE# COLUMN /IO CONTROL CIRCUIT Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 1 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL PIN CONFIGURATIONS 36-Pin mini BGA (6mm x 8mm) 1 A B C D D A0 I/O4 2 A1 A2 I/O5 3 NC WE# NC 32-Pin TSOP (Type I) 32-Pin STSOP (Type I) 4 A3 A4 5 A6 A7 A5 GND I/O6 G I/O7 H A9 A8 A10 A8 3 A13 4 29 I/O7 CS# 28 I/O6 I/O0 27 I/O5 A15 7 26 I/O4 I/O1 VDD A17 8 9 25 24 I/O3 GND A16 10 23 I/O2 A14 11 22 I/O1 A12 12 21 A7 13 20 I/O0 A0 A6 A5 14 19 14 A4 16 18 17 OE# CS# A16 A15 I/O3 A10 A11 A12 A13 A14 A1 A2 A3 I/O2 PIN DESCRIPTIONS Chip Enable Input Output Enable Input Write Enable Input No Connection Power Ground OE# 31 30 5 A17 CS# OE# WE# NC VDD GND 32 2 6 A18 Address Inputs Data Inputs/Outputs 1 A9 A18 GND A0-A18 I/O0-I/O7 A11 WE# VDD VDD F 6 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 32-Pin SOP 32-Pin TSOP (Type II) A17 1 32 VDD A16 2 3 31 30 A15 A14 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 A3 8 9 25 24 A11 OE# A2 10 23 A10 A1 11 22 CS# A0 12 21 I/O0 13 20 I/O7 I/O6 I/O1 14 19 I/O2 14 GND 16 18 17 A18 I/O5 I/O4 I/O3 2 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL FUNCTION DESCRIPTION SRAM is one of random access memories. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-7) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input LOW. The input and output pins (I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW. READ MODE Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode Not Selected Output Disabled Write Read CS# WE# OE# I/O0-I/O7 VDD Current H L L L X H H L X H L X High-Z High-Z DIN DOUT ISB2 ICC,ICC1 ICC,ICC1 ICC,ICC1 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 3 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE (1) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vt er m Terminal Voltage with Respect to GND Value –0.5 to VDD + 0.5 Unit V VDD V DD Related to GND –0.3 to 4.0 V tStg Storage Temperature –65 to +150 PT Power Dissipation 1.0 C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (1) OPERATING RANGE Range Ambient Temperature PART NUMBER SPEED (MAX) VDD(MIN) VDD(TYP) VDD(MAX) 55 ns 1.65V 1.8V 2.2V 55 ns 1.65V 1.8V 2.2V Commercial 0C to +70C Industrial -40C to +85C Automotive -40C to +125C 55 ns 1.65V 1.8V 2.2V Commercial ~EALL 0C to +70C 45ns 2.2V 3.0V 3.6V Industrial -40C to +85C 45ns 2.2V 3.0V 3.6V Automotive -40C to +125C 55ns 2.2V 3.0V 3.6V Commercial 0C to +70C 35ns 3.135V 3.3V 3.465V Industrial -40C to +85C 35ns 3.135V 3.3V 3.465V 45ns 3.135V 3.3V 3.465V Automotive Note: 1. ~EBLL ~ECLL -40C to +125C Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. PIN CAPACITANCE Parameter (1) Symbol Input capacitance DQ capacitance (IO0–IO7) Test Condition CIN CI/O TA = 25°C, f = 1 MHz, VDD = VDD(typ) Max Units 6 8 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. (1) THERMAL CHARACTERISTICS Parameter Thermal resistance from junction to ambient (airflow = 1m/s) Thermal resistance from junction to pins Thermal resistance from junction to case Symbol RθJA RθJB RθJC Rating TBD TBD TBD Units °C/W °C/W °C/W Note: 1. These parameters are guaranteed by design and tested by a sample basis only. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 4 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Unit Unit (1.65V~2.2V) (2.2V~3.6V) Input Pulse Level 0.4V to VDD -0.3V 0.4V to VDD -0.3V Input Rise and Fall Time 1V/ns 1V/ns Output Timing Reference Level 0.9V ½ VDD R1 13500 1005 R2 10800 820 VTM Output Load Conditions 1.8V Unit (3.3V +/-5%) 0.4V to VDD -0.3V 1V/ns ½ VDD + 0.05V 1213 1378 3.0V Refer to Figure 1 and 2 3.3V OUTPUT LOAD CONDITIONS FIGURES FIGURE 1 FIGURE 2 R1 R1 VTM VTM OUTPUT OUTPUT 30pF, Including jig and scope R2 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 5pF, Including jig and scope R2 5 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL DC ELECTRICAL CHARACTERISTICS IS62(5)WV5128EALL DC ELECTRICAL CHARACTERISTICS- I (OVER THE OPERATING RANGE) VDD = 1.65V ~ 2.2V Symbol VOH VOL (1) VIH (1) VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA Max. — 0.2 VDD + 0.2 0.4 1 1 Unit V V V V µA µA IS62(5)WV5128EBLL DC ELECTRICAL CHARACTERISTICS- I (OVER THE OPERATING RANGE) VDD = 2.2V ~ 3.6V Symbol Parameter Test Conditions Min. Max. VOH Output HIGH Voltage 2.2 ≤ V DD < 2.7, I OH = -0.1 mA 2.0 — 2.7 ≤ V DD ≤ 3.6, I OH = -1.0 mA 2.4 — VOL Output LOW Voltage 2.2 ≤ V DD < 2.7, IOL = 0.1 mA — 0.4 2.7 ≤ V DD ≤ 3.6, IOL = 2.1 mA — 0.4 (1) VIH Input HIGH Voltage 2.2 ≤ V DD < 2.7 1.8 VDD + 0.3 2.7 ≤ V DD ≤ 3.6 2.0 VDD + 0.3 (1) VIL Input LOW Voltage 2.2 ≤ V DD < 2.7 –0.3 0.6 2.7 ≤ V DD ≤ 3.6 –0.3 0.8 ILI Input Leakage GND < VIN < VDD –1 1 ILO Output Leakage GND < VIN < VDD, Output Disabled –1 1 Unit V V V V V V V V µA µA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. IS62(5)WV5128ECLL DC ELECTRICAL VDD = 3.3V +/-5% Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage (1) VIH Input HIGH Voltage (1) VIL Input LOW Voltage ILI Input Leakage ILO Output Leakage CHARACTERISTICS - I (OVER THE OPERATING RANGE) Test Conditions I OH = -1.0 mA IOL = 2.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 2.4 — 2.0 –0.3 –1 –1 Max. — 0.4 VDD + 0.3 0.8 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. 2. VDD=3.3V +/-5% is for high speed of 35ns device (ECLL). Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 6 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL IS62(5)WV5128EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB2 Notes: 1. Parameter Test Conditions VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) VDD = Max , CS# = VIL, IOUT = 0 mA, f = fMAX Grade Com. Ind./Auto A1 Auto. A3 Com. Ind./Auto A1 Auto. A3 Com. Ind./Auto A1 Auto. A3 (1) typ. VDD = Max , CS# = VIL, IOUT = 0 mA, f = 0 VDD = Max, CS# ≥ VDD - 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V, f = 0 -55 Max. 20 22 22 5 5 5 6 8 20 3.5 Unit mA mA µA Typical values are measured at VDD = 1.8V, TA = 25C , and not 100% tested. IS62(5)WV5128EBLL/ECLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol ICC ICC1 ISB2 Parameter Test Conditions VDD Dynamic Operating Supply Current VDD Static Operating Supply Current CMOS Standby Current (CMOS Inputs) VDD = Max , CS# = VIL, IOUT = 0 mA, f = fMAX VDD = Max , CS# = VIL, IOUT = 0 mA, f = 0 VDD = Max, CS# ≥ VDD - 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V, f = 0 Grade Com. Ind./Auto A1 Auto. A3 Com. Ind./Auto A1 Auto. A3 Com. -35 Max. 22 25 5 5 5 6 -45 Max. 20 22 22 5 5 5 6 -55 Max. 20 22 22 5 5 5 6 Ind./Auto A1 8 8 8 Auto. A3 - 20 20 (2) typ. Notes: 1. 2. Unit mA mA µA 3.5 35 ns speed bin is for ECLL (VDD=3.3V +/-5%) only. Typical values are measured at VDD = 3.0V, TA = 25C , and not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 7 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL AC CHARACTERISTICS (6) (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS (7) 35ns Min Max 45ns Min Max 55ns Min Max Parameter Symbol Read Cycle Time Address Access Time Output Hold Time tRC tAA tOHA 35 8 35 - 45 10 45 - 55 10 CS# Access Time OE# Access Time OE# to High-Z Output OE# to Low-Z Output CS# to High-Z Output CS# to Low-Z Output tACS tDOE tHZOE tLZOE tHZCS tLZCS 4 10 35 18 12 12 - 5 10 45 20 15 15 - 5 10 unit notes 55 - ns ns ns 1,5 1 1 55 25 20 20 - ns ns ns ns ns ns 1 1 2 2 2 2 unit notes WRITE CYCLE AC CHARACTERISTICS (7) Parameter Symbol Write Cycle Time CS# to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE# Pulse Width Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output 35ns 45ns 55ns Min Max Min Max Min Min tWC tSCS tAW tHA tSA 35 30 30 0 0 - 45 35 35 0 0 - 55 40 40 0 0 - ns ns ns ns ns 1,3,5 1,3 1,3 1,3 1,3 tPWE tSD tHD tHZWE tLZWE 30 18 0 4 12 - 35 20 0 5 15 - 40 25 0 5 20 - ns ns ns ns ns 1,3,4 1,3 1,3 2,3 2,3 Notes: 1. Tested with the load in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are measured when the output enters a high impedance state. Not 100% tested. 3. The internal write time is defined by the overlap of CS# = LOW, and WE# = LOW. All four conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tPWE > tHZWE + tSD when OE# is LOW. 5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby mode is acceptable. 6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS. 7. 35 ns speed bin is at VDD=3.3V +/-5% . Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 8 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL TIMING DIAGRAM READ CYCLE NO. 1 (1) (ADDRESS CONTROLLED, CS# = OE# = LOW, WE# = HIGH)) tRC Address tAA tOHA tOHA PREVIOUS DATA VALID DQ 0-15 LOW-Z DATA VALID Notes: 1. The device is continuously selected. READ CYCLE NO. 2 (1) (OE# CONTROLLED) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS# tHZCS tACS DOUT HIGH-Z tLZCS LOW-Z DATA VALID HIGH-Z Notes: 1. Address is valid prior to or coincident with CS# LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 9 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL WRITE CYCLE NO. 1(1,2) (CS# Controlled, OE# = HIGH or LOW) tWC ADDRESS tSCS tSA tHA CS# tAW tPWE WE# tHZWE DATA UNDEFINED DOUT HIGH-Z (1) tSD DATA UNDEFINED DIN (2) tLZWE tHD DATA IN VALID Notes: 1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. (1,2) WRITE CYCLE NO. 2 (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# OE# DOUT tPWE tSA tHZOE DATA UNDEFINED HIGH-Z (1) tSD DIN DATA UNDEFINED (2) tHD DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 10 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL (1) WRITE CYCLE NO. 3 (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# tPWE tSA tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN DATA UNDEFINED (2) tLZWE tHD DATA IN VALID Notes: 1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 11 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL DATA RETENTION CHARACTERISTICS Symbol Parameter VDD for Data Retention VDR Data Retention Current IDR Test Condition OPTION Min. Typ. Max. Unit 1.5 - 3.6 V Com. - - 6 Ind. - - 8 Auto - - 20 See Data Retention Waveform VDD= VDR(min), CS# ≥ VDD – 0.2V (2) typ. uA tSDR Data Retention Setup Time See Data Retention Waveform 0 3.5 - - ns tRDR Recovery Time See Data Retention Waveform tRC - - ns Note: 1. If CS1# >VDD–0.2V, all other inputs including CS2 must meet this condition. 2. Typical values are measured at VDD = 3.0V, TA = 25C , and not 100% tested. 3. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode. DATA RETENTION WAVEFORM (CS# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS# CS# > VDD – 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 12 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL ORDERING INFORMATION IS62WV5128EALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 55 IS62WV5128EALL-55TI TSOP, Type I (8 x 20 mm) 55 IS62WV5128EALL-55TLI TSOP, Type I (8 x 20 mm), Lead-free 55 IS62WV5128EALL-55T2I TSOP, Type II 55 IS62WV5128EALL-55T2LI TSOP, Type II, Lead-free 55 IS62WV5128EALL-55BI mini BGA (6mm x 8mm) 55 IS62WV5128EALL-55BLI mini BGA (6mm x 8mm), Lead-free 55 IS62WV5128EALL-55HI sTSOP, (Type I) (8 x 13.4 mm) 55 IS62WV5128EALL-55HLI sTSOP (Type I), Lead-free (8 x 13.4 mm) AUTOMOTIVE RANGE (A3): –40°C TO +125°C *PLEASE CONTACT ISSI MARKETING IS62WV5128EBLL (2.2V – 3.6V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 IS62WV5128EBLL-45TI TSOP, Type I (8 x 20 mm) 45 IS62WV5128EBLL-45TLI TSOP, Type I (8 x 20 mm), Lead-free 45 IS62WV5128EBLL-45QLI SOP, Lead-free 45 IS62WV5128EBLL-45T2I TSOP, Type II 45 IS62WV5128EBLL-45T2LI TSOP, Type II, Lead-free 45 IS62WV5128EBLL-45BI mini BGA (6mm x 8mm) 45 IS62WV5128EBLL-45BLI mini BGA (6mm x 8mm), Lead-free 45 IS62WV5128EBLL-45HI sTSOP, (Type I) (8 x 13.4 mm) 45 IS62WV5128EBLL-45HLI sTSOP (Type I), (8 x 13.4 mm), Lead-free Automotive Range (A1): –40°C to +85°C Speed (ns) Order Part No. Package 45 IS65WV5128EBLL-45CT2LA1 TSOP (Type II), Lead-free, Copper Lead-frame 45 IS65WV5128EBLL-45BLA1 mini BGA (6mm x 8mm), Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 13 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL Automotive Range (A3): –40°C to +125°C Speed (ns) Order Part No. Package 55 IS65WV5128EBLL-55CT2LA3 TSOP (Type II), Lead-free, Copper Lead-frame 55 IS65WV5128EBLL-55BLA3 mini BGA (6mm x 8mm), Lead-free IS62WV5128ECLL (3.3V+/-5%) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 35 IS62WV5128ECLL-35TI TSOP, Type I (8 x 20 mm) 35 IS62WV5128ECLL-35TLI TSOP, Type I (8 x 20 mm), Lead-free 35 IS62WV5128ECLL-35QLI SOP, Lead-free 35 IS62WV5128ECLL-35T2I TSOP, Type II 35 IS62WV5128ECLL-35T2LI TSOP, Type II, Lead-free 35 IS62WV5128ECLL-35BI mini BGA (6mm x 8mm) 35 IS62WV5128ECLL-35BLI mini BGA (6mm x 8mm), Lead-free 35 IS62WV5128ECLL-35HI sTSOP, (Type I) (8 x 13.4 mm) 35 IS62WV5128ECLL-35HLI sTSOP (Type I), (8 x 13.4 mm), Lead-free Automotive Range (A3): –40°C to +125°C Speed (ns) Order Part No. Package 45 IS65WV5128ECLL-45CT2LA3 TSOP (Type II), Lead-free, Copper Lead-frame 45 IS65WV5128ECLL-45BLA3 mini BGA (6mm x 8mm), Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 14 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 15 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 16 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 17 IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 08/04/2015 18