RENESAS HD74LV123ATELL

HD74LV123A
Dual Retriggerable Monostable Multivibrators
REJ03D0314–0600Z
(Previous ADE-205-258D (Z))
Rev.6.00
Jun. 02, 2004
Description
The HD74LV123A features output pulse-duration control by three methods. In the first method, the A input is low and
the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A
input is low, the B input is high, and the clear (CLR) input goes high.
The basic pulse duration is programmed by selecting external resistance and capacitance values.
The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and Vcc
To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and Vcc.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-levelactive (B) input. Pulse duration can be reduced by taking CLR low.
Features
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV123AFPEL
SOP–16 pin(JEITA)
FP–16DAV
FP
EL (2,000 pcs/reel)
HD74LV123ARPEL
HD74LV123ATELL
SOP–16 pin(JEDEC)
TSSOP–16 pin
FP–16DNV
TTP–16DAV
RP
T
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.6.00 Jun. 02, 2004 page 1 of 15
HD74LV123A
Function Table
Inputs
Outputs
CLR
A
B
Q
Q
L
H
H
H
H
↑
X
H
X
L
↓
L
X
X
L
↑
H
H
L
L
L
H
H
H
Note: H:
L:
X:
↑:
↓:
:
:
High level
Low level
Immaterial
Low to high transition
High to low transition
High level pulse
Low level pulse
Pin Arrangement
16 VCC
1A 1
1B
2
15 1Rext / Cext
1CLR
3
14 1Cext
1Q 4
13 1Q
2Q
5
12 2Q
2Cext
6
11 2CLR
2Rext / Cext
7
10 2B
GND 8
9 2A
(Top view)
Rev.6.00 Jun. 02, 2004 page 2 of 15
HD74LV123A
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
VCC
Input voltage range*1
Output voltage range*1, 2
VI
VO
V
V
V
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation at
Ta = 25°C (in still air)*3
IIK
IOK
IO
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
Storage temperature
Tstg
ICC or IGND
PT
Conditions
Output: H or L
VCC: OFF
VI < 0
VO < 0 or VO > VCC
VO = 0 to VCC
mA
mA
mA
mA
mW
785
500
–65 to 150
SOP
TSSOP
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage range
VCC
Input voltage range
Output voltage range
Output current
VI
VO
IOH
2.0
0
0
—
—
—
—
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.5
5.5
VCC
–50
–2
–6
–12
50
2
6
12
200
100
20
V
V
V
µA
mA
—
—
Unlimited
—
—
—
—
—
kΩ
—
85
IOL
Input transition rise or fall rate
∆t /∆v
External timing resistance
Rext
External timing capacitance
Power-up ramp rate
Cext
∆t /∆VCC
5
1
—
1
Operating free-air temperature
Ta
–40
Note: Unused or floating inputs must be held high or low.
Rev.6.00 Jun. 02, 2004 page 3 of 15
µA
mA
ns/V
F
ms/
V
°C
Conditions
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
VCC ≥ 2.3 V
HD74LV123A
Logic Diagram
Cext
Rext/
Cext
A
Q
Q
Q
Q
B
CLR
CLR
Rev.6.00 Jun. 02, 2004 page 4 of 15
HD74LV123A
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)*
Min
Typ
Max
Unit
Input voltage
VIH
1.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
—
—
—
—
VCC – 0.1
2.0
2.48
3.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
—
—
—
—
0.1
0.4
0.44
0.55
±1
±2.5
V
Input current
Input current
Rext / Cext
IIN
IIN
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
Min to Max
2.3
3.0
4.5
Min to Max
2.3
3.0
4.5
0 to 5.5
5.5
Quiescent supply
current
ICC
5.5
—
—
Active state supply
current
(per circuit)
∆ICC
Output leakage
current
IOFF
2.3
3.0
4.5
5.5
0
—
—
—
—
—
Input capacitance
CIN
3.3
—
VIL
Output voltage
VOH
VOL
Test Conditions
µA
µA
IOH = –50 µA
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
IOL = 2 mA
IOL = 6 mA
IOL = 12 mA
VIN = 5.5 V or GND
VIN = VCC or GND
20
µA
VIN = VCC or GND, IO = 0
—
—
—
—
—
220
280
650
975
5
µA
VIN = VCC or GND
Rext/Cext = 0.5 VCC
µA
VI or VO = 0 V to 5.5 V
4.0
—
pF
VI = VCC or GND
V
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.6.00 Jun. 02, 2004 page 5 of 15
HD74LV123A
Switching Characteristics
VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Propagation
delay time
tPLH
tPHL
twQ
13.5
16.0
11.0
13.0
14.0
16.0
170
100
31.4
36.0
25.0
32.8
33.4
38.0
260
110
1.0
1.0
1.0
1.0
1.0
1.0
—
90
37.0
42.0
29.5
34.5
39.0
44.0
320
110
ns
Output pulse
width
—
—
—
—
—
—
—
90
ns
µs
0.9
1.0
1.1
0.9
1.1
ms
—
6.0
—
±1
—
40
—
—
—
—
6.5
—
—
—
—
%
ns
ns
—
1.5
—
—
—
µs
Pulse width
Retrigger time
∆twQ
tw
trr
Test
Conditions
FROM
(Input)
TO
(Output)
CL = 15 pF
A or B
Q or Q
CL = 50 pF
CL = 15 pF
CLR
Q or Q
CL = 50 pF
CL = 15 pF
CLR
Q or Q
(Trigger)
CL = 50 pF
CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
CL = 50 pF
A, B or CLR
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
A, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Propagation
delay time
tPLH
tPHL
twQ
9.7
11.5
8.0
9.5
9.9
11.5
150
100
20.6
24.1
15.8
19.3
22.4
25.9
240
110
1.0
1.0
1.0
1.0
1.0
1.0
—
90
24.0
27.5
18.5
22.0
26.0
29.5
300
110
ns
Output pulse
width
—
—
—
—
—
—
—
90
ns
µs
0.9
1.0
1.1
0.9
1.1
ms
—
5.0
—
±1
—
30
—
—
—
—
5.0
—
—
—
—
%
ns
ns
—
1.2
—
—
—
µs
Pulse width
Retrigger time
∆twQ
tw
trr
Rev.6.00 Jun. 02, 2004 page 6 of 15
Test
Conditions
FROM
(Input)
TO
(Output)
CL = 15 pF
A or B
Q or Q
CL = 50 pF
CL = 15 pF
CLR
Q or Q
CL = 50 pF
CL = 15 pF
CLR
Q or Q
(Trigger)
CL = 50 pF
CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
CL = 50 pF
A, B or CLR
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
A, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
HD74LV123A
Switching Characteristics (cont)
VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Propagation
delay time
tPLH
tPHL
twQ
7.3
8.5
5.9
7.5
7.3
8.7
140
100
12.0
14.0
9.4
11.4
12.9
14.9
200
110
1.0
1.0
1.0
1.0
1.0
1.0
—
90
14.0
16.0
11.0
13.0
15.0
17.0
240
110
ns
Output pulse
width
—
—
—
—
—
—
—
90
ns
µs
0.9
1.0
1.1
0.9
1.1
ms
—
5.0
—
±1
—
20
—
—
—
—
5.0
—
—
—
—
%
ns
ns
—
0.95
—
—
—
µs
Pulse width
Retrigger time
∆twQ
tw
trr
Test
Conditions
FROM
(Input)
TO
(Output)
CL = 15 pF
A or B
Q or Q
CL = 50 pF
CL = 15 pF
CLR
Q or Q
CL = 50 pF
CL = 15 pF
CLR
Q or Q
(Trigger)
CL = 50 pF
CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
CL = 50 pF
A, B or CLR
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
A, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test Conditions
Power dissipation capacitance
CPD
3.3
5.0
—
—
74.0
86.0
—
—
pF
f = 10 MHz
Test Circuit
VCC
Cext
−
VCC
Input
Refer
to
Function
Table
Rext
Cext = 28 pF or 100 pF or 0.01 µF or 0.1 µF
Rext = 1 kΩ or 2 kΩ or 10 kΩ
+
Cext Rext/
Cext
A
VCC
Q
Output
C L = 15 pF or 50 pF
B
Q
CLR
GND
Output
C L = 15 pF or 50 pF
Note : C L includes the probe and jig capacitance.
Rev.6.00 Jun. 02, 2004 page 7 of 15
HD74LV123A
Timing diagram
t rr
A
B
CLR
Rext/
Cext
Q
tw
tw
t w +t rr
Caution in use
In order to prevent any malfunctions due to noise, connect a high frequency
performance capacitor between Vcc and GND, and keep the wiring between the
External components and Cext, Rext/Cext pins as short as possible.
Large values of Cext may cause problems when powering down the HD74LV123A
because of the amount of energy stored in the capacitor. When a system containing
this device is powered down, the capacitor may discharge from Vcc through the protection
diodes at pin 7 or pin 15.
Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off
time of the Vcc power supply must not be faster than t = Vcc • Cext/(20 mA). For example,
if Vcc = 5 V and Cext = 22 µF, the Vcc supply must turn off no faster than t = (5 V) • (22 µF)/
20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of Vcc to zero volts occurs, the HD74LV123A may sustain damage.
To avoid this possibility, use an external calmping diode.
The input pins for unused circuit should be used under conditions to fix the outputs to avoid
malfunction cased by noises. Also, it's recommended that Rext / Cext terminals are open and
external parts are not connected to.
Rev.6.00 Jun. 02, 2004 page 8 of 15
HD74LV123A
• Waveform − 1
Input A
tf
VCC
90%
50%
10%
GND
tr
VCC
90%
50%
Input B
10%
GND
tf
tr
90%
50%
Input CLR
10%
tr
90%
50%
10%
90%
50%
10%
VCC
GND
t w (L)
t PLH (trigger)
t PHL
VOH
Output Q
50% V CC
50% V CC
VOL
t PHL (trigger)
t PLH
VOH
Output Q
50% V CC
50% V CC
VOL
Rev.6.00 Jun. 02, 2004 page 9 of 15
HD74LV123A
• Waveform − 2
Input A
tf
tr
90%
50%
10%
tr
90%
50%
10%
90%
50%
10%
t w (H)
tf
Input B
VCC
GND
t w (L)
tf
tr
90%
50%
90%
50%
10%
10%
t w (L)
VCC
90%
50%
10%
t w (H)
GND
VOH
Output Q
50% VCC
50% VCC
VOL
t w (out)
VOH
50% VCC
Output Q
50% VCC
VOL
• Waveform − 3
Input A
tf
tf
tr
90%
50%
90%
10%
VCC
90%
50%
10%
10%
t rr
tf
tr
Input B
90%
50%
tr
90%
50%
10%
90%
10%
GND
10%
VCC
GND
VOH
Output Q
50% VCC
50% VCC
VOL
t w (out) + t rr
VOH
Output Q
50% VCC
50% VCC
VOL
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Rev.6.00 Jun. 02, 2004 page 10 of 15
HD74LV123A
Application Data
Vcc = 2.5 V
t WQ (µs)
10000.0
1000.0
Output pulse width
100.0
10.0
Rext
1 kΩ
10 kΩ
100 kΩ
1 MΩ
1.0
0.1
10
2
10
3
10
4
Timing capacitance
10
5
10
6
10
7
Cext (pF)
Vcc = 3.3 V
t WQ (µs)
10000.0
1000.0
Output pulse width
100.0
10.0
Rext
1 kΩ
10 kΩ
100 kΩ
1 MΩ
1.0
0.1
10
2
10
3
10
4
Timing capacitance
Rev.6.00 Jun. 02, 2004 page 11 of 15
10
5
Cext (pF)
10
6
10
7
HD74LV123A
Vcc = 5.0 V
t WQ (µs)
10000.0
1000.0
Output pulse width
100.0
10.0
Rext
1 kΩ
10 kΩ
100 kΩ
1 MΩ
1.0
0.1
10
2
10
3
10
4
10
Timing capacitance
5
10
6
10
7
Cext (pF)
Rext = 2 kΩ
1.4
Coefficient of output pulse width
K
Cext
1000 pF
10000 pF
100000 pF
1000000 pF
1.3
1.2
1.1
1.0
0.9
0.8
2.0
2.5
3.0
3.5
4.0
Supply voltage
Rev.6.00 Jun. 02, 2004 page 12 of 15
4.5
VCC (V)
5.0
5.5
6.0
HD74LV123A
Rext = 10 kΩ
1.4
Coefficient of output pulse width
K
Cext
1000 pF
10000 pF
100000 pF
1000000 pF
1.3
1.2
1.1
1.0
0.9
0.8
2.0
2.5
3.0
3.5
4.0
Supply voltage
Rev.6.00 Jun. 02, 2004 page 13 of 15
4.5
VCC (V)
5.0
5.5
6.0
HD74LV123A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
1
8
1.27
*0.40 ± 0.06
0.20
7.80 +– 0.30
1.15
0 ˚ – 8˚
0.10 ± 0.10
0.80 Max
*0.20 ± 0.05
2.20 Max
5.5
16
0.70 ± 0.20
0.15
0.12 M
Package Code
JEDEC
JEITA
Mass (reference value)
*Ni/Pd/Au plating
FP-16DAV
—
Conforms
0.24 g
As of January, 2003
Unit: mm
9.9
10.3 Max
9
1
8
0.635 Max
*0.40 ± 0.06
0.15
*0.20 ± 0.05
1.27
0.11
0.14 +– 0.04
1.75 Max
3.95
16
0.10
6.10 +– 0.30
1.08
0˚ – 8˚
0.67
0.60 +– 0.20
0.25 M
*Ni/Pd/Au plating
Rev.6.00 Jun. 02, 2004 page 14 of 15
Package Code
JEDEC
JEITA
Mass (reference value)
FP-16DNV
Conforms
Conforms
0.15 g
HD74LV123A
As of January, 2003
Unit: mm
4.40
5.00
5.30 Max
16
9
1
8
0.65
1.0
0.13 M
6.40 ± 0.20
*Ni/Pd/Au plating
Rev.6.00 Jun. 02, 2004 page 15 of 15
0.10
*0.15 ± 0.05
1.10 Max
0.65 Max
0.07 +0.03
–0.04
*0.20 ± 0.05
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-16DAV
—
—
0.05 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0