HD151012 8-bit Binary Programmable Counter with Synchronous Preset Enable REJ03D0299–0200Z (Previous ADE-205-132 (Z)) Preliminary Rev.2.00 Jul.16.2004 Description The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider. Features • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) • High output current Fanout of 10 LS TTL Loads • Wide operating voltage VCC = 2 to 6 V • Low supply current (Ta = 25°C) ICC (Static) = 4 µA (max) • Ordering Information Part Name Package Type HD151012TELL TSSOP-16 pin Package Code TTP-16DAV Package Abbreviation T Taping Abbreviation (Quantity) ELL (2,000 pcs/reel) Function Table Control Inputs CLR SPE H H PR H Mode Generally count Operation Description Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) X X L Synchronous preset L H — Initialize of Q output Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Initialize of Q = “L” H L — Initialize of Q output Initialize of Q = “H” Notes: 1. Synchronous preset (SPE) input can set max 256 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. H : High level L : Low level X : Immaterial — : Irrespective of condition Rev.2.00, Jul.16.2004, page 1 of 13 HD151012 Pin Arrangement J0 1 16 VCC J1 2 15 CLK J2 3 14 CLK J3 4 13 Q J4 5 12 PR J5 6 11 SPE J6 7 10 CLR GND 8 9 J7 (Top view) Pin Description Pin Name Input pins Output pins Pin Description J0 to J7 CLK, CLK Count data input for option Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger SPE PR Preset input for Jn data Preset input for D-type Flip Flop (Initialize “L” at Q output) CLR Q Clear input for D-type Flip Flop (Initialize “H” at Q output) Output for D-type Flip Flop Absolute Maximum Ratings Item Symbol Supply voltage VCC Ratings –0.5 to 7.0 Unit Input / output voltage VCC, GND current VIN/VOUT ICC, IGND –0.5 to VCC +0.5 ±50 V mA Output current / pin Power dissipation IOUT PT ±25 500 mA mW Storage temperature Input diode current Tstg IIK –65 to 150 ±20 °C mA V Output diode current IOK ±20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. Rev.2.00, Jul.16.2004, page 2 of 13 HD151012 Recommended Operating Conditions Item Symbol Supply voltage Input/output voltage Operating temperature Input rise/fall time*1 VCC = 2.5 V Typ Max Unit 2 0 — — 6 VCC V V Topr tr, tf –40 0 — — +85 1000 °C ns 0 0 — — 500 400 VCC = 4.5 V VCC = 5.5 V Note: Min VCC VIN/OUT 1. This item guarantees maximum limit when one input switches. Logic Diagram J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7 CLK CLK 8-bit binary counter J0 CLK PR PR Q D CO SPE CK Q Q CLR SPE CLR Rev.2.00, Jul.16.2004, page 3 of 13 HD151012 Electrical Characteristics Ta = 25°C Item High level input Symbol VCC Min Typ Max Min Max Unit VIH 2.0 1.5 — — 1.5 — V J0 to J7 voltage Low level input VIL voltage High level output VOH voltage Low level output voltage Ta = –40 to 85°C VOL 4.5 6.0 3.15 4.2 — — — — 3.15 4.2 — — SPE PR, CLR 2.0 4.5 1.5 3.15 — — — — 1.5 3.15 — — CLK, CLK 6.0 2.0 4.2 — — — — 0.5 4.2 — — 0.5 4.5 6.0 — — — — 1.35 1.8 — — 1.35 1.8 SPE PR, CLR 2.0 4.5 — — — — 0.5 1.35 — — 0.5 1.35 CLK, CLK 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 6.0 4.4 5.9 4.5 6.0 — — 4.4 5.9 — — 4.5 6.0 4.18 5.68 4.31 5.80 — — 4.13 5.63 — — 2.0 4.5 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 6.0 4.5 — — 0.0 0.17 0.1 0.26 — — 0.1 0.33 V V Test Conditions J0 to J7 VIN = VIH or VIL IOH = –4 mA IOH = –5.2 mA V VIN = VIH or VIL IOL = 20 mA IOL = 4 mA Input capacitance IIN 6.0 6.0 — — 0.18 — 0.26 ±0.1 — — 0.33 ±1.0 mA VIN = VCC or GND Supply current ICC 6.0 — — 4.0 — 40.0 mA VIN = VCC or GND Rev.2.00, Jul.16.2004, page 4 of 13 IOH = –20 mA IOL = 5.2 mA HD151012 Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) SymItem Maximum clock bol fmax frequency Ta = 25°C Ta = –40 to 85°C VCC Min Typ Max Min Max Unit 2.0 — — 4 — 3 MHz 4.5 6.0 — — 36 — 20 24 — — 16 19 Output rise/fall time tTLH tTHL 2.0 4.5 — — 30 8 75 15 — — 95 19 Propagation delay tPLH 6.0 2.0 — — 7 — 13 300 — — 16 380 time tPHL 4.5 6.0 — — 35 — 60 53 — — 75 65 tPLH tPHL 2.0 4.5 — — — 18 150 30 — — 185 38 tw 6.0 2.0 — 80 — — 25 — — 100 32 — 4.5 6.0 16 14 — — — — 20 17 — — 2.0 4.5 100 20 — — — — 125 25 — — 6.0 2.0 17 15 — — — — 21 15 — — 4.5 6.0 10 5 — — — — 10 5 — — — — — — 5 48 10 — — — 10 — Pulse width (CLK, CLK, PR, CLR) Setup time (Jn - CLK, CLK) (SPE, CLK, CLK) Hold time ts th (Jn - CLK, CLK) (SPE, CLK, CLK) Input capacitance Power dissipation capacitance*1 Note: CIN CPD Test Conditions ns CLK or CLK to Q PR or CLR to Q ns ns ns pF pF 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. ICC (opr) = CPD • VCC • fIN + ICC Rev.2.00, Jul.16.2004, page 5 of 13 HD151012 Test Circuit VCC VCC Input J0 J1 Pulse generator See Function Table Zout = 50 Ω Input Pulse generator Zout = 50 Ω Output Q J7 CLK CLK CL SPE PR CLR Note: 1. CL includes probe and jig capacitance. Waveforms – 1 tw tw 6 ns 6 ns CLK 50 % CLK VCC 90 % 90 % 50 % 10 % 10 % t PLH t PHL 90 % 50 % Q GND 10 % t TLH Rev.2.00, Jul.16.2004, page 6 of 13 VOH 90 % 50 % 10 % t THL VOL HD151012 Waveforms – 2 6 ns 90 % Jn VCC 90 % 50 % 10 % 10 % GND ts CLK 90 % VCC 10 % 6 ns GND 50 % CLK 10 % VOH *1 50 % F/F Output VOL Internal delay Waveforms – 3 6 ns 90 % Jn 90 % VCC 50 % 10 % 10 % th CLK GND 90 % VCC 10 % 6 ns GND 50 % CLK 10 % VOH *1 50 % F/F Output Internal delay Note: 1. F/F output is internal signal of IC. Rev.2.00, Jul.16.2004, page 7 of 13 VOL HD151012 Waveforms – 4 6 ns 90 % SPE VCC 90 % 50 % 10 % 10 % GND ts CLK 90 % VCC 10 % 6 ns GND 50 % CLK 10 % VOH *1 50 % F/F Output VOL Internal delay Waveforms – 5 6 ns 90 % SPE 90 % VCC 50 % 10 % 10 % th CLK GND 90 % VCC 10 % 6 ns GND 50 % CLK 10 % VOH *1 50 % F/F Output Internal delay Note: 1. F/F output is internal signal of IC. Rev.2.00, Jul.16.2004, page 8 of 13 VOL HD151012 Waveforms – 6 tf tr 90 % CLR VCC 90 % 50 % 50 % 10 % 10 % GND tw tf tr 90 % 90 % VCC PR 50 % 50 % 10 % 10 % GND tw t PHL t PLH VOH Q 50 % 50 % VOL Rev.2.00, Jul.16.2004, page 9 of 13 HD151012 Timing Chart CLK SPE J0 J1 J2 J3 J4 J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 5 Rev.2.00, Jul.16.2004, page 10 of 13 4 3 2 1 0 3 2 1 0 35 34 HD151012 Example of Application Circuit AC Signal Generator for STN Type Liquid Crystal Panel Initialize counter: 50 J0 V CC J1 CLK J2 CLK J3 Q J4 PR J5 SPE J6 CLR GND Note: When initializing output D-F/F apply “L” Rev.2.00, Jul.16.2004, page 11 of 13 J7 * * HD151012 Timing Chart Example of AC Signal Generator 1 2 3 50 49 48 49 50 51 52 53 101 102 1 0 103 104 CLK SPE J0 J1 J2 J3 50 J4 J5 J6 J7 (CO=SPE) CLR Q PR Q Count Rev.2.00, Jul.16.2004, page 12 of 13 2 1 0 50 49 50 49 HD151012 Package Dimensions As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.2.00, Jul.16.2004, page 13 of 13 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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