ISOFACE™ ISO1I811T Isolated 8 Channel Digital Input with IEC61131-2 Type 1/2/3 Characteristics Data Sheet Revision 2.0, 2012-06-14 Industrial & Multimarket Edition 2012-06-14 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ISO1I811T ISO1I811T Revision History: 2012-06-14, Revision 2.0 Previous Version: Preliminary Data Sheet V1.0 Page Subjects (major changes since last revision) V2.0 Data Sheet Page 25 Parallel Interface timing table updated Page 26 Serial Interface timing table updated Data Sheet 3 Revision 2.0, 2012-06-14 ISO1I811T 1 1.1 1.2 1.2.1 1.2.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins of Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins of Serial and Parallel logic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Error Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Digital Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Standard Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 5.1 5.2 5.3 5.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions and Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Input Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data Sheet 4 6 6 8 8 9 11 11 11 12 12 14 14 15 16 19 19 20 22 24 Revision 2.0, 2012-06-14 ISO1I811T Isolated 8 Channel Digital Input with IEC61131-2 Type 1/2/3 Characteristics Product Highlights • • • • Minimization of power dissipation due to constant current characteristic Status LED output for each input Digital averaging of the input signals to suppress interference pulses Isolation between Input and Output using Coreless Transformer Technology Features Description • The ISO1I811T is an electrically isolated 8 bit data input interface in TSSOP-48 package. • • • • • • • Complete system integration (up to eight digital sensor or switch inputs, galvanic isolation and intelligent micro-controller or bus-ASIC interface) 8-channel input according to IEC61131-2 (Type 1/2/3) Integrated galvanic isolation 500VAC (EN60664-1, UL1577) 3.3/5V SPI and parallel micro-controller interface Adjustable deglitching filters Up to 125 kHz sampling frequency VBB under-voltage detection Package: TSSOP-48, 8 mm x 12.5 mm This part is used to detect the signal states of eight independent input lines according to IEC61131-2 Type 1/2/3 (e.g. two-wire proximity switches) with a common ground (GNDFI). For operation in accordance with IEC61131-2, it is necessary for the ISO1I811T to be wired with resistors according to the application diagram. The 8 bit parallel/serial µC compatible interface allows the IC to directly connect to a µC system. The µC interface also supports a direct control mode and is designed to operate with 3.3/5V CMOS compatible levels. Typical Application Programmable Logic Controllers(PLC) The data transfer and isolation from input to output side is realized by the integrated Coreless Transformer Technology. Industrial PC General Control Equipment VFI VBB 330n VCC TS 8 sensors Rosc IN0 12k I0H 2k I0L IN7 12k GNDFI I7H 2k I7L S E R I A L I Z E D E S E R I A L I Z E DS0 digital filter DS1 L O G I C /ERR µC /RD /CS e.g. XE166 parallel or serial interface digital filter GND GNDBB ISO1I811T Data Sheet 5 Revision 2.0, 2012-06-14 ISO1I811T Pin Configuration and Functionality 1 Pin Configuration and Functionality The pin configuration slightly differs for the parallel or the serial interface. 1.1 Pin Configuration The ordering, type and functions of the IC pins are listed in the Table 1. Table 1 Pin Pin Configuration Parallel Interface Mode Symbol Serial Interface Mode Ctrl Type Function 1) Symbol 1 GND 2 SEL 3 n.c. 4 ROSC A Clock Frequency Adjustment ROSC 5 VCC A Positive 5/3.3V logic supply VCC 6 ERR OD, PU Error output ERR 7 GND A Logic Ground GND I O A Logic Ground GND PU Serial Parallel Mode Select SEL not connected n.c. 8 D0 O PPZ Data output bit0 SDI 9 D1 O PPZ Data output bit1 GND 10 D2 O PPZ Data output bit2 GND 11 D3 O PPZ Data output bit3 GND 12 D4 O PPZ Data output bit4 GND 13 D5 O PPZ Data output bit5 SCLK 14 D6 O PPZ Data output bit6 GND 15 D7 O PPZ Data output bit7 SDO 16 CS I PU Chip Select CS 17 RD I PU Data Read Input n.c. 18 GND A Logic Ground GND 19 DS0 I PD Filter Select Input 0 DS0 20 DS1 I PD Filter Select Input 1 DS1 21 GND A Logic Ground GND 22 n.c. not connected n.c. 23 n.c. not connected n.c. 24 GND A Logic Ground GND 25 GNDBB A Input Ground GNDBB 26 VBB A Positive input supply voltage VBB 27 I0L A Input 0 Low, LED Out I0L 28 I0H A Input 0 High I0H 29 I1L A Input 1 Low, LED Out I1L 30 I1H A Input 1 High I1H 31 GNDBB A Input Ground GNDBB 32 I2L A Input 2 Low, LED Out I2L Data Sheet Ctrl. Type Function 2) 6 I PD SPI Data input I PD SPI Shift Clock input O PPZ SPI Data output not connected Revision 2.0, 2012-06-14 ISO1I811T Pin Configuration and Functionality Table 1 Pin Pin Configuration Parallel Interface Mode Symbol Serial Interface Mode Ctrl Type Function 1) Symbol Ctrl. Type Function 2) 33 I2H A Input 2 High I2H 34 I3L A Input 3 Low, LED Out I3L 35 I3H A Input 3 High I3H 36 TS A Sensor Type 1/2/3 Select TS 37 GNDBB A Input Ground GNDBB 38 n.c. not connected n.c. 39 I4L A Input 4 Low, LED Out I4L 40 I4H A Input 4 High I4H 41 I5L A Input 5 Low, LED Out I5L 42 I5H A Input 5 High I5H 33 GNDBB A Input Ground GNDBB 44 I6L A Input 6 Low, LED Out I6L 45 I6H A Input 6 High I6H 46 I7L A Input 7 Low, LED Out I7L 47 I7H A Input 7 High I7H 48 GNDBB A Input Ground GNDBB 1) Direction of the pin: I = input, O = output, IO = Input/Output 2) Type of the pin: A = analog, OD = Open-Drain, PU = internal Pull-Up resistor, PD = internal Pull-Down resistor, PPZ = Push-Pull pin with High-Impedance functionality Data Sheet 7 Revision 2.0, 2012-06-14 ISO1I811T Pin Configuration and Functionality GND 1 48 GNDBB GND 1 48 GNDBB SEL 2 47 I7H SEL 2 47 I 7H n.c. 3 46 I7L n.c. 3 46 I7L Rosc 4 45 I6H Rosc 4 45 I 6H VCC 5 44 I6L VCC 5 44 I6L /ERR 6 43 GNDBB /ERR 6 43 GNDBB GND 7 42 I5H GND 7 42 I 5H D0 8 41 I5L SDI 8 41 I5L D1 9 40 I4H GND 9 40 I 4H D2 10 39 I4L GND 10 39 I4L D3 11 38 n.c. GND 11 38 n.c. D4 12 37 GNDBB GND 12 D5 13 36 TS SCLK 13 D6 14 35 I3H GND D7 15 34 I3L SDO /CS 16 33 I2H Pinout for parallel Interface 37 GNDBB 36 TS 14 35 I 3H 15 34 I3L /CS 16 33 I 2H Pinout for serial Interface /RD 17 32 I2L n.c. 17 32 I2L GND 18 31 GNDBB GND 18 31 GNDBB DS0 19 30 I1H DS0 19 30 I 1H DS1 20 29 I1L DS1 20 29 I1L GND 21 28 I0H GND 21 28 I 0H n.c. 22 27 I0L n.c. 22 27 I0L n.c. 23 26 VBB n.c. 23 26 VBB GND 24 25 GNDBB GND 24 25 GNDBB n.c. = Not Connected Figure 1 TSSOP-48 Pinout for Parallel and Serial Interface 1.2 Pin Functionality The meaning and the functions of the IC pins are described below. 1.2.1 Pins of Sensor Interface VBB (Positive supply 9.6-35V sensor supply) VBB supplies the sensor input stage. GNDBB (Ground for VBB domain) This pin acts as the ground reference for the sensor input stage, that is supplied by VBB. I0H... I7H (Input channel 0 ... 7) Sensor inputs with current sink characteristic according IEC61131-2 Type 1/2/3 which has been selected by pin TS I0L... I7L (LED output channel 0 ... 7) This pin provides the output signal to switch on the LED if the input voltage and current has been detected as “High” according the selected type. TS (Type Select) By connecting a resistor between TS and GNDBB the sensor type (Type 1/2/3) can be selected (refer to Table 9 for corresponding resistor value). This pin is for static configuration (pin-strapping). The voltage level at pin TS is not allowed to be changed during operation. Data Sheet 8 Revision 2.0, 2012-06-14 ISO1I811T Pin Configuration and Functionality 1.2.2 Pins of Serial and Parallel logic Interface Some pins are common for both interface types, some others are specific for the parallel or serial access. VCC (Positive 3.3 / 5V logic supply) VCC supplies the output interface that is electrically isolated from the sensor input stage. The interface can be supplied with 3.3 / 5V. GND (Ground for VCC domain) This pin is the ground reference for the uC-interface that is supplied by VCC. ROSC (Clock Adjustment) A high precision resistor has to be connected between ROSC and GND to guarantee the frequency accuracy of the sampling clock. For details see Chapter 3.3. ERR (Error Output) The low active ERR signal contains the OR-wired information of the sensor input missing voltage (MV) detection and the internal data transmission failure detection unit. The output pin ERR provides an open drain functionality. A current source is also connected to the pin ERR. In normal operation the signal ERR is high. See Chapter 3.5 for more details. DS0, DS1 (Filter Select) The internal filter delay can be selected by pulling those pins to VCC or to GND (see Table 10). These pins are for static configuration (pin-strapping). CS (Chip Select) When this pin is in a logic Low state, the IC interface is enabled and data can be transferred. SEL (Serial or Parallel Mode Select) When this pin is in a logic High state, the IC operates in Serial Mode. For Parallel Mode operation the pin has to be pulled into logic Low state. This pin has an internal Pull-UP resistor. The following pins are provided by the parallel interface D7:D0 (Data output bit7 ... bit0) The pins D0 .. D7 are the outputs for data read. RD (Read Select) By pulling this pin down, a read transaction is initiated on the data bus and the data becomes valid. The following pins are provided by the serial interface SCLK (Serial interface shift clock) Output data is updated with the falling edge of this input clock signal. SDI (Serial interface input data) SDI is put into a FIFO dedicated to the sensor data bits (no internal registers Write operation supported, only daisy chain). Input data is sampled with the rising edge of SCLK. SDO (Serial interface data) SDO provides the sensor data bits. Data Sheet 9 Revision 2.0, 2012-06-14 ISO1I811T Blockdiagram 2 Blockdiagram VBB ROSC UVLO VCC OSC MV UVLO CLK Startup TS Type Selector /ERR TX/RX Control TX/RX Common Control Error DS0 Validation DATA I0H I0L Sensor Circuit 0 DATA Sensor Circuit 1 DATA Sensor Circuit 2 DATA Sensor Circuit 3 DATA Sensor Circuit 4 DATA I1H I1L I2H I2L I5H I5L DATA Sensor Circuit 6 DATA Sensor Circuit 7 DATA I7H I7L E S R E I L Sensor Circuit 5 I6H I6L E A I4H I4L S Data Sheet DATA A I L Z I E Z GNDBB Figure 2 I E Filter 1 DATA DATA /RD D7 DATA R /CS Filter 0 DATA DATA I3H I3L D DS1 U P D A T E G A T E Filter 2 D6 D5 D4 Filter 3 Interface Filter 4 Handler D3 D2 D1 D0 Filter 5 SCLK Filter 6 SDO SDI DATA parallel interface serial interface Filter 7 SEL GND Block Diagram 10 Revision 2.0, 2012-06-14 ISO1I811T Functional Description 3 Functional Description The ISO1I811T is an electrically isolated 8 bit data input interface. This part is used to detect the signal states of eight independent input lines according to IEC61131-2 Type 1/2/3 (e.g. two-wire proximity switches) with a common ground (GNDBB). 3.1 Introduction The current in the input circuit is determined by the switching element in state “0” and by characteristics of the input stage in state “1”. The octal input device is intended for a configuration comprising of two specified external resistors per channel, as shown in Figure 5 “Typical Application for Sensor Input Type 1, 2, and 3” on Page 13. As a result the power dissipation within the package is at a minimum. The voltage dependent current through the external resistor REXT is compensated by a negative differential resistance of the current sink across pins IxH and IxL, therefore input INx behaves like a constant current sink. The comparator assigns level 1 or 0 to the voltage present at input IxH. To improve interference protection, the comparator is provided with hysteresis. A status LED is connected in series with the input circuit (REXT and current sink). If no LED is used an external resistor of 2 kΩ should be connected between IxL and GNDBB. The specified switching thresholds may change if the resistor is used. The LED drive short-circuits the status LED if the comparator detects “0”. A constant current sink in parallel with the LED reduces the operating current of the LED, and a voltage limiter ensures that the input circuit remains operational if the LED is interrupted, but the specified switching thresholds may change. For each channel an adjustable digital filter is provided which samples the comparator signal at a rate selected by the pins DS0 and DS1. The digital filter is designed to provide averaging characteristics. If the input value remains the same for the selected number of sampling values, then the output changes to the corresponding state. The control interface is compatible to standard microcontrollers. Furthermore a direct control mode can be selected that allows the direct control of the outputs D0...D7 by means of the inputs I0H...I7H without any additional logic signal. The µC compatible interfaces allows a direct connection to the ports of a microcontroller without the need for other components. The diagnostic logic on the chip monitors the internal data transfer as well as the sensor input supply. The information is sent via the internal coreless transformer to the pin ERR at the µC-Interface side. 3.2 Power Supply The IC contains two electrically isolated voltage domains that are independent from each other. The microcontroller interface is supplied via pin VCC and the input stage is supplied via pin VBB. The different voltage domains can be switched on at different times. Figure 3 shows the Start Up behaviour if both voltage domains are powered by an external power supply. If the VCC and VBB voltage have reached their operating range and the internal data transmission has been started successfully, the IC indicates the end of the Start Up procedure by setting the pin ERR to logic high. Data Sheet 11 Revision 2.0, 2012-06-14 ISO1I811T Functional Description VBB Missing Voltage VBB UVLO V B B VCC UVLO VC C tER Rstart 1 /ERR 0 tds_startup_timing_STD. vsd Figure 3 Start-Up 3.3 Internal Oscillator An external resistor has to be connected to ROSC pin and allows the adjustment of the frequency as shown in Figure 4. 160 140 120 KHz 100 80 60 40 20 0 50 70 90 110 130 150 170 190 210 230 Resistance at Rosc (KOhm) Figure 4 Internal Frequency Setting at ROSC The internal oscillator provides the scan clock for the sampling of the sensor data as well as for the internal digital averaging filters. Therefore the filter times as defined in the Table 10 for the typical frequency of 125 KHz will change accordingly. As an example, it is possible to define filter time longer than 20 ms by reducing the internal oscillator frequency. 3.4 Sensor Input The sensor input structure is shown in Figure 5. Due to its active current a V-I-characteristic as shown in Figure 6 is maintained. This V-I-curve is well within the IEC 61131 standard requirements of Type 1 and Type 3 sensors, respectively. Type 2 sensors are supported as well with the restriction that two input channels have to be used in parallel i.e. only 4 channels are available. It is recommended to choose for the external resistors Rext, RV, RLED an accuracy of 2 % (< 5% is mandatory) otherwise the V/I-characteristic shown in Figure 6 cannot be guaranteed. Data Sheet 12 Revision 2.0, 2012-06-14 ISO1I811T Functional Description VFI VBB Sensor x x = 1,...,8 TS RTS RV INx IxH DATAx Rext IxL GNDBB Type 1,3 Figure 5 Type 2 RV 2kΩ 1.5kΩ Rext 12kΩ 8.5kΩ Typical Application for Sensor Input Type 1, 2, and 3 VFI=30V 15V/11V VINxDset VINxDhys VINxDclr active current sink 5V -3V 2mA/3mA I INxsnkC,M 0.5mA Data Bit must be zero Figure 6 Data Sheet 15mA Data Bit must be one Sensor Input Characteristics 13 Revision 2.0, 2012-06-14 ISO1I811T Functional Description 3.5 Common Error Output The input (VBB) missing voltage status which is transmitted via the integrated coreless transformer to the output block and the internal data transmission monitoring information are evaluated in the common error output block, see Figure 7. In case of an internal data transmission error the data bits are replaced by the last valid transmission. Moreover, if four consecutive erroneous data transmissions (TE1=1, see Figure 7) occur, an internal error signal TE4 (see Figure 7) is set. The average filters are reset. This status is held until four consecutive error-free transmissions (TE1=0) occur. An example timing diagram is shown in Figure 7. The internal W4S (Wait for Sense) signal indicates whether the Sense Input interface is operating properly or not. This internal error signal is OR-wired with the current VBB missing voltage status. Since the output error signal is active low, the OR-wired result is negated. The output stage at pin ERR has an open drain functionality with a pull-up resistor. See Table 12 for the electrical characteristics. scan trigger transmission error VBB missing voltage Wait for Sense TRIG TE1 TRIG filter MV TE4 TE1 N O R /ERR 0 1 2 3 0 1 2 3 TE4 W4S Figure 7 Common Error Output 3.6 Programmable Digital Input Filter The sensor data bits can be filtered by a configurable digital input filter. If selected, the filter changes its output according to an averaging rule with a selectable average length. When the sensor state changes without any spikes and noise the change is delayed by the averaging length. Sensor spikes that are shorter than the averaging length are suppressed. Figure 8 shows the behavior of the filter. scan trigger filter input output is 1 N-1 N-2 N-3 output is unchanged filter state 2 1 0 output is 0 filter output averaging time Figure 8 Digital Filter Behavior The averaging length is selected using the configuration pins DS0 and DS1. See Table 10 for the different setting options including filter bypass. The filters are dimensioned for the nominal internal sampling fscannom. The corresponding filter delays can be adjusted by changing the oscillator frequency i.e. by tuning the resistor at the ROSC pin. Data Sheet 14 Revision 2.0, 2012-06-14 ISO1I811T Functional Description 3.7 Parallel Interface Mode The ISO1I811T contains a parallel interface that can be selected by pulling the SEL Pin to logic low state. It can be directly controlled by the microcontroller output ports. (Figure 9, left side). The output pins D7:D0 are in state “Z” as long as CS=1. Otherwise, new sensor data bits bits are sampled with the falling edge of RD and provided at pins D7:D0. The parallel interface can also be switched over to a direct control mode to observe continuously the changes of the inputs I0H ... I7H by means of the corresponding outputs D7:D0 without additional logic signals. To activate the parallel direct control mode pin CS and pin RD have to be connected both to ground (permanently as in Figure 9, right side or by the microcontroller ports). The Direct Control Mode is entered when at least CS and RD are held low for tdirect (Table 14). VCC VCC VCC /CS /CS /RD /RD D0 D0 D1 D1 D2 D3 D2 D3 D4 D4 D5 D5 D6 D6 D7 ISO1I811T Figure 9 VCC D7 MCU (e.g. XE166) or ASIC SEL ISO1I811T MCU (e.g. XE166) or ASIC SEL parallel _interface1.vsd Parallel Bus Configuration for µC-Control-Mode (left) or Direct Control Mode (right) The timing requirements for the parallel interface are shown in Figure 10 and in Table 14. /CS tCSD /RD tCSS tRD tRDlow tdirect tfloat tvalid D7:D0 scan event tvalid data t scan tscan data data data data ~8 scan cycles direct control mode Figure 10 Data Sheet Parallel Bus Timing 15 Revision 2.0, 2012-06-14 ISO1I811T Functional Description 3.8 Serial Interface Mode The ISO1I811T contains a serial interface that can be activated by pulling the SEL pin to logic High state. It can be directly controlled by the microcontroller output ports. The output pin SDO is in state “Z” as long as CS=1. Otherwise, the bits are sampled with the falling edge of CS. Subsequently with every falling edge of SCLK the bits are provided serially to the pin SDO. At the same time, the input to SDI is put into an 8bit FIFO buffer sampled with the rising edge of SCLK. When all 8 internally sampled bits have been put to SDO, the buffered bits from the input SDI are provided to the serial output pin SDO (Daisy Chain Mode). The timing requirements for the parallel interface are shown in Figure 11 and in Table 15. inactive /CS t SCLK_su active tCSD t SCLK receive edge SCLK t SU transmit edge t HD tSU t CSH MSB SDI LSB tCS_valid SDO Figure 11 t SCLK_valid MSB tfloat LSB Serial Bus Timing Several SPI topologies are supported: pure bus topology and daisy-chain (Figure 12). Of course independent individual control with dedicated SPI controller interfaces for each slave IC are possible, as well. A SCLK SCLK SDO MISO A SCLK SCLK SDO MISO SDI /CS /CS B SCLK B SDO SCLK SDO SDI /CS C SCLK MCU or ASIC /CS C SDO SCLK MCU or ASIC SDO SDI /CS /CS D SCLK D SDO SCLK SDO SDI /CS /CS spi_topologies .vsd Figure 12 Data Sheet Example SPI Topologies 16 Revision 2.0, 2012-06-14 ISO1I811T Standard Compliance 4 Standard Compliance The ISO1I811T allows the design of a sensor interface compliant with the standard requirements listed below: System Insulation Characteristics as shown in Table 3, System Maximum Ratings as shown in Table 2. There requirements are valid for an application using the ISO1I811T including external circuitry (as proposed in Figure 13), not for the IC alone. Note: When the IC is not supplied via VBB , probing of the digital input interface is still possible due to the external circuitry, i.e. the 12k resistor and the LED. In addition to the current through the LED a small current IIxH flows through the pins IxH and IxL. VBB VFI 330n VCC TS 8 sensors Rosc IN0 12k I0H 2k I0L I7H IN7 12k GNDFI D E S E R I A L I Z E S E R I A L I Z E 2k I7L DS0 digital filter DS1 L O G I C /ERR µC /RD /CS e.g. XE166 parallel or serial interface digital filter GND GNDBB ISO1I811T Figure 13 Recommended Application Circuit Table 2 System Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Unit Max. Field Input Voltage Overvoltage 1300 ms VFIov -45 +45 V Input Voltage INx VINx -45 +45 V + I Figure 14 Data Sheet VISO RIO ,C IO Note / Test Condition − O System Insulation Characteristics 17 Revision 2.0, 2012-06-14 ISO1I811T Standard Compliance Table 3 System Insulation Characteristics Parameter Symbol Values Min. Typ. Pollution Degree (DIN VDE 0110/1.89, DIN EN 60664-1) Unit Max. Note / Test Condition 2 Minimum External Clearance CLR 6.7 mm Minimum External Creepage CPG 6.2 mm Maximum Working Insulation Voltage VISO 500 VAC 1 min duration1) 1) not subject to production test, verified by characterization Approvals: UL1577 Certificate Number: 20120309-E311313 Data Sheet 18 Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics 5 Electrical Characteristics This section comprises: • • • Operating Conditions and Power Supply (see Section 5.2) Electrical Characteristics Input Side (see Section 5.3) Electrical Characteristics Microcontroller Interface (see Section 5.4) Tolerance values always contain the sum of process-related tolerance values and tolerance-values based on the temperature drift within the specified temperature range. 5.1 Absolute Maximum Ratings All voltages at pins 25 to 48 are measured with respect to ground GNDBB. All voltages at pins 1 to 24 are measured with respect to GND. The voltage levels are valid if other ratings are not violated. The two voltage domains VCC, GND and VBB, GNDBB are internally electrically isolated. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only for functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4 Absolute Maximum Ratings Parameter Symbol Value Min. Max. Unit Note / Test Condition Power Dissipation must not exceed max-value Continuous Voltage at pin VBB VVBB -0.3 45 V Peak Voltage VBB, Overvoltage 500 ms VVBB -0.3 45 V Supply Voltage VCC VVCC -0.3 6.5 V Continuous Voltage at logic pins 1 - 24 (except VLOG VCC and GND pins) -0.3 6.5 V Continuous Voltage at pin TS -0.3 6.5 V Junction Temperature TJ -40 150 °C Storage Temperature TS -50 150 °C Power Dissipation Ptot 800 mW Input Voltage Range VIxH -45 45 V Input Voltage Range VIxL -0.3 5 V Error Pin Sink Current (ERR=0) IERRsink 5 mA Electrostatic discharge voltage (Human Body Model) according to JESD22-A114-B VESD – 2.5 kV Electrostatic discharge voltage (Charge Device Model) according to ESD STM5.3.1 - 1999 VESD – 1.5 kV Data Sheet 19 VERR < 0.25·VVCC Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics 5.2 Operating Conditions and Power Supply For proper operation of the device, absolute maximum rating (Section 4) and the parameter ranges in Table 5 must not be violated. Exceeding the limits of operating condition parameters may result in device malfunction or spec violations. The power supply pins VBB and VCC have the characteristics given in Table 7. Table 5 Operating Range Parameter at Tj = -40 ... 125°C Symbol Supply Voltage Logic VCC Value Unit Note / Test Condition Min. Max. VVCC 2.85 5.5 V related to GND Supply Voltage Senses VBB VVBB 9.6 35 V related to GNDBB Ambient Temperature TA -40 85 °C Junction Temperature TJ -40 125 °C Common Mode Transient dVISO/dt -25 25 kV/μs Magnetic Field Immunity |HIM| 30 A/m IEC61000-4-8 Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Limit Values Unit Note / Test Condition Thermal resistance junction - case top RthJC_Top 15.0 K/W measured on top side1) Thermal resistance junction - case bottom RthJC_Bot 13.8 K/W 1) Thermal resistance junction - pin RthJP 11.8 K/W 1) Thermal resistance @ 2 cm² cooling area2) (thermal conductance only by radiation and free convection) Rth(JA) 88.6 K/W 1) Table 6 Thermal Characteristics Min. Max. 1) not subject to production test, specified by design 2) Device on 50 mm x 50 mm x 1.5 mm epoxy PCB FR4 with 2 cm² (one layer, 35 µm thick) copper area. PCB is vertical without blow air. Table 7 Electrical Characteristics of the Power Supply Pins Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. VBB UVLO startup threshold VVBBon VBB UVLO shutdown threshold VVBBoff Typ. Unit Max. 9.6 8.0 Note / Test Condition V V VBB UVLO Hysteresis VVBBhys VBB missing voltage OFF (MV) threshold VVBBmvoff VBB missing voltage ON (MV) threshold VVBBmvon Glitch filters for VBB missing voltage and undervoltage TVBBfil 40 µs 1) Undervoltage Current for VBB IVBBuv 3.5 mA VVBB < VVBBon Data Sheet 1 V 13.9 12.1 V V 20 Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics Table 7 Electrical Characteristics of the Power Supply Pins (cont’d) Symbol Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Values Min. Typ. Unit Note / Test Condition Max. Quiescent Current VBB IVBBq 4.5 mA VVBB = 24 V, IINx = 0, VCC = 0V Startup Delay (time between VBBon/VCCon and ERR high) tERRstart 130 µs Digital Filter bypassed 1) Startup Delay (time between VBBon/VCCon and first data output) tVXXon 130 µs Digital Filter bypassed 1) VCC UVLO startup threshold VCC UVLO shutdown threshold VVCCon 2) VVCCoff 2.85 2.5 V V VCC UVLO threshold hysteresis VVCChys 0.1 V Quiescent Current VCC IVCCq 3.1 mA IVCCq 2.3 Quiescent Current VCC VVCC = 5 V, VVBB = 0V 1) mA VVCC = 3.3 V, VVBB = 0V 1) 1) valid for fscantyp = 100kHz 2) Note that the specified operation of the IC requires VVCC as given in Table 5 Data Sheet 21 Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics 5.3 Electrical Characteristics Input Side The electrical characteristics of the input side (pins 25-48) are given in Table 8. Note that some parameters refer to IN0 to IN7 which are nodes of external circuitry (see Figure 5 or Figure 13). Electrical characteristics with respect to these nodes are given for the system including the external circuitry and not for the IC alone. See also Figure 6 for the different threshold parameters. Table 8 Sensors Inputs Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Sink Current Limit at Saturation Edge Type 1/3 IINxsnkC13 Sink Current Limit at Saturation Edge Type 2 IINxsnkC2 Sink Current Limit at Maximum Input Voltage Type 1/3 IINxsnkM13 Sink Current Limit at Maximum Input Voltage Type 2 IINxsnkM2 LED Supply Current at Maximum Input Voltage, Type 1/3 IIxLmax LED Supply Current at Maximum Input Voltage, Type 2 Unit Note / Test Condition 2.3 mA VVBB=VVBBon, VINx=6.7V, VIxL=1.2V 3.3 mA VVBB=VVBBon, VINx=6.7V, VIxL=1.2V 3.4 mA VVBB=35V, VINx=30V, VIxL=2.5V 4.8 mA VVBB=35V, VINx=30V, VIxL=2.5V 2.1 3.1 mA VVBB=35V, VINx=30V, VIxL=2.5V IIxLmax 3.1 4.5 mA VVBB=35V, VINx=30V, VIxL=2.5V LED Supply Current at High Threshold Type 3 IIxL1 1.5 2.5 mA VVBB=VVBBon, VINx=11V, VIxL=2.5V LED Supply Current at High Threshold Type 2 IIxL2 2.3 3.6 mA VVBB=VVBBon, VINx=11V, VIxL=2.5V LED Supply Current at High Threshold Type 1 IIxL3 1.6 2.6 mA VVBB=VVBBon, VINx=15V, VIxL=2.5V LED Voltage VFLED 1.9 3.0 V 1) Sense Voltage Switching Threshold, L→H (Type 1) VINxDset(1) 15 V VVBB=24V VIxL=2.5V 2) Sense Voltage Switching Threshold H→L (Type 1) VINxDclr(1) V VVBB=24V VIxL=2.5V 2) Min. Hysteresis H↔L (Type 1) VINxDhys(1) Sense Voltage Switching Threshold L→H (Type 2) VINxDset(2) Sense Voltage Switching Threshold H→L (Type 2) VINxDclr(2) Hysteresis H↔L (Type 2) VINxDhys(2) Sense Voltage Switching Threshold L→H (Type 3) VINxDset(3) Sense Voltage Switching Threshold H→L (Type 3) VINxDclr(3) Data Sheet Values Typ. Max. 11 1 V 11 7 0.65 22 VVBB=24V VIxL=2.5V 2) V VVBB=24V VIxL=2.5V 2) V 11 7 V V VVBB=24V VIxL=2.5V 2) V VVBB=24V VIxL=2.5V 2) Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics Table 8 Sensors Inputs (cont’d) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Unit Max. Note / Test Condition Hysteresis H↔L (Type 3) VINxDhys(3) 0.7 V Input Sink Current when VVBB=0 IIxHq 300 µA VVBB=0V VIxH=30V, Ixl = open Unit Note / Test Condition 1) not subject to production test, specified by design; recommended for proper operation 2) clamped to 2.5V if “logic 1”, internally limited if logic “0” Table 9 Setting at the Configuration Pin TS Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Max. TS Pull-Down Resistance for Type RTSpd1 1 Selection 33 Ω 1) TS Pull-Down Resistance for Type RTSpd2 2 Selection 33 kΩ 2) 1) TS Pull-Down Resistance for Type RTSpd3 3 Selection 330 kΩ 1) pF 1) Max. TS Pin Load Capacitance CTSmax 20 1) required for operation 2) Only 4 channels can be used for this case. Data Sheet 23 Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics 5.4 Electrical Characteristics Microcontroller Interface Timing characteristics refer to CL < 50 pF and RL > 10 kΩ. Table 10 Sensor Scanning and Averaging Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Unit Note / Test Condition kHz 1) Max. Scan Frequency Range fscanrge Input Scan Propagation Delay tctdelay 40 µs applies equally to all channels 2) tbypass 10 µs 2) µs 2) Filter Bypass delay 50 150 refer to Figure 4 Input Scan Jitter Δtscan Input Scan Processing Delay tdelay 60 µs 2) Digital Filter Monitoring Time N=125D tFILT01 1.0 ms DS0=L, DS1=H 2) Digital Filter Monitoring Time N=400D tFILT02 3.2 ms DS0=H, DS1=L2) Digital Filter Monitoring Time N=1248D tFILT03 10.0 ms DS0=L, DS1=L 2) Digital Filter Monitoring Time Filter is Bypassed tFILToff 10 µs DS0=H, DS1=H 2) Unit Note / Test Condition kΩ E96 resistor 10 1) not subject to production test, specified by design 2) valid for fscantyp = 100kHz Table 11 Setting at the Configuration Pin (CLKADJ) see also Figure 4 Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. ROSC Resistance to GND ROSC ROSC Pin Regulated Voltage VROSCreg Typ. 73.2 Max. 221 1.2 Max. ROSC Pin Load Capacitance CROSCmax V 5 pF 1) 1) required for operation Data Sheet 24 Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics Table 12 Error Pin (ERR) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Error Pin Pull-Up Resistance (ERR=1) RERRpu ERR-Maximum Switching Frequency fSW Error Pin low voltage VERROL Typ. Unit Max. 50 10 Note / Test Condition kΩ 125 kHz 0.25·VVCC V 1) IFIOL = 5mA 1) not subject to production test, specified by design Table 13 Logical Pins (RD, DS0/1, CS, D7:D0, SCLK, SDO, SDI, SEL) Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Unit Max. Note / Test Condition Input Voltage High Level VIH 0.7·VVCC VVCC+0.3 V Input Voltage Low Level VIL -0.3 0.3·VVCC V Input Voltage Hysteresis VIhys Output Voltage High Level VOH 0.75·VVCC VVCC V IOH = 5mA Output Voltage Low Level VOL 0 0.25·VVCC V IOL = 5mA Table 14 100 mV Parallel Interface Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Unit Max. Input Pull Up Resistance (RD, CS) RPU Read Request Frequency fRD 0.061) 5 MHz Read Request Period (1/fRD) tRD 200 150002) ns 50 kΩ CS Setup time (falling edge of CS tCSS to falling edge of RD) 55 ns CS Disable time (minimum CS high time between two accesses) 35 µs tCSD Note / Test Condition D7:D0 Output disable time tfloat 80 ns D7:D0 Output Valid (by Read) tvalid 80 ns RD Low duration (by Read) tRDlow 100 ns Waiting Time for CS=RD=0 until transparent mode is entered tdirect 50 µs repeated read access during CS = low 1) 3) 1) Minimum value to ensure that the direct control mode is not entered, see also tRD and tdirect 2) After 50 µs the interface may enter the direct control mode, see also tdirect 3) not subject to production test, specified by design Data Sheet 25 Revision 2.0, 2012-06-14 ISO1I811T Electrical Characteristics Table 15 Serial Interface Parameter at Tj = -40 ... 125°C, Vbb=9.6...35V, VCC=2.85...5.5V, unless otherwise specified Symbol Values Min. Typ. Unit Max. Input Pull Up Resistance ( CS) RPU 50 kΩ Input Pull Down Resistance (SCLK, SDI) RPD 50 kΩ Serial Clock Frequency fSCLK Serial Clock Period (1/fSCLK) tSCLK 200 ns Serial Clock High Period tSCLKH 100 ns Serial Clock Low Period tSCLKL 100 ns Data setup time (required time SDI tSU to rising edge of SCLK) 5 ns Data hold time (rising edge of SCLK to SDI) 15 ns Minimum CS Hold time (rising tCSH edge of SCLK to rising edge of CS) 40 ns Minimum CS Disable time (CS high time between two accesses) tCSD 24 µs CS falling edge to SDO output valid time tCS_valid 50 ns CS falling edge to first rising SCLK tSCLK_su edge 80 ns SCLK falling edge to SDO output valid time tHD 5 tSCLK_valid Minimum SDO Output disable time tfloat 1) valid for fscantyp = 100kHz Data Sheet 26 Note / Test Condition MHz 80 ns 65 ns 1) Revision 2.0, 2012-06-14 ISO1I811T Package Outline Package Outline A2 6 A C A1 c O 0.10 L C D D B 0.20 C A-B D F3 F4 F2 E E1 Footprint F1 1 b 0.08 M C A-B D e A DOCUMENT NO. Z8B00158954 1) DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. DIM A A1 A2 b c D E E1 e N L Θ F1 F2 F3 F4 Figure 6-1 INCHES MILLIMETERS MAX 1.10 0.15 1.05 0.27 0.16 12.60 MIN 0.05 0.80 0.17 0.09 12.40 MIN 0.002 0.031 0.007 0.004 0.488 8.10 BSC 6.00 0.319 BSC 6.20 0.244 0.236 0.50 BSC 48 0.50 0° MAX 0.043 0.006 0.041 0.011 0.006 0.496 SCALE 0 1.0 0 1.0 2mm EUROPEAN PROJECTION 0.020 BSC 48 0.75 8° 0.020 0° 7.80 0.29 1.30 0.50 0.030 8° 0.307 0.011 0.051 0.020 ISSUE DATE 14.06.2011 REVISION 03 Package Outline TSSOP-48 (tie bar not drawn in outline) Notes 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Packages”: http://www.infineon.com/packages 2. Dimensions in mm. Data Sheet , 27 Revision 2.0, 2012-06-14 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG