HD74AC273 Octal D-Type Flip-Flop REJ03D0265–0200Z (Previous ADE-205-386 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flops’s Q output All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Features • Ideal Buffer for MOS Microprocessor or Memory • Eight Edge-Triggered D Flip-Flops • Buffered Common Clock • Buffered, Asynchronous Master Reset • See HD74AC373 for Transparent Latch Version • See HD74AC374 for 3-State Version • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC273P DIP-20 pin DP-20N P — HD74AC273FPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel) HD74AC273RPEL SOP-20 pin (JEDEC) FP-20DBV RP EL (1,000 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC273 Pin Arrangement MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 Gnd 10 11 CP (Top view) Logic Symbol D0 D1 D2 D3 D 4 D 5 D 6 D 7 CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Pin Names D0 – D 7 MR CP Q0 – Q 7 Data Inputs Master Reset Clock Pulse Input Data Outputs Rev.2.00, Jul.16.2004, page 2 of 7 HD74AC273 Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 CP D D Q Q D CP CP RD RD Q D CP Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q CP RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Mode Select-Truth Table Inputs MR Operating Mode Reset (Clear) L Load “1” Load “0” H H H : L : X : : Outputs CP Dn X Qn X L H L H L High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK –0.5 to 7 –20 V mA VI 20 –0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C VI = –0.5V Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Ta tr, tf –40 to +85 8 °C ns/V Rev.2.00, Jul.16.2004, page 3 of 7 Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC273 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Unit Maximum clock frequency fmax 3.3 5.0 90 140 125 175 — — 75 125 — — MHz Propagation delay Clock to output tPLH 3.3 5.0 1.0 1.0 7.0 5.5 12.5 9.0 1.0 1.0 14.0 10.0 ns Propagation delay Clock to output tPHL 3.3 5.0 1.0 1.0 7.0 5.0 13.0 10.0 1.0 1.0 14.5 11.0 ns Propagation delay MR to output tPHL 3.3 5.0 1.0 1.0 7.0 5.0 13.0 10.0 1.0 1.0 14.0 10.5 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 4 of 7 HD74AC273 AC Operating Requirements Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Symbol VCC (V)*1 Typ tsu 3.3 3.5 Data to CP Hold time, HIGH or LOW th 5.0 3.3 Data to CP Clock pulse width Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 6.0 ns Unit 2.5 –2.0 4.0 0.0 4.5 0.0 ns –1.0 3.5 1.0 5.5 1.0 6.0 ns tw 5.0 3.3 HIGH or LOW MR Pulse width tw 5.0 3.3 2.5 2.0 4.0 5.5 4.5 6.0 ns HIGH or LOW Recovery time trec 5.0 3.3 1.5 1.5 4.0 3.5 4.5 4.5 ns 5.0 1.0 2.0 3.0 MR to CP Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 5 of 7 Symbol CIN CPD Typ 4.5 50.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC273 Package Dimensions As of January, 2003 Unit: mm 24.50 25.40 Max 6.30 11 1 7.00 Max 20 10 2.54 ± 0.25 0.51 Min 1.27 Max 0.48 ± 0.10 2.54 Min 5.08 Max 1.30 0.89 7.62 + 0.11 0.25 – 0.05 0˚ – 15˚ Package Code JEDEC JEITA Mass (reference value) DP-20N — Conforms 1.26 g Unit: mm 24.50 25.40 Max 1 7.00 Max 11 6.30 20 10 1.30 2.54 ± 0.25 *0.48 ± 0.08 0.51 Min 1.27 Max 2.54 Min 5.08 Max 0.89 7.62 *0.25 ± 0.06 0˚ – 15˚ *NI/Pd/AU Plating Rev.2.00, Jul.16.2004, page 6 of 7 Package Code JEDEC JEITA Mass (reference value) DP-20NEV — Conforms 1.26 g HD74AC273 As of January, 2003 Unit: mm 12.6 13 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0˚ – 8 ˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 20 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-20DAV — Conforms 0.31 g As of January, 2003 Unit: mm 12.8 13.2 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 ± 0.10 0.935 Max *0.25 ± 0.05 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0˚ – 8˚ 0.57 0.70 +– 0.30 0.15 0.12 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 7 of 7 Package Code JEDEC JEITA Mass (reference value) FP-20DBV Conforms — 0.52 g Sales Strategic Planning Div. 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