RENESAS HD74LS156P

HD74LS156
Dual 2-line-to-4-line Decoders / Demultiplexers
(with open collector outputs)
REJ03D0441–0300
Rev.3.00
Jul.13.2005
This circuit features dual 1-line-to-4-line demultiprexer with individual strobes and common binary-address input.
When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route
associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting
each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following
the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS156P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
—
HD74LS156RPEL
SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
FP
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Data 1C
1
16
VCC
Strobe 1G
2
15
Data 2C
Select Input B
3
14
Strobe 2G
1Y3
4
1Y3 1G
1C
13
Select Input A
1Y2
5
1Y2
2G 2Y3
2C
12
2Y3
1Y1
6
1Y1
2Y2
11
2Y2
1Y0
7
1Y0
2Y1
10
2Y1
GND
8
2Y0
9
2Y0
Outputs
B
B
A
A
B
B
A
A
(Top view)
Rev.3.00, Jul.13.2005, page 1 of 6
Outputs
HD74LS156
Function Table
• 2-to-4-line Decoder / 1-to-4-line Demultiplexer
Inputs
Select
B
X
L
L
H
H
X
A
X
L
H
L
H
X
Outputs
Strobe
1G
H
L
L
L
L
X
Data
1C
X
H
H
H
H
L
Data
2C
X
L
L
L
L
H
1Y0
1Y1
1Y2
1Y3
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
Inputs
Select
Outputs
B
X
L
L
H
A
X
L
H
L
Strobe
2G
H
L
L
L
H
X
H
X
L
X
2Y0
2Y1
2Y2
2Y3
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
• 3-to-8-line Decoder / 1-to-8-line Demultiplexer
Inputs
Strobe or
Select
(0)
Data
C*1
B
A
G*2
2Y0
X
X
X
H
H
L
L
L
L
L
L
L
H
L
H
L
H
L
L
H
L
H
H
L
H
H
L
L
L
H
H
L
H
L
H
H
H
L
L
H
H
H
H
L
H
Notes: 1. C; input 1C and 2C connected together
2. G; inputs 1G and 2G connected together
3. H; high level, L; low level, X; irrelevant
Rev.3.00, Jul.13.2005, page 2 of 6
Outputs
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2Y1
H
H
L
H
H
H
H
H
H
2Y2
H
H
H
L
H
H
H
H
H
2Y3
H
H
H
H
L
H
H
H
H
1Y0
H
H
H
H
H
L
H
H
H
1Y1
H
H
H
H
H
H
L
H
H
1Y2
H
H
H
H
H
H
H
L
H
1Y3
H
H
H
H
H
H
H
H
L
HD74LS156
Block Diagram
Strobe
1G
1Y0
Data
1C
1Y1
Select
B
1Y2
1Y3
Outputs
2Y0
Select
A
Data
2C
2Y1
2Y2
Strobe
2G
2Y3
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VCC
7
V
Input voltage
VIN
7
V
PT
400
mW
Tstg
–65 to +150
°C
Power dissipation
Storage temperature
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.75
5.00
5.25
V
High level output voltage
VOH
—
—
5.5
V
Low level output current
IOL
—
—
8
mA
Operating temperature
Topr
–20
25
75
°C
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Symbol
VIH
VIL
min.
2.0
—
typ.*
—
—
max.
—
0.8
Unit
V
V
Output current
IOH
—
—
100
µA
Output voltage
VOL
—
—
—
—
—
—
—
—
—
—
—
—
6.1
—
0.4
0.5
20
–0.4
0.1
10
–1.5
Input voltage
Input current
IIH
IIL
II
V
µA
mA
mA
mA
V
Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
VOH = 5.5V
IOL = 4 mA
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IOL = 8 mA
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
VCC = 5.25 V, VI = 7 V
VCC = 5.25 V
VCC = 4.75 V, IIN = –18 mA
Supply current**
ICC
Input clamp voltage
VIK
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded.
Rev.3.00, Jul.13.2005, page 3 of 6
HD74LS156
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Propagation
delay time
Symbol
Inputs
Output
Level of
logic
min.
typ.
max.
tPLH
A, B, 2C,
1G or 2G
Y
2
—
25
40
Y
2
—
34
51
Y
Y
Y
Y
3
3
3
3
—
—
—
—
31
34
32
32
46
51
48
48
tPHL
tPLH
tPHL
tPLH
tPHL
A, B, 2C,
1G or 2G
A or B
A or B
1C
1C
Unit
ns
Testing Method
Test Circuit
VCC
4.5V
Input
P.G.
Zout = 50Ω
See Testing Table
1Y0
1G
1Y1
1C
1Y2
B
1Y3
A
2Y0
2C
2Y1
2G
2Y2
2Y3
Note:
CL includes probe and jig capacitance.
Rev.3.00, Jul.13.2005, page 4 of 6
RL
Output
CL
Condition
CL = 15 pF,
RL = 2 kΩ
HD74LS156
Waveform
tTLH
tTHL
90%
1.3 V
Input
3V
90%
1.3 V
10%
10%
0V
tPHL
tPLH
VOH
In phase output
1.3 V
1.3 V
VOL
tPHL
tPLH
VOH
Out of phase output
1.3 V
1.3 V
VOL
Note:
Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
Rev.3.00, Jul.13.2005, page 5 of 6
HD74LS156
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
MASS[Typ.]
1.05g
Previous Code
DP-16FV
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
c
e1
D
19.2
E
6.3
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.15g
D
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
θ
bp
e
Dimension in Millimeters
Min
9
c
*2
Index mark
HE
E
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
9.90
10.30
E
3.95
A2
8
1
Z
e
*3
bp
x
A1
0.10
0.14
0.25
0.34
0.40
0.46
0.15
0.20
0.25
6.10
6.20
1.75
A
M
L1
bp
b1
c
A
c
A1
θ
L
y
Detail F
1
θ
0°
HE
5.80
e
1.27
x
0.25
y
0.15
0.635
Z
0.40
L
L
Rev.3.00, Jul.13.2005, page 6 of 6
8°
1
0.60
1.08
1.27
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