LSI/CSI UL ® RDD 104 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 SELECTABLE 4 DECADE CMOS DIVIDER PIN ASSIGNMENT - TOP VIEW 1 DIVIDER SELECT-2 2 V SS (-V) 3 RESET 4 RDD 104 DIVIDER SELECT-1 LSI FEATURES: • Selectable Divide by 10 or 100 or 1,000 or 10,000 • Clock Input Shaping Network Accepts Fast or Slow Edge Inputs • Active Oscillator Network for External Crystal • Square Wave Output • Output TTL Compatible at +4.5V Operation • High Noise Immunity • Reset • All Inputs Protected • +4.5V to +15V Operation (VDD-VSS) • Low Power Dissipaton • RDD104 (DIP); RDD104-S (SOIC) - See Figure 1 January 2003 8 V DD (+V) 7 OUTPUT 6 CLOCK OUTPUT 5 CLOCK INPUT FIGURE 1 DESCRIPTION OF OPERATION: The RDD104 is a CMOS four decade MAXIMUM RATINGS: divider circuit that advances on each negative PARAMETER SYMBOL VALUE UNIT transition of the input clock pulse. When the reset Storage Temperature T STG -65 to +150 °C input is high the circuit is cleared to zero. The Operating Temperature T A -40 to +85 °C clock input is applied to a three stage inverting DC Supply Voltage (VDD - VSS) +18 V amplifier network whose output is brought out so Voltage at any input V IN V SS 0.5 to V DD + 0.5 V that an external crystal network can be used to form an oscillator circuit. If the clock output is not used,the amplifier acts as an input buffer. Two DC ELECTRICAL CHARACTERISTICS: select inputs are provided which enables the circuit (All voltages referenced to Vss) VDD -40°C +25°C +85°C UNIT to divide by 10, 100, 1,000 or 10,000. The Output Division is selected according to the following truth table: DIVIDER SELECT INPUTS: SELECT 2 SELECT 1 0 0 0 1 1 0 1 1 OUTPUT DIVISION 10,000 1,000 100 10 The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. RDD104-012703-1 Quiescent Device Current 4.5V 10V 10 20 10 20 300 600 uA Max uA Max Output Voltage, Low Level 4.5V 10V 4.5V 10V 0.01 0.01 4.49 9.99 0.01 0.01 4.49 9.99 0.05 0.05 4.45 9.95 V Min V Min V Max V Max Input Noise Immunity (Low and High) 4.5V 10V 1.3 3.0 1.3 3.0 1.3 3.0 V Min V Min Output Drive Current: N-Channel Sink Current (VOUT = Vss + 0.4V) 4.5V 10V High Level P-Channel Source Current (VOUT = VDD - 1V) Input Capacitance (any input) 4.5V 10V 2.3 5.0 1.9 4.0 1.1 2.5 0.95 2.1 5.0 1.6 3.5 0.8 1.8 mA Min mA Min mA Min mA Min pF Max PIN 5 DYNAMIC ELECTRICAL CHARACTERISTICS: (CL = 50pF, Input Rise and Fall Times = 20ns except for Clock, unless otherwise specified.) VDD MIN MAX Clock Input Frequency 4.5V 0 1.5 10V 0 4.0 15V 0 6.0 UNIT MHz MHz MHz Clock Input Rise & Fall Times 4.5 to 15V - Clock Input Rise & Fall Time, CL = 15pF 4.5V 10V - 140 70 ns ns Clock Output Propagation Delay, CL = 15pF 4.5V 10V - 300 150 ns ns Output Rise & Fall Times 4.5V 10V - 400 200 ns ns Propagation Delay to Output 4.5V 10V - 1500 750 ns ns Reset Pulse Width 4.5V 10V 800 400 - ns ns Reset Removal Time 4.5V 10V - 500 250 ns ns Reset Propagation Delay to Output 4.5V 10V - 1400 700 ns ns Select Input Setup Time 4.5V 10V - 800 400 ns ns 10M PIN 6 No Limit FIGURE 2. MINIMUM PARTS OSCILLATOR CIRCUIT PIN 5 100pF 20M 10M 40pF PIN 6 FIGURE 3. TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW PIN 5 50pF 10M 20pF 39pF 56pF PIN 6 FIGURE 4. TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ V DD V DD FIGURE 5. TYPICAL INPUT If input signals are less than VSS or greater than VDD, a series input resistor, R1, should be used to limit the maximum input current to 2 milliamperes. R1 CLOCK INPUT SIGNAL 5 V SS 3 STAGE INVERTING AMPLIFIER 5 CLOCK IN OSCILLATOR EXTERNAL COMPONENTS RDD 104 BLOCK DIAGRAM CLOCK GENERATOR R 8 V DD -V 3 V SS ÷ 10 ÷ 10 ÷ 10 ÷ 10 6 CLOCK OUT RESET 4 DIVIDER SELECT-1 1 DIVIDER SELECT-2 2 DECODER RDD104-012703-2 +V FIGURE 6. 1 OUT OF 4 SELECTOR BUFFER 7 OUTPUT