RENESAS 2SK2788

2SK2788
Silicon N Channel MOS FET
High Speed Power Switching
REJ03G1033-0200
(Previous: ADE-208-538)
Rev.2.00
Sep.07,2005
Features
• Low on-resistance
RDS(on) = 0.12 Ω typ (VGS = 10 V, ID = 1 A)
• Low drive current
• High speed switching
• 4 V gate drive devices.
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK R )
3
D
2 1
1. Gate
2. Drain
3. Source
4. Drain
G
4
S
Note:
Marking is “VY”
*UPAK is a trademark of Renesas Technology Corp.
Rev.2.00 Sep. 07, 2005 page 1 of 6
2SK2788
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Drain to source voltage
VDSS
Gate to source voltage
VGSS
Drain current
ID
Drain peak current
ID(pulse)*1
Body to drain diode reverse drain current
IDR
Channel dissipation
Pch*2
Channel temperature
Tch
Storage temperature
Tstg
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1 %
2. When using the alumina ceramic board (12.5 x 20 x 0.7 mm)
Ratings
60
±20
2
4
2
1
150
–55 to +150
Unit
V
V
A
A
A
W
°C
°C
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Static drain to source on state
resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body to drain diode forward voltage
Body to drain diode reverse
recovery time
Notes: 3. Pulse test
Rev.2.00 Sep. 07, 2005 page 2 of 6
Symbol
V(BR)DSS
V(BR)GSS
Min
60
±20
Typ
—
—
Max
—
—
Unit
V
V
IDSS
IGSS
VGS(off)
RDS(on)
—
—
1.0
—
—
1.6
—
—
—
—
—
—
—
—
—
—
—
—
0.12
0.16
2.8
180
90
30
9
15
40
35
0.9
35
10
±10
2.0
0.16
0.25
—
—
—
—
—
—
—
—
—
—
µA
µA
V
Ω
Ω
S
pF
pF
pF
ns
ns
ns
ns
V
ns
RDS(on)
|yfs|
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
VDF
trr
Test Conditions
ID = 10 mA, VGS = 0
IG = ±100 µA, VDS = 0
VDS = 60 V, VGS = 0
VGS = ±16 V, VDS = 0
ID = 1 mA, VDS = 10 V
ID = 1 A, VGS = 10 V*3
ID = 1 A, VGS = 4 V*3
ID = 1 A, VDS = 10 V*3
VDS = 10 V, VGS = 0,
f = 1 MHz
VGS = 10 V, ID = 1 A,
RL = 30 Ω
ID = 2 A, VGS = 0
IF = 2 A, VGS = 0
diF/ dt = 50A/µs
2SK2788
Main Characteristics
Maximum Safe Operation Area
Power vs. Temperature Derating
10
=
s
s
(1
sh
ot
n
tio
)
c
(T
=
25
0.3 Operation in
this area is
0.1 limited by RDS(on)
m
m
ra
°C
)
50
100
150
0.01 Ta = 25°C
0.1 0.3
1
200
3
10
Typical Output Characteristics
Typical Transfer Characteristics
5
Drain Current ID (A)
Pulse Test
3V
3
2
2.5 V
1
4
3
Tc = 75°C
2
–25°C
25°C
1
VDS = 10 V
Pulse Test
VGS = 2 V
2
4
6
8
0
10
2
4
6
8
10
Gate to Source Voltage VGS (V)
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
Static Drain to Source on State
Resistance vs. Drain Current
Pulse Test
1.6
1.2
0.8
0.4
ID = 2 A
1A
2
4
6
8
10
Gate to Source Voltage VGS (V)
Rev.2.00 Sep. 07, 2005 page 3 of 6
Static Drain to Source on State Resistance
RDS (on) (Ω)
Drain to Source Voltage VDS (V)
2.0
0
100
Drain to Source Voltage VDS (V)
6V 5V
4V
10 V
4
3.5 V
0
30
Ambient Temperature Ta (°C)
5
Drain to Source Saturation Voltage
VDS (on) (V)
1
10
0.03
0
Drain Current ID (A)
1
pe
0.5
PW
O
1.0
3
C
Drain Current ID (A)
1.5
100 µs
Test condition :
When using the alumina ceramic
board (12.5 x 20 x 0.7 mm)
D
Channel Dissipation Pch (W)
2.0
5
Pulse Test
2
1
0.5
VGS = 4 V
0.2
0.1
0.05
0.1
10 V
0.3
1
3
10
30
Drain Current ID (A)
100
Forward Transfer Admittance
vs. Drain Current
Static Drain to Source on State
Resistance vs. Temperature
Forward Transfer Admittance yfs (S)
Static Drain to Source on State Resistance
RDS (on) (Ω)
2SK2788
0.5
Pulse Test
0.4
1A
2A
0.3
VGS = 4 V
0.2
1, 2 A
0.1
10 V
0
–40
0
40
80
120
160
25°C
2
75°C
1
0.5
0.2
0.1
0.1
VDS = 10 V
Pulse Test
0.5
0.2
1
2
5
Drain Current ID (A)
Body to Drain Diode Reverse
Recovery Time
Typical Capacitance
vs. Drain to Source Voltage
10
1000
VGS = 0
f = 1 MHz
500
Capacitance C (pF)
200
100
50
20
10
100
0.2
1
5
Coss
50
Crss
0
10
10
20
30
40
Drain to Source Voltage VDS (V)
Dynamic Input Characteristics
Switching Characteristics
20
ID = 2 A
VDD = 10 V
25 V
50 V
16
12
VDS
VGS
40
20
0
2
100
Reverse Drain Current IDR (A)
80
60
0.5
Ciss
10
8
4
VDD = 50 V
25 V
10 V
2
4
6
8
Gate Charge Qg (nc)
Rev.2.00 Sep. 07, 2005 page 4 of 6
0
10
50
100
Switching Time t (ns)
5
0.1
200
20
di / dt = 50 A / µs
VGS = 0, Ta = 25°C
Gate to Source Voltage VGS (V)
Reverse Recovery Time trr (ns)
Tc = –25°C
5
Case Temperature TC (°C)
500
Drain to Source Voltage VDS (V)
10
td(off)
50
tf
20
tr
td(on)
10
5
VGS = 10 V, VDD = 30 V
PW = 5 µs, duty < 1 %
2
1
0.1
0.2
0.5
1
2
Drain Current ID (A)
5
10
2SK2788
Reverse Drain Current vs.
Source to Drain Voltage
Reverse Drain Current IDR (A)
10
8
6
10 V
4
5V
VGS = 0, –5 V
2
Pulse Test
0
0.4
0.8
1.2
Source to Drain Voltage
1.6
2.0
VSD (V)
Switching Time Test Circuit
Waveform
90%
Vout
Monitor
Vin Monitor
D.U.T.
RL
Vin
Vout
Vin
10 V
50 Ω
VDD
= 30 V
10%
10%
90%
td(on)
Rev.2.00 Sep. 07, 2005 page 5 of 6
10%
tr
90%
td(off)
tf
2SK2788
Package Dimensions
RENESAS Code
Package Name
MASS[Typ.]
PLZZ0004CA-A
UPAK / UPAKV
0.050g
1.5 1.5
3.0
1.5 ± 0.1
0.44 Max
2.5 ± 0.1
4.25 Max
(1.5)
0.44 Max
(0.2)
0.53 Max
0.48 Max
0.8 Min
φ1
0.4
4.5 ± 0.1
1.8 Max
Unit: mm
(2.5)
SC-62
(0.4)
JEITA Package Code
Ordering Information
Part Name
2SK2788VYTL-E
2SK2788VYTR-E
Quantity
1000 pcs
1000 pcs
Shipping Container
Taping
Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.2.00 Sep. 07, 2005 page 6 of 6
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Colophon .3.0