SD-SST210/214 N-CHANNEL LATERAL DMOS SWITCH PRODUCT SUMMARY PART NUMBER V(BR)DS Min (V) V(GS)th Max (V) rDS(on) Max (Ω) C rss Max (pF) tON Max (ns) SD210DE 30 1.5 45 @ VGS=10V 0.5 2 SD214DE 20 1.5 45 @ VGS=10V 0.5 2 SST210 30 1.5 50 @ VGS=10V 0.5 2 SST214 20 1.5 50 @ VGS=10V 0.5 2 Features Benefits Applications • Ultra-High Speed Switching—tON: 1ns • Ultra-Low Reverse Capacitance: 0.2pF • Low Guaranteed rDS @5V • Low Turn-On Threshold Voltage • N-Channel Enhancement Mode • High-Speed System Performance • Low Insertion Loss at High Frequencies • Low Transfer Signal Loss • Simple Driver Requirement • Single Supply Operation • Fast Analog Switch • Fast Sample-and-Holds • Pixel-Rate Switching • DAC Deglitchers • High-Speed Driver Description The SD210DE/214 and SST210/214 are enhancement-mode MOSFETs designed for high speed low-glitch switching in audio, video and high-frequency applications. The SD214DE and SST214 are normally used for ±10-V analog switching. These MOSFETs utilize lateral construction to achieve low capacitance and ultra-fast switching speeds. These MOSFETs do not have a gate protection Zener diode which results in lower gate leakage and ± voltage capability from gate to substrate. A polysilicon gate is featured for manufacturing reliability. For similar products see: quad array—SD5000/5400 series, Zener protected—SD211DE/SST211 Series. Top Views Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201114 04/07/2014 Rev#A11 ECN# SD210DE_214DE Absolute Maximum Ratings (TA = 25°C unless otherwise noted) Gate-Drain, Gate-Source Voltage Gate-Substrate Voltage Drain-Source Voltage Source-Drain Voltage Drain-Substrate Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 40V . . . . . . . . . . . . . . . . . . . . . . . ± 30V (SD210DE/SST210) . . . . . . . . 30V (SD214DE/SST214) . . . . . . . . 20V (SD210DE/SST210) . . . . . . . . 10V (SD214DE/SST214) . . . . . . . . 20V (SD210DESST210) . . . . . . . . 30V (SD214DE/SST214) . . . . . . . . 25V Source-Substrate Voltage Drain Current Lead Temperature (1/16” from ease for 10 seconds) Storage Temperature Operating Junction Temperature Power Dissipation* (SD210DE/SST210) . . . . . . . . 15V (SD210DE/SST210) . . . . . . . . 25V . . . . . . . . . . . . . . . . . . . . . . . .50mA . . . . . . . . . . . . . . . . . . . . . . . 300°C . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . . . -55 to 125°C . . . . . . . . . . . . . . . . . . . . . .300mW Note: * Derate 3mW/°C above 25°C Specificationsa LIMITS PARAMETER SYMBOL TEST CONDITIONS TYP V(BR)DS VGS = VBS = 0V, ID = 10 µA VGS = VBS = -5V, ID = 10 nA V(BR)SD VGD = VBD = -5V, IS = 10 nA Static Drain - Source Breakdown Voltage Source - Drain Breakdown Voltage Drain - Substrate Breakdown Voltage V(BR)DBO Source - Substrate Breakdown Voltage V(BR)SBO Drain – Source Leakage IDS(off) Source - Drain Leakage ISD(off) Gate Leakage IGBS Threshold Voltage Drain – Source On-Resistance VGS(th) rDS(on) VGB = 0V, ID= 10 nA Source Open VGB = 0V, Is = 10 µA Drain Open VDS = 10V VGS = VBS = -5V VDS = 20V VSD = 10V VGD = VBD = -5V VSD = 20V VDB = VSB = 0V, VGB = ±40V VDS = VGS, ID = 1 µA , VSB = 0V VGS = 5V (SD Series) VGS = 5V (SST Series) VGS = 10V (SD Series) VSB = 0V VGS = 10V ID = 1mA (SST Series) Linear Integrated Systems 210 Series Min Max 214 Series Min Max 35 30 30 10 20 22 10 20 35 15 25 35 15 25 V 0.4 0.9 0.5 10 ±0.001 ±100 0.8 10 nA 10 ±100 pA 1.5 V 10 0.5 1.5 0.1 58 70 70 60 75 75 38 45 45 40 50 50 VGS = 15V 30 VGS = 20V 26 VGS = 25V 24 • UNIT Ω 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201114 04/07/2014 Rev#A11 ECN# SD210DE_214DE Specificationsa LIMITS PARAMETER SYMBOLb TEST CONDITIONSb TYPc 210 Series Min Max 214 Series Min Max 11 10.5 0.9 10 9 10 9 UNIT Dynamic Forward Transconductance Gate Node Capacitance Drain Node Capacitance Source Node Capacitance Reverse Transfer Capacitance gfs gos SD Series SST Series All VDS = 10V, VSB = 0V, ID = 20mA, f = 1kHz C(GS+GD+GB) C(GD+DB) C(GS+SB) SD Series VDS = 10V, f = 1MHz VGS = VBS = -15V Crss mS 2.5 3.5 3.5 1.1 1.5 1.5 3.7 5.5 5.5 SST Series 4.2 SD Series 0.2 0.5 0.5 0.5 0.6 2 6 1 1 1 1 pF Switching Turn-On Time Turn-Off Time tD(on) tr tD (off) tf SD Series Only VSB = 0V, VIN 0 to 5V, RG = 25Ω VDD = 5V, RL = 680Ω ns NOTES a. TA = 25°C unless otherwise notes. b. B is the body (substrate) and V(BR) is breakdown voltage. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Switching Time Test Circuit Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201114 04/07/2014 Rev#A11 ECN# SD210DE_214DE