LSJ74, SST74 ULTRA LOW NOISE SINGLE P-CHANNEL JFET FEATURES ULTRA LOW NOISE (f = 1kHz) en = 0.9nV/√Hz HIGH GAIN Gfs = 22mS (typ) HIGH INPUT IMPEDANCE IG = 1.0nA LOW CAPACITANCE CRSS = 32pF ABSOLUTE MAXIMUM RATINGS @ 25 °C (unless otherwise stated) SOT-89 TOP VIEW TO 92 TOP VIEW IMPROVED SECOND SOURCE REPLACEMENT FOR 2SJ74 1 Maximum Temperatures Storage Temperature -55 to +150°C Junction Operating Temperature -55 to +135°C Maximum Power Dissipation Continuous Power Dissipation 400mW Maximum Currents Gate Forward Current IG(F) = -10mA Maximum Voltages * For equivalent N-Channel, see LSK170 family. Gate to Drain Voltage VGDS = 25V Gate to Source Voltage VGSS = 25V ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise stated) SYMBOL CHARACTERISTIC MIN TYP MAX BVGDS Gate to Drain Breakdown Voltage 25 VGS(OFF) Gate to Source Pinch-off Voltage 0.15 2 -2.6 -6.5 LSJ74B -6 -12 LSJ74C -10 -20 LSJ74D -17 LSJ74A IDSS IG Drain to Source Saturation Current2 Gate Operating Current IGSS Gate to Source Leakage Current Gfss Full Conductance Transconductance en 1 22 0.9 1.9 2.5 4 Noise Voltage VDS = 0V, IG = 100µA VDS = -10V, ID = -0.1µA mA VDG = -10V, VGS = 0V pA VDG = -10V, ID = -1mA nA VGS = 25V, VDS = 0V mS VDG = -10V, VGS = 0V, f = 1kHz nV/√Hz CISS Common Source Input Capacitance 105 CRSS Common Source Reverse Transfer Cap. 32 Linear Integrated Systems V CONDITIONS -30 50 8 UNITS pF VDS = -10V, ID = -2mA, f = 1kHz, NBW = 1Hz VDS = -10V, ID = -2mA, f = 10kHz, NBW = 1Hz VDS = -10V, VGS = 0V, f = 1MHz VDS = -10V, ID = 0A, f = 1MHz • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201175 06/26/2014 Rev#A4 ECN# LSJ74 TO-92 SOT-89 Dimensions in millimeters Dimensions in inches NOTES: 1. Absolute maximum ratings are limiting values above which serviceability may be impaired. 2. Pulse test: PW ≤ 300 µS, Duty Cycle ≤ 3%. 3. All MIN/TYP/MAX Limits are absolute values. Negative signs indicate negative electrical polarity only. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201175 06/26/2014 Rev#A4 ECN# LSJ74