R1LV0416D Series 4M SRAM (256-kword × 16-bit) REJ03C0311-0100 Rev.1.00 May.24.2007 Description The R1LV0416D is a 4-Mbit static RAM organized 256-kword × 16-bit, fabricated by Renesas's high-performance 0.15µm CMOS and TFT technologies. R1LV0416D Series has realized higher density, higher performance and low power consumption. The R1LV0416D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. The R1LV0416D Series is packaged in a 44-pin thin small outline mount device, or a 48-ball fine pitch ball grid array. Features • Single 3.0 V supply: 2.7 V to 3.6 V • Fast access time: 55/70 ns (max) • Power dissipation: Standby: 3 µW (typ) (VCC = 3.0 V) • Equal access and cycle times • Common data input and output. Three state output • Battery backup operation. 2 chip selection for battery backup • Temperature Range: -40 to +85°C Rev.1.00, May.24.2007, page 1 of 15 R1LV0416D Series Ordering Information Type No. Access time Package R1LV0416DSB-5SI 55 ns 400-mil 44-pin plastic TSOP II R1LV0416DSB-7LI 70 ns PTSB0044GA-A (44P3W-H) R1LV0416DBG-5SI 55 ns 48-ball CSP with 0.75 mm ball pitch R1LV0416DBG-7LI 70 ns PTBG0048HB-A (48FHH) Rev.1.00, May.24.2007, page 2 of 15 R1LV0416D Series Pin Arrangement 48-ball CSP 44-pin TSOP A4 A3 A2 A1 A0 CS1# I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE# UB# LB# I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 (Top view) 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B I/O8 UB# A3 A4 CS1# I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE# I/O7 H NC A8 A9 A10 A11 NC (Top view) Pin Description Pin name 1 Function A0 to A17 Address input I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 OE# (OE) Output enable WE# (WE) Write enable LB# (LB) Lower byte select UB# (UB) Upper byte select VCC Power supply VSS Ground NC No connection Rev.1.00, May.24.2007, page 3 of 15 R1LV0416D Series Block Diagram LSB A13 V CC A7 A8 V SS A9 A10 A11 A12 A6 MSB Row decoder • • • • • Memory matrix 2,048 x 2,048 A14 A15 A16 I/O0 Column I/O • • Input data control Column decoder I/O15 LSB A0 A1 A2 A3 A4 A5 A17 MSB • • CS2 CS1# LB# UB# WE# OE# Rev.1.00, May.24.2007, page 4 of 15 Control logic • • R1LV0416D Series Operation Table CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS VCC −0.5 to +4.6 V Terminal voltage on any pin relative to VSS VT −0.5*1 to VCC + 0.3*2 V Power dissipation PT 0.7 W Operating temperature1 Topr −40 to +85 °C Storage temperature range Tstg −65 to +150 °C Storage temperature range under bias Tbias −40 to +85 °C Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Supply voltage Symbol Min Typ Max Unit VCC 2.7 3.0 3.6 V VSS 0 0 0 V Input high voltage VIH 2.2 VCC + 0.3 V Input low voltage VIL −0.3 0.6 V Ambient temperature range Ta −40 +85 °C Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Rev.1.00, May.24.2007, page 5 of 15 Note 1 R1LV0416D Series DC Characteristics Parameter Symbol Min Typ Max Unit Test conditions Input leakage current |ILI| 1 µA Vin = VSS to VCC Output leakage current |ILO| 1 µA CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Operating current ICC 20 mA CS1# = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA Average operating current ICC1 25 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL ICC2 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1# ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V ISB 0.1*1 0.3 mA CS2 = VIL to +85°C ISB1 10 µA Vin ≥ 0 V to +70°C ISB1 8 µA (1) 0 V ≤ CS2 ≤ 0.2 V or to +40°C ISB1 3 µA (2) CS1# ≥ VCC − 0.2 V, to +25°C ISB1 1* 2.5 µA CS2 ≥ VCC − 0.2 V or to +85°C ISB1 20 µA to +70°C ISB1 16 µA to +40°C ISB1 10 µA ISB1 1* VOH 2.4 VOH2 Standby current Standby current −5SI −7LI (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V 10 µA Average values — — V IOH = −1 mA VCC − 0.2 — — V IOH = −100 µA VOL — — 0.4 V IOL = 2 mA VOL2 — — 0.2 V IOL = 100 µA to +25°C Output high voltage Output low voltage Note: 1 1 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Symbol Min Typ Max Unit Test conditions Note Input capacitance Parameter Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.1.00, May.24.2007, page 6 of 15 R1LV0416D Series AC Characteristics (Ta = -40 to +85°C, VCC = 2.7 V to 3.6 V) Test Conditions Input pulse levels: VIL = 0.4 V, VIH = 2.4 V • Input rise and fall time: 5 ns • Input/output timing reference levels: 1.4 V • Output load: See figures (Including scope and jig) 1.4 V RL=500 Ω Dout 50pF Output load Rev.1.00, May.24.2007, page 7 of 15 R1LV0416D Series Read Cycle R1LV0416D -5SI Parameter -7LI Symbol Min Max Min Max Unit Read cycle time tRC 55 70 ns Address access time tAA 55 70 ns tACS1 55 70 ns tACS2 55 70 ns Output enable to output valid tOE 35 40 ns Output hold from address change tOH 10 10 ns LB#, UB# access time tBA 55 70 ns Chip select to output in low-Z tCLZ1 10 10 ns 2, 3 tCLZ2 10 10 ns 2, 3 tBLZ 5 5 ns 2, 3 Chip select access time LB#, UB# disable to low-Z Notes Output enable to output in low-Z tOLZ 5 5 ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 20 0 25 ns 1, 2, 3 tCHZ2 0 20 0 25 ns 1, 2, 3 LB#, UB# disable to high-Z tBHZ 0 20 0 25 ns 1, 2, 3 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3 Rev.1.00, May.24.2007, page 8 of 15 R1LV0416D Series Write Cycle R1LV0416D -5SI Parameter -7LI Symbol Min Max Min Max Unit Notes Write cycle time tWC 55 70 ns Address valid to end of write tAW 50 60 ns Chip selection to end of write tCW 50 60 ns 5 Write pulse width tWP 40 50 ns 4 LB#, UB# valid to end of write tBW 50 55 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 30 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3 Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.1.00, May.24.2007, page 9 of 15 R1LV0416D Series Timing Waveform Read Timing Waveform (WE# = VIH) t RC Address Valid address tAA tACS1 CS1# tCLZ1*2, 3 CS2 tCHZ1*1, 2, 3 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB#, UB# tBLZ*2, 3 tOHZ*1, 2, 3 tOE OE# tOLZ*2, 3 Dout High impedance Rev.1.00, May.24.2007, page 10 of 15 tOH Valid data R1LV0416D Series Write Timing Waveform (1) (WE# Clock) tWC Valid address Address tWR*7 tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tAW tWP*4 WE# tAS*6 tDW tDH Valid data Din tWHZ*1, 2 tOW*2 High impedance Dout Rev.1.00, May.24.2007, page 11 of 15 R1LV0416D Series Write Timing Waveform (2) (CS# Clock, OE# = VIH) tWC Valid address Address tAW tAS *6 tWR*7 tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tWP*4 WE# tDW Valid data Din High impedance Dout Rev.1.00, May.24.2007, page 12 of 15 tDH R1LV0416D Series Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH) tWC Valid address Address tAW tCW*5 tWR*7 CS1# tCW*5 CS2 tAS*6 tBW LB#, UB# tWP*4 WE# tDW Valid data Din High impedance Dout Rev.1.00, May.24.2007, page 13 of 15 tDH R1LV0416D Series Low VCC Data Retention Characteristics (Ta = -40 to +85°C) Parameter Symbol Min Typ Max Unit VDR 2.0 V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V ICCDR 10 µA to +70°C ICCDR 8 µA to +40°C ICCDR 3 µA to +25°C ICCDR 1* 2.5 µA to +85°C ICCDR 20 µA to +70°C ICCDR 16 µA VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V Average values to +40°C ICCDR 10 µA ICCDR 1* 10 µA tCDR 0 ns tR 5 ms VCC for data retention Data retention current −5SI −7LI to +85°C to +25°C Chip deselect to data retention time Operation recovery time Note: 1 1 Test conditions See retention waveform 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Rev.1.00, May.24.2007, page 14 of 15 R1LV0416D Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) t CDR Data retention mode tR V CC 2.7 V 2.2 V V DR CS1# ≥ VCC – 0.2 V CS1# 0V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR V CC 2.7 V CS2 V DR 0.6 V 0 V < CS2 < 0.2 V 0V Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled) t CDR Data retention mode V CC 2.7 V 2.2 V V DR LB#, UB# 0V Rev.1.00, May.24.2007, page 15 of 15 LB#, UB# ≥ VCC – 0.2 V tR Revision History Rev. Date 0.01 1.00 Dec. 25, 2006 May. 24, 2007 R1LV0416D Series Data Sheet Contents of Modification Description Page Initial issue 2 Ordering Information R1LV0416DSB-5S% to R1LV0416DSB-5SI R1LV0416DSB-7L% to R1LV0416DSB-7LI R1LV0416DBG-5S% to R1LV0416DBG-5SI R1LV0416DBG-7L% to R1LV0416DBG-7LI 3 Pin Arrangement A6 to A13, A13 to A6 4 Change of Block Diagram 5 Absolute Maximum Ratings: Deletion of R ver. specification 5 DC Operating Conditions: Deletion of R ver. specification 6 DC Characteristics ISB1 (-5SI) (to +25°C) max: 3 µA to 2.5 µA AC Characteristics: Change of Test Conditions 7 Low VCC Data Retention Characteristics 14 ICCDR (-5SI) (to +25°C) max: 3 µA to 2.5 µA Deletion of note 2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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