ANALOG
W DEVICES
CompleteQuad12-Bit
OfA Converter
withReadback
FEATURES
Data Readback Capability
Four Complete, Voltage Output, 12-Bit DACs in One
32-Pin Hermetic Package
Fast Bus Access: 40ns max, Tmin-Tmax
Asynchronous Reset to Zero Volts
Minimum of Two TTL Load Drive (Readback Mode)
Double-Buffered Data Latches
Monotonicity Guaranteed TminoTmax
Linearity Error :t:1/2LSB
Low Digital-to-Analog Feedthrough, 2nV sec typ
Factory Trimmed Gain and Offset
Low Cost
OBS
OLE
PRODUCT DESCRIPTION
The AD392 is a quad I2-bit, high-speed, voltage output digital-toanalog converter with readback in a 32-pin hermetically sealed
package. The design is based on a custom IC interface to complete
I2-bit DAC chips which reduces chip count and provides high
reliability. The AD392 is ideal for systems requiring digital
control of many analog voltages and for the monitoring of these
analog voltages especially where board space is a premium. Such
applications include ATE, robotics, process controllers and
precision fIlters.
Featuring maximum access time of 40ns, the AD392 is capable
of interfacing to the fastest of microprocessors. The readback
capability provides a diagnostic check between the data sent
from the microprocessor and the actual data received and transferred to the DAC. When RESET is low, all four DACs are
simultaneously set to (bipolar) zero providing a known starting
point.
The AD392 is laser-trimmed to :!:1/2LSB integral linearity and
:!:ILSB max differential linearity at + 25°C. Monotonicity is
guaranteed over the full operating temperature range. The high
initial accuracy and stability over temperature are made possible
by the use of precision thin-fIlm resistors.
The individual DAC registers are accessed by the address lines
AO and Al and control lines CS and 2ND UP. These control
signals permit the registers of the four DACs to be loaded
sequentially and the outputs to be simultaneously updated.
PRODUCT HIGHLIGHTS
1. The AD392 is packaged in a 32-pin DIP and is a complete
solution to space constraint multiple DAC applications.
TE
2. Readback capability provides system monitor of DAC output
useful in ATE, robotics or any closed-loop system.
3. Fast bus access time of 40ns maximum allows for fast system
updating compatible with high-speed microprocessing.
4. Simultaneous reset to zero volts output is extremely useful
for system calibration or simply when all DAC outputs must
initially start at zero volts.
5. Readback drive capability of two TTL loads virtually eliminates
the need to buffer.
6. Each DAC is independently addressable, providing a versatile
control architecture for simple interface to microprocessors.
7. Monolithic DAC chips provide excellent linearity and guaranteed monotonicity over the full operating temperature range.
8. Low digital-to-analog feedthrough (2nV sec typ) is maintained
to assure DAC accuracy.
9. New pin stake package provides a low-cost solution to cost
constraint applications.
The AD392 outputs are calibrated for a :!:lOV output range
with positive true offset binary input coding.
The AD392 is packaged in a 32-lead ceramic package and is
hermetically sealed. The AD392 is specified for operation over
the 0 to + 70°C temperature range.
Information furnished by Analog Devices is believed to be accurate
and reliable. However. no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106
Tel: 617/329-4700
TWX:710/394-6577
West Coast
Mid-West
Texas
714/641-9391
3121350-9399
2141231-5094
SPECIFICATIONS
Nee = +
15V.
VEE
= -15V,
Voo
=
+ 5V.
TA
+ 25"C, unlessothelWisespecified)
AD392
Parameter
DATA INPUTS (Pins 1-13, 16-18,30-32)
TTL Compatible
Input Voltage
Bit ON (Logic "I")
Bit OFF (Logic "0")
Input Current
+ 25°C
T nUnto T max
Bidirectional Outputs (Pins 2-13)
Voltage Output Low (IoL = +4.0mA)
Voltage Output High (IoH = -4.0mA)
Tristate Output Leakage
Min
Max
+2.0
DGND
+Voo
+0.8
V
V
Voo = 5.25V
Voo = 4.75V
-2
-20
+2
+20
J.LA
J.LA
VIN = VooorGND
VIN = VooorGND
0
+2.4
+0.4
Voo
V
V
+20
J.LA
V
mA
mA
OBS
-20
T nUnto T max
DAC Output Voltage Range
Current Range
Short Circuit Current
Gain Error
Offset
Bipolar Zero
Integral Linearity Error
Differential Linearity Error
TEMPERATURE PERFORMANCE
Gain Drift
Offset Drift
Integral Linearity Error
::,::10
-5
+5
+40
OLE
-0.1
-0.05
+0.1
+0.05
-0.5
-1
::'::0.05
::'::0.025
::,::0.025
::'::0.25
::'::0.5
+0.5
+1
%ofFSR
%ofFSR
%ofFSR
LSB
LSB
-25
-25
::'::20
::,::20
+25
+25
ppm FSRloC
ppm FSRlOC
-1
+1
LSB
-Monotonicity Guaranteed Over Full Temperature Range-
T nUnto T max
Differential Linearity Error
J
Settling Time (to ::'::1/2LSB)
Change All Register Inputs
From +5VtoOV/OVto +5V
For LSB Change
Slew
Digital-to-Analog Glitch Impulse
Crosstalk
+Vcc, -VEE
+Voo
Current (All Digital Inputs DGND or
+ VooONL Y, No Load)
Ice
lEE
100
Power Dissipation
4
2
I
10
2
0.1
::'::13.5
+4.5
26
62
7.2
1356
POWER SUPPLY GAIN SENSITIVITY
+ Vcc, Voo, - VEE
Operating (Full SpecificatIons)
Storage
NOTES
'VOUT= VooorDGND.
See Note I
0
-65
See Note 3
See Note 4
V
V
44
82
13
1955
mA
mA
mA
mW
See Note 5
0.002
%FS/%Vs
See Note 6
+70
+ 150
°C
°C
-
3Digital-to-Analog Glitch Impulse: This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change state. Specified as the area of the glitch in nV sees.
'Crosstalk is deemed as the change in anyone output as a result of any other output being driven
from -IOVto + IOV intoa2kO load.
'Ojc approximately lOoCIW.
6+VCC, +Voo, -VEEare :tIO%.
-2-
See Note 2
::'::16.5
+5.5
2 Referenced to trailing rising edge ofWR.
Specifications subject to change without notice.
J.Ls
J.Ls
V/J.LS
nVsec
LSB
TE
I-.!,,'
-
ABSOLUTEMAXIMUMRATINGS.
+ Va:: to AGND (Any DAC)
- VEEto AGND (Any DAC)
. . . . . . . . . . . . 0 to
. . . . . . . . . . . . 0 to
+VDDtoDGND
Digital Inputs to DGND
(Pins 1-13, 16-18, 30-32)
Analog Outputs (Pins 20,22,26,28)
+ 18V
-18V
-0.3Vto+7V
Short Circuit Duration.
(+ Va::, - VEEorAGND)
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stess rating only and functional
operation at or above this specification is not implied. Exposure to above
maximum rating conditions for extended periods may affect device reliability.
. . . . . . -O.3Vto +7V
. . . . . . . . .
IndefInite
StorageTemperature. . . . . . . . . . . . - 65°C to + 150°C
CAUTION:
ESD (Electro-Static-Discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
OBS
PACKAGE OUTLINE
PIN CONFIGURATION
O
LE
J
Dimensions shown in inches and (mm).
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AD392
TOP VIEW
(Not to Scalel
lID
Model
AD392JV
ORDERING GUIDE
Temperature
Linearity Error
Range
Gain Error T min-T max
Oto + 70°C
:t4LSB
:tlLSB
-3-
Quantity
1-24
25-99
100+
Price
$151.00
$132.00
$ 99.00
Theoryof Operation
The AD392 is a quad 12-bit digital-to-analog converter with
readback capability. The analog portion of the AD392 includes
four bipolar process digital-to-analog converters. Each DAC
contains current steering switches and a resistor ladder network
which is laser-wafer trimmed for 12-bit accuracy. A precision
output amplifier for voltage out operation and an internal highly
stable voltage reference are all integrated on a single chip. The
DAC is fIXed to run in bipolar, 20V span analog output mode as
shown in Table I.
Data Input
1111
1111
1111
1100
0000
0000
I AnalogOutput
AnalogOutput Vollage
I + I,(VREFIN) { 2048
2O47}
+9.995IV
I
+ I,(VREFIN)
{ 2048
1O24}
I .+5.000V
+ Full Scale-ILSB
+ 1/2Scale
OBS
1000
1000
0111
0000
0000
1111
0100
0000
0000
0000
0001
0000
llli
0000
I
+I,(VREFIN)
{28}
1 +I,(VREFIN
){28}
2048
I -I'(VREFIN) {-L}
I
-I'(VREFIN)
{ 2048
1O24}
I +4.88mV
+ILSB
I +o.ooov
Zero
I -4.88mV
-ILSB
I
- 5.000V
I -IO.OOOV
-I'(VREFIN) g}
Table I. AD392 Bipolar Code Table.
DA1;A AND CONTROL SIGNAL FORMAT
The double buffered registers of the AD392 are addressed by
the CS, Al and AO lines. Each rank of registers is 12 bits wide
and is presented in a straight offset binary notation. The first
rank of registers are loaded sequentially, with valid CS, AI, AO
on the trailing rising edge of WR. The second rank of registers,
on the other hand, are loaded simultaneously with the data
which is in their corresponding first rank registers, with a valid
CS and positive pulse of the 2ND UP command. (Note: All
second rank registers can be made transparent by tieing the
2ND UP line to a Logic "1".) The data loaded into the second
rank registers represents the actual digital code which is on the
input of the individual DACs. This data can be read back through
the data port, with valid CS, Al and AO, by taking the RD line
to a Logic "0". The AD392 also features an asyncronous reset
to zero volts for all four DACs by applying a negative pulse to
the RESET line. Executing a reset replaces the contents of both
ranks of registers with the bipolar zero code (MSB equals Logic
"1", all other bits equal Logic "0".)
CS
Al
AO
WR
RD
RESET
OLE
2ND Up
X
X
X
X
X
I
X
X
X
X
X
0
X
MSBs Go to I,All
OthersGotoO
0
X
X
X
X
I
I
0
X
X
X
X
I
0
All 2ND Rank
Latches Transparent
All 2ND Rank
Latches Latched
0
0
0
I
0
I
0
0
0
U
I
I
0
0
I
I
0
I
0
0
I
U
I
I
0
I
0
I
0
I
0
I
0
I
0
I
I
I
0
I
I
ru-
- FullScale
The digital portion of the AD392 includes the readback function,
control logic and registers all integrated on a custom IC. Data
can be latched into anyone of the first rank registers by selecting
the correct combination of address lines (AOand AI) and CS.
The second rank registers are controlled by the 2ND UP control
line. Use of the 2ND UP line enables the DACs to be updated
simultaneously. The digital word can be readback from the
second rank registers by asserting the correct address lines,
2ND UP and RD command. The RD and WR commands
control the bidirectional I/O port. The AD392 features a RESET
command for simultaneous update of all DACs to 0 volts out.
This is useful for easy system calibration.
u
Chip ReadlWrite Disable
TE
X
ReadBackDACI
2ND Rank
X
Write to 1ST Rank
DACI
X
Read Back DAC2
2ND Rank
X
Write to 1ST Rank
DAC2
X
ReadBackDAC3
2ND Rank
I
X
Write to 1ST Rank
DAC3
0'
I
X
ReadBackDAC4
2ND Rank
I
I
X
Write to 1ST Rank
DAC4
Symbols: X = Don'tCare
I = Logic High
0 = Logic Low
AD392
U
= Positive Trailing
Edge Triggered
Table II. AD392 Truth Table
WR AD 2NDUP
!!!1
0
...
I
en
I
(')
(')
0
Output
I
- 1/2Scale
CD
+5V
DGND
Figure 1. AD392Block Diagram
-4--
<i.
en
::i
~
c
~
z
a:
Q.
,~() )
TIMING
The timing diagrams (Figures 2 and 3) illustrate the precise
relationship between control signals, address signals and the
data. The address lines (CS, AI, AO)as well as the data (DO-Dll)
must be valid a minimum of l5ns before a WR is executed, and
the data must remain valid a minimum of l5ns after the WR
has been executed. Minimum pulse width for the WR, 2ND UP
and RESET commands is l5ns, Similarly, the address lines (CS,
AI, AO)must be valid a minimum of 15ns before a RD is executed.
Data will be valid a maximum of 40ns after RD goes low, (Note:
This is a MAXIMUM and, therefore, data should be off the bus
just before RD goes low to avoid bus contention problems, i.e.,
damage to the device, data bus oscillations which may result in
latching erroneous data in the registers.) Data will be off the
bus a maximum of 30ns after RD goes high. (Note: This is a
MAXIMUM and, therefore, the data read should be completed
just before RD goes high to avoid reading erroneous data.)
DAC settling time is measured from the trailing rising edge of
the WR signal.
OBS
A°-i
I
Parameter
Min
IDS
tw
tsu
tHD
IRS
tVR
tDDS
tBAOn
tBAOff
t2L!
t21.2
t2TR
tnn
tR"tp
Device Select
Write!UpdatelResetPulse Width
Data SetUp Time
Data Hold Time
Reset Valid for Read
Read Valid After Write
Device De-Select (from Read Data to Tristate
Bus Access On Time
Bus Access Off Time
Minimum Latch Delay after Write/
Minimum Latch Delay after Next Write!
2ND Rank Transparent for Valid Read
2ND Rank Transparent to DAC Port Outputs
Data Rise, Fall Times
IS
IS
IS
IS
-1 tV"
ViR
Timing
DATA IN
between
pulses measured
--I
iID
4
tm
l
'"
TE
3
~
0
>
10
DATA
OUT
30
20
ns
'DATA IS IN BOTH 1" AND 2NO RANKS
uDATA B IS IN 2NORANK. DATA C IS IN 1" RANK
40
50
Figure 4. Typical Bus Access Off Time (tSA Off)
Figure 2. AD392 Write/Read Cycle Timing Diagram
I
'"
~
I
RD
ON
TRISTATE
0
>
I
I-
--.:::r::.
DATA IN
(lID BUS)
DATA
OUT
f
:~I
DATA OUT
IVO BUSI
--J
TRISTATE
TRISTATE
'"
ON
I)(
1--'00'--1
X
RESET CODE
TRISTATE
RD
TRISTATE
10
r-t,,-J
3,
20
30
40
50
ns
¥
RESET
Figure
40
5
0
Table 11/. ACCharactertics:
Voo = 5.0V::!::10%;
05TA5+70°C;
v,N= VooorDGND
RESET
\VA
10
5
25
Bus access off time measured from 50% point of read going high to point at which voltage
rrails away from active high or low under standard tristate load conditions (see Figure 6).
TRISTATE
mJ
40
40
30
at 50"A,points.
TRISTATE
DATA OUT
35
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus access on rime measured from 50% point of read going low to active high (2.4)
or active low (0.4) (see Figures 4 and 5).
r
2ND UP
Max Unit
NOTES
OLE
esj
AI
Symbol
Figure 5. Typical Bus Access On Time (tSA On)
+5V
AD392 Read Cycle Timing Diagram
IHP6216A
VOLTAGE
SUPPLY
I
RI
TRISTATE
OUTPUT
TO SCOPE INPUT
TEKTRONIX
7A26 PLUG.IN
-
RI
R2
CI
R2
P6106A
PROBES
7704A MAINFRAME
7B92 TIME BASE
OR EQUIVALENT
=
1.35kH
=
15pF,
""%,1/4W
= 1.25kH ""%, 1/4W
= 100pF, FOR tBA ON
FOR
tBA OFF
ALL DIODES IN916
OR EQUIVALENT
DIGITAL
GROUND
Figure 6. Standard Tristate Load Circuit
-5-
SETTLING TIME
The output amplifiers used in the AD392 are capable of supplying
a :t 10 volt swing into a resistive load of 2kD or greater. The
settling characteristics of the output amplifier is shown in
Figure 7. The test setup used to determine settling time is shown
in Figure 8.
the DAC bit input currents are sourced from the + VDDsupply
and should return by the shortest possible path and not down
the analog return (see Figure 9 for details.).
ADDRESS
8US
POWER SUPPLY DECOUPLING
The power supplies used with the AD392 should be well filtered
and regulated. Internally the + Vcc and - VEEsupplies are
independently decoupled about each DAC with O.O39/LFchip
capacitors to their corresponding AGND. Therefore, if the
grounding scheme of Figure 9 is used, it should be sufficient to
place a 4.7/LF tantalum electrolytic capacitor across the + Vcc
and - VEE supplies. Decoupling the + VDD supply to DGND
should be done in the same manner, however, using a parallel
combination ofO.O47/LFceramic and a 4.7/LF tantalum electrolytic
capacitor.
RESET
I
0>
I
M
M
0
15V
AGNO
RETURN
+5V
(DIGITAL)
OGNO
2ND UP
RETURN
WR
Figure
3
+5V
-V'>IT""'
IHP6216A
VOLTAGE
SUPPLVI
2", UP
A'
WR
m
AGND
0.01% FSR = lmV (" ARTIFICIAL SUMMING
Circuit Schematic
TE
HP80128
PULSE GEN.
HPB0128
PULSE
DECODE
GEN.
9.AD392Recommended
RO
CIRCUIT DETAILS
The following two suggestions are intended to aid the user in
the normal operation of the AD392:
1. Bus Termination: The bidirectional tristateable port of the
AD392 (as well as the digital inputs) should not be allowed
to "float". These functions are provided by a custom CMOS
integrated circuit having an input control circuit which is
essentially the common gate contact of a pair of P and N
channel MOS devices connected in series between the + VDD
and DGND supply lines. An unterminated bus allows the
gate potential to float to a point where both channels are
partially "on" creating an ohmic path across the supply.
Therefore, to avoid excessive supply current drain and possible
reflections of the digital signal the bus should be terminated
in its characteristic impedance to DGND.
AD392V0 Settling 20V Step
AD392
U
+15V
OLE
ADDRESS
!1:1
0
~
OBS
Figure 7.
CD
TEKTRONIX
"'>PLUG.IN
P6106A PROBE
77OA MAINFRAME
7892 TIME BASE
2. Digital Signal Integrity and the RESET line: The AD392
has been designed to respond to extremely fast data rates and
as a result must operate with a "clean" bus to ensure that
valid data is being transmitted (i.e., transients on the bus
that cross thresholds with sufficient duration, Sns-lOns, may
cause data to become invalid just before a WR command). If
the RESET line is not connected to this "clean" bus (i.e.,
connected to some sort of power on reset circuitry), then it is
recommended that this line be decoupled with a minimum of
1O00pfcapacitor to avoid an unwanted asynchronous zero
volt reset on all four DACs. If this signal is not used, it
should be tied to + VDD at the package.
NODE
Figure 8. AD392 V0 Settling Time Circuit
GROUNDING RULES
The AD392 has been designed with four independent DAC
analog grounds and a separate digital ground return pin. The
analog ground pins are not only the reference points for the
individual voltage outputs, they also serve as the return path for
the switched DAC bit input currents. These rapidly switching
currents may be as large as several milliamps for each DAC
and, therefore, should be returned to a low impedance node to
avoid code dependent linearity errors, digital-to-analog feedthrough and crosstalk between DAC outputs. It is recommended
that all four DAC analog grounds and the digital ground be tied
together at the package for optimal performance. + Vcc and
- VEEgrounds can be tied together back at the system supply
and brought up to the AD392 together, whereas the + VDD
ground is tied to the other grounds at the package and not back
at the system supply. This configuration is recommended because
-6-
<i.
en
::i
~
0
w
IZ
ii:
0..