MX63UxG 130-Ball MCP SLC NAND FLASH and LPDDR 130-Ball MCP MCP (Multi-Chip Package) MX63UxGxxx Key Features NAND Flash Features: • Low Power Dissipation • High Reliability P/N:PM2066 REV. 1.0, MAR. 13, 2015 1 MX63UxG 130-Ball MCP Contents 1. MCP FEATURES.................................................................................................................................3 2. BLOCK DIAGRAM...............................................................................................................................4 3. PART NAME DESCRIPTION...............................................................................................................5 4. Product Selection Guide....................................................................................................................6 5. PIN CONFIGURATIONS......................................................................................................................7 130-Ball, BGA (NAND x8; LPDDR x32)................................................................................................................ 7 130-Ball, BGA (NAND x8/x16; LPDDR x16)......................................................................................................... 8 6. PIN DESCRIPTION..............................................................................................................................9 LPDDR x32........................................................................................................................................................... 9 LPDDR x16......................................................................................................................................................... 10 7. PACKAGE INFORMATION................................................................................................................11 8. REVISION HISTORY .........................................................................................................................12 P/N:PM2066 REV. 1.0, MAR. 13, 2015 2 MX63UxG 130-Ball MCP 1. MCP FEATURES •Unique ID Read support (ONFI) •Secure OTP support •Electronic Signature (5 Cycles) •High Reliability - Endurance: typical 100K cycles (with 4-bit ECC per (512+16) Byte) - Data Retention: 10 years • Wide Temperature Operating Range - 40°C to +85°C Operation Temperature • -40°C to +85°C Package • 130-ball FBGA - 8.0mm x 9.0mm, 1.0mm (h), 0.65mm pitch NAND Flash Features • 2G-bit SLC NAND Flash - Bus: x8 / x16 - Page size: (2048+64) byte for x8 bus, (1024+32) word for x16 bus - Block size: (128K+4K) byte for x8 bus, (64K+2K) word for x16 bus - Plane size: 1024-block/plane x 2 • 1G-bit SLC NAND Flash - Bus: x8 / x16 - Page size: (2048+64) byte for x8 bus, (1024+32) word for x16 bus - Block size: (128K+4K) byte for x8 bus, (64K+2K) word for x16 bus - Plane size: 1024-block/plane x 1 •ONFI 1.0 compliant •User Redundancy - 64-byte attached to each page •Fast Read Access - Latency of array to register: 25us - Sequential read: 25ns •Cache Read Support •Page Program Operation - Page program time: 320us (typ.) •Cache Program Support •Block Erase Operation - Block erase time: 1.0ms (typ.) •Single Voltage Operation: - VCC: 1.7 ~ 1.95V •Low Power Dissipation - Max. 30mA (1.8V) Active current (Read/Program/Erase) •Sleep Mode - 50uA (Max) standby current LPDDR DRAM Features • • • • • • • • • • • • • • • • • • • • • P/N:PM2066 VDD/VDDQ = 1.7~1.95V Data width: x16, x32 Clock rate: 200MHz, 166MHz, 133MHz Partial Array Self-Refresh (PASR) Auto Temperature Compensated Self-Refresh (ATCSR) Power Down Mode Deep Power Down Mode (DPD Mode) Programmable output buffer driver strength Four internal banks for concurrent operation Data mask (DM) for write data Clock Stop capability during idle periods Auto Pre-charge option for each burst access Double data rate for data output Differential clock inputs (CK and /CK ) Bidirectional, data strobe (DQS) /CAS Latency: 2 and 3 Burst Length: 2, 4, 8 and 16 Burst Type: Sequential or Interleave 64 ms Refresh period Interface: LVCMOS Operating Temperature Range - Industrial (-40°C to +85 °C) REV. 1.0, MAR. 13, 2015 3 MX63UxG 130-Ball MCP 2. BLOCK DIAGRAM NAND ALE IOx~IO0 CLE CE# NAND RE# WE# R/B# WP# PT (For 1.8V) LPDDR CKE CK /CK /CS /WE /CAS /RAS Ax~A0 LPDDR DQ0~DQx DQS0~DQS3 / UDQS & LDQS Address, BA0, BA1 DM0~DM3 / UDQM & LDQM P/N:PM2066 REV. 1.0, MAR. 13, 2015 4 MX63UxG 130-Ball MCP 3. PART NAME DESCRIPTION MX63 U 1G D 12 E A XN I 00 Reserved Product Grade I: Industrial Package XM: 162-Ball FBGA XN: 130-Ball FBGA MCP Combinations Type CE# A 1,1 Combination 1 NAND; 1 LPDDR LPDDR Configuration Type A B C E F J K DDR2 DDR2 DDR2 DDR DDR DDR DDR Bus Vcc Generation Speed x16 x32 x32 x16 x32 x16 x32 1.7-1.95V 1.7-1.95V 1.7-1.95V 1.7-1.95V 1.7-1.95V 1.7-1.95V 1.7-1.95V 3 2 3 5 5 5 5 533MHz 533MHz 533MHz 200MHz 200MHz 200MHz 200MHz LPDDR Density 256M = 56 512M = 12 1G = 1G 2G = 2G 4G = 4G 8G = 8G NAND Configuration Type Bus A B x8 x16 Number of ECC-bit 8 8 C x8 4 1st D x16 4 1st Generation 1st 1st NAND Density 512M = 12 8G = 8G 1G = 1G 16G = AG 2G = 2G 32G = BG 4G = 4G 64G = CG NAND Voltage: 1.8V Product Family MX63U : NAND + LPDRAM MCP P/N:PM2066 REV. 1.0, MAR. 13, 2015 5 MX63UxG 130-Ball MCP 4. Product Selection Guide Device NAND Flash Mobile DRAM Package Type MX63U1GD12EAXNI00 1Gb, x16, 1.8V, 4-bit ECC 512Mb, LPDDR, x16, 1.8V 130 Ball BGA MX63U1GC12FAXNI00 1Gb, x8, 1.8V, 4-bit ECC 512Mb, LPDDR, x32, 1.8V 130 Ball BGA MX63U2GC1GKAXNI00 * 2Gb, x8, 1.8V, 4-bit ECC 1Gb, LPDDR, x32, 1.8V 130 Ball BGA MX63U2GD1GJAXNI00 * 2Gb, x16, 1.8V, 4-bit ECC 1Gb, LPDDR, x16, 1.8V 130 Ball BGA Notes: 1. For other NAND/ LPDDR I/O combination, please cotact Macronix Representative. 2. * Advanced Information P/N:PM2066 REV. 1.0, MAR. 13, 2015 6 MX63UxG 130-Ball MCP 5. PIN CONFIGURATIONS 130-Ball, BGA (NAND x8; LPDDR x32) 1 2 3 4 5 6 7 8 9 10 A NC DNU RE# CLE VCC CE# WE# VDD VSS NC A B VSS A4 WP# ALE VSS R/B# DQ31 DQ30 VDDQ VSSQ B C VDD A5 A7 A9 DQ25 DQ27 DQ29 DQ28 VSSQ VDDQ C D A6 A8 CKE DQ18 DQS3 DQ22 DM3 DQ26 VDDQ VSSQ D E A12 A11 DNU DQ17 DQ19 DQ24 DQ23 DM2 VSSQ VDDQ E F NC /RAS DQ15 DQ16 DQS1 DM1 DQ9 CK VDDQ VSSQ F G VDD /CAS DQ20 DQ21 DQ13 DQ12 DQS2 /CK VSS VDD G H VSS /CS BA0 DQ14 DQ11 DQ10 DQS0 DM0 VSSQ VDDQ H J /WE BA1 A10 A0 DQ7 DQ8 DQ6 DQ4 VDDQ VSSQ J K A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ K L VDD VSS DNU DNU I/O3 I/O5 DNU I/O7 VSSQ VDDQ L M I/O0 I/O1 I/O2 DNU VCC I/O6 DNU DNU VDDQ VSSQ M N DNU DNU DNU DNU DNU VSS I/O4 VDD VSS PT N 1 2 3 4 5 6 7 8 9 10 NAND Supply LPDDR P/N:PM2066 Ground REV. 1.0, MAR. 13, 2015 7 MX63UxG 130-Ball MCP 130-Ball, BGA (NAND x8/x16; LPDDR x16) 1 2 3 4 5 6 7 8 9 10 A NC DNU RE# CLE VCC CE# WE# VDD VSS NC A B VSS A4 WP# ALE VSS R/B# DQ15 DQ14 VDDQ VSSQ B C VDD A5 A7 A9 DQ9 DQ11 DQ13 DQ12 VSSQ VDDQ C D A6 A8 CKE RFU UDQS RFU UDQM DQ10 VDDQ VSSQ D E A12 A11 RFU RFU RFU DQ8 RFU RFU VSSQ VDDQ E F NC /RAS RFU RFU RFU RFU RFU CK VDDQ VSSQ F G VDD /CAS RFU RFU RFU RFU RFU /CK VSS VDD G H VSS /CS BA0 RFU RFU RFU LDQS LDQM VSSQ VDDQ H J /WE BA1 A10 A0 DQ7 RFU DQ6 DQ4 VDDQ VSSQ J K A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ K L VDD VSS A13* RFU I/O3 I/O5 I/O14 I/O7 VSSQ VDDQ L M I/O0 I/O1 I/O2 I/O10 VCC I/O6 I/O13 I/O15 VDDQ VSSQ M N RFU I/O8 I/O9 I/O11 I/O12 VSS I/O4 VDD VSS PT N 1 2 3 4 5 6 7 8 9 10 NAND Supply LPDDR Ground *Note: A13 is only for 1Gb LPDDR1. It is DNU pin in Other density. P/N:PM2066 REV. 1.0, MAR. 13, 2015 8 MX63UxG 130-Ball MCP 6. PIN DESCRIPTION LPDDR x32 SYMBOL I/O0 ~ I/O7 CLE ALE CE# WE# RE# WP# R/B# VCC VSS PT CK, /CK CKE /CS /RAS, /CAS, /WE DM0 ~ DM3 DQ0 ~ DQ31 DQS0 ~ DQS3 BA0, BA1 Ax ~ A0 VDDQ VSSQ VDD NC DNU * NAND Flash 2Gb (x8) 1Gb (x8) V V V V V V V V V V V DESCRIPTION Data Input / Output Command Latch Enable Address Latch Enable Chip Enable Write Enable Read Enable Write Protect Ready / Busy Out Supply Voltage Ground Chip Protection Enable Differential Clock Input Clock Enable Chip Select Command Input Input Data Mask Data I/O Data Strobe Pin Bank Address Input Address Input DQ Power Supply DQ Ground Power Supply No Connection Do Not Use V LPDDR 1Gb (32Mb x32) 512Mb (16Mbx32) V V V V V V V V V V V V V V V * : DNU pin must keep floating. P/N:PM2066 REV. 1.0, MAR. 13, 2015 9 MX63UxG 130-Ball MCP LPDDR x16 SYMBOL I/O0 ~ I/Ox CLE ALE CE# WE# RE# WP# R/B# VCC VSS PT CK, /CK CKE /CS /RAS, /CAS, /WE UDQM & LDQM DQ0 ~ DQx UDQS & LDQS BA0, BA1 Ax ~ A0 VDDQ VSSQ VDD NC DNU * NAND Flash 2Gb (x16) 1Gb (x16) V V V V V V V V V V V DESCRIPTION Data Input / Output Command Latch Enable Address Latch Enable Chip Enable Write Enable Read Enable Write Protect Ready / Busy Out Supply Voltage Ground Chip Protection Enable Differential Clock Input Clock Enable Chip Select Command Input Input Data Mask Data I/O Data Strobe Pin Bank Address Input Address Input DQ Power Supply DQ Ground Power Supply No Connection Do Not Use V LPDDR 1Gb (64Mb x16) 512Mb (32Mb x16) V V V V V V V V V V V V V V V * : DNU pin must keep floating. P/N:PM2066 REV. 1.0, MAR. 13, 2015 10 MX63UxG 130-Ball MCP 7. PACKAGE INFORMATION P/N:PM2066 REV. 1.0, MAR. 13, 2015 11 MX63UxG 130-Ball MCP 8. REVISION HISTORY Revision No. Description 0.01 1. Removed MX63U2GA1GEAXNI00 ; Added MX63U1GD12EAXNI00/MX63U1GC12FAXNI00/ MX63U2GC1GKAXNI00/MX63U2GD1GJAXNI00 2. Modified Package Information 1.0 1. Removed document status "ADVANCED INFORMATION" 2. Content modification 3. Updated the PART NAME DESCRIPTION 4. Re-arrange the order of pin description tables 5. Added note in PIN CONFIGURATIONS - 130-Ball, BGA (NAND x8/x16; LPDDR x16) P/N:PM2066 Page All P10 All P3,9-10 P5 P9-10 P8 Date SEP/25/2014 MAR/13/2015 REV. 1.0, MAR. 13, 2015 12 MX63UxG 130-Ball MCP Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. 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