MX63UxG 162-Ball MCP SLC NAND FLASH and LPDDR2 162-Ball MCP (Multi-Chip Package) P/N:PM2054 REV. 1.1, OCT. 24, 2014 1 MX63UxG 162-Ball MCP 1. MCP FEATURES • Low Power Dissipation - Max. 30mA (1.8V) Active current (Read/Program/Erase) • Sleep Mode - 50uA (Max) standby current • Unique ID Read support (ONFI) • Secure OTP support • Electronic Signature (5 Cycles) • High Reliability - 8 bit-ECC SLC NAND Flash: Endurance: typical 100K cycles (with 8-bit ECC per (512+28) Byte) - 4 bit-ECC SLC NAND Flash: Endurance: typical 100K cycles (with 4-bit ECC per (512+16) Byte) - Data Retention: 10 years Operation Temperature • -30°C to +85°C Package • 162-ball FBGA - 8.0mmx10.5mm, 1.0mm (h) (max), 0.5mm pitch NAND Flash Features • 2G-bit/4G-bit SLC NAND Flash - Bus: x8 / x16 - 8 bit-ECC SLC NAND Flash: Page size: (2048+112) byte for x8 bus, (1024+56) word for x16 bus Block size: (128K+7K) byte for x8 bus, (64K+2K) word for x16 bus - 4 bit-ECC SLC NAND Flash: Page size: (2048+64) byte for x8 bus, (1024+32) word for x16 bus Block size: (128K+4K) byte for x8 bus, (64K+2K) word for x16 bus - Plane size: 1024-block/plane x 2 for 2Gb 2048-block/plane x 2 for 4Gb • ONFI 1.0 compliant • User Redundancy - 8 bit-ECC SLC NAND Flash: 112-byte attached to each page - 4 bit-ECC SLC NAND Flash: 64-byte attached to each page • Fast Read Access - Latency of array to register: 25us - Sequential read: 25ns • Cache Read Support • Page Program Operation - Page program time: 320us (typ.) • Cache Program Support • Block Erase Operation - Block erase time: 1.0ms (typ.) • Single Voltage Operation: - VCC: 1.7 ~ 1.95V LPDDR2 DRAM Features • • • • JEDEC LPDDR2-S4B compliance DLL is not implemented Low power consumption Mobile RAM functions - Partial Array Self-Refresh (PASR) - Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor - Deep power-down mode - Per Bank Refresh • VDD Definition: Typical Range VDD1 1.8V 1.7~1.95V VDD2 1.2V 1.14~1.3V VDDQ 1.2V 1.14~1.3V - Voltage source of VREFCA is VDD2, VREFCA=1/2*VDD2 (from voltage divider) - Voltage source of VREFDQ is VDDQ, VREFDQ=1/2*VDDQ (from voltage divider) VREFCA VREFDQ P/N:PM2054 Min. 0.49xVDD2 0.49xVDDQ Max. 0.51xVDD2 0.51xVDDQ REV. 1.1, OCT. 24, 2014 2 MX63UxG 162-Ball MCP 2. BLOCK DIAGRAM NAND ALE IOx~IO0 CLE CE# RE# NAND WE# R/B# WP# PT LPDDR2 VSS VDD1 VDD2 VDDQ VDDCA VSSQ VSSCA VREFCA VREFDQ /CS CKE CK /CK DM ZQ RZQ LPDDR2 CA[9:0] DQ[31:0] DQS P/N:PM2054 REV. 1.1, OCT. 24, 2014 3 MX63UxG 162-Ball MCP 3. PART NAME DESCRIPTION MX63 U 4G A 2G B A XM I 00 Reserved Product Grade I: Industrial Package MCP Combinations Type CE# A 1,1 Combination 1 NAND; 1 LPDDR LPDDR Configuration Type Bus Vcc Generation Speed A DDR2 x32 1.7-1.95V 1 200MHz B DDR2 x32 1.7-1.95V 2 533MHz C DDR2 x32 1.7-1.95V 3 533MHz LPDDR Density 256M = 56 512M = 12 1G = 1G 2G = 2G 4G = 4G 8G = 8G NAND Configuration Type Bus A B x8 x16 Number of ECC-bit 8 8 C x8 4 1st D x16 4 1st Generation 1st 1st NAND Density 512M = 12 8G = 8G 1G = 1G 16G = AG 2G = 2G 32G = BG 4G = 4G 64G = CG NAND Voltage: 1.8V Product Family MX63U : NAND + LPDRAM MCP P/N:PM2054 REV. 1.1, OCT. 24, 2014 4 MX63UxG 162-Ball MCP 4. Product Selection Guide Device NAND Flash Mobile DRAM Package Type MX63U4GA2GBAXMI00 4Gb, x8, 1.8V, 8-bit ECC 2Gb, LPDDR2, x32, 1.8V 162 Ball BGA MX63U4GB2GBAXMI00 4Gb, x16, 1.8V, 8-bit ECC 2Gb, LPDDR2, x32, 1.8V 162 Ball BGA MX63U2GA1GCAXMI00 2Gb, x8, 1.8V, 8-bit ECC 1Gb, LPDDR2, x32, 1.8V 162 Ball BGA MX63U2GB1GCAXMI00 2Gb, x16, 1.8V, 8-bit ECC 1Gb, LPDDR2, x32, 1.8V 162 Ball BGA MX63U2GC1GCAXMI00 * 2Gb, x8, 1.8V, 4-bit ECC 1Gb, LPDDR2, x32, 1.8V 162 Ball BGA MX63U4GC2GBAXMI00 * 4Gb, x8, 1.8V, 4-bit ECC 2Gb, LPDDR2, x32, 1.8V 162 Ball BGA * Advanced Information P/N:PM2054 REV. 1.1, OCT. 24, 2014 5 MX63UxG 162-Ball MCP 5. PIN CONFIGURATIONS 162-Ball, BGA (NAND x16; LPDDR x32) 1 2 3 4 5 6 7 8 VCC 9 10 A PT DNU WP# CLE VCC IO4 IO7 DNU DNU A B DNU VCC IO11 ALE RE# IO5 IO14 IO15 VSSm DNU B C IO10 IO1 IO3 WE# R/B# IO6 C D IO8 IO0 IO2 CE# IO12 IO13 D E VSSm IO9 NC VDD2 VDD1 DQ31 DQ29 DQ26 DNU E F VDD1 VSS NC VSS VSSQ VDDQ DQ25 VSSQ VDDQ F G VSS VDD2 ZQ VDDQ DQ30 DQ27 DQS3 /DQS3 VSSQ G H VSSCA CA9 CA8 DQ28 DQ24 DM3 DQ15 VDDQ VSSQ H J VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ J DQ8 VSSQ K K VDD2 CA5 VREF (CA) /DQS1 DQS1 DQ10 DQ9 L VDDCA VSS /CK DM1 VDDQ L M VSSCA NC CK VSSQ VDDQ VDD2 VSS VREF (DQ) M N CKE NC NC P /CS NC NC /DQS0 DQS0 DQ5 DQ6 DQ7 VSSQ P R CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ R DQ0 VDDQ VSSQ T VDDQ DQ17 DQ20 DQS2 /DQS2 VSSQ U T VSSCA VDDCA CA1 U VSS VDD2 CA0 V N DM0 VDDQ DQ19 DQ23 DM2 VDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ V NC VDD2 VDD1 DQ16 DQ18 DQ21 DNU W W DNU NC Y DNU DNU 1 2 3 4 5 6 7 8 DNU DNU 9 10 Y LPDDR2 Command/Address LPDDR2 Data IO NAND IO/Command/Address Ground (VSS,VSSCA,VSSQ, VSSm) Power (VDD1,VDD2, VDDCA,VREF, VCC) P/N:PM2054 REV. 1.1, OCT. 24, 2014 6 MX63UxG 162-Ball MCP 162-Ball, BGA (NAND x8; LPDDR x32) 1 2 3 4 5 6 7 8 VCC 9 10 A PT DNU WP# CLE VCC IO4 IO7 DNU DNU A B DNU VCC DNU ALE RE# IO5 DNU DNU VSSm DNU B C DNU IO1 IO3 WE# R/B# IO6 C D DNU IO0 IO2 CE# DNU DNU D E VSSm DNU NC VDD2 VDD1 DQ31 DQ29 DQ26 DNU E F VDD1 VSS NC VSS VSSQ VDDQ DQ25 VSSQ VDDQ F G VSS VDD2 ZQ VDDQ DQ30 DQ27 DQS3 /DQS3 VSSQ G H VSSCA CA9 CA8 DQ28 DQ24 DM3 DQ15 VDDQ VSSQ H J VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ J DQ8 VSSQ K K VDD2 CA5 VREF (CA) /DQS1 DQS1 DQ10 DQ9 L VDDCA VSS /CK DM1 VDDQ L M VSSCA NC CK VSSQ VDDQ VDD2 VSS VREF (DQ) M N CKE NC NC P /CS NC NC /DQS0 DQS0 DQ5 DQ6 DQ7 VSSQ P R CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ R DQ0 VDDQ VSSQ T VDDQ DQ17 DQ20 DQS2 /DQS2 VSSQ U T VSSCA VDDCA CA1 U VSS VDD2 CA0 V N DM0 VDDQ DQ19 DQ23 DM2 VDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ V NC VDD2 VDD1 DQ16 DQ18 DQ21 DNU W W DNU NC Y DNU DNU 1 2 3 4 5 6 7 8 DNU DNU 9 10 Y LPDDR2 Command/Address LPDDR2 Data IO NAND IO/Command/Address (NAND DNU pin must keep floating) Ground (VSS,VSSCA,VSSQ, VSSm) Power (VDD1,VDD2, VDDCA, VREF, VCC) P/N:PM2054 REV. 1.1, OCT. 24, 2014 7 MX63UxG 162-Ball MCP 6. PIN DESCRIPTION SYMBOL I/O0 ~ I/OX CLE ALE CE# WE# RE# WP# R/B# VCC VSSm PT /CS CK, /CK CKE CA0 ~ CA9 DQ0 ~ DQ31 DM0 ~ DM3 DQS0 ~ DQS3 /DQS0 ~ /DQS3 ZQ VREF(DQ) VREF(CA) VDD1 VDD2 VSS, VSSCA, VSSQ VDDQ VDDCA NC DNU * DESCRIPTION Data Input / Output Command Latch Enable Address Latch Enable Chip Enable Write Enable Read Enable Write Protect Ready / Busy Out Supply Voltage Ground Chip Protection Enable Chip Select Differential Clocks Clock Enable Command / Address Data I/O Input Data Mask Differential Data Strobe (rising edge) Differential Data Strobe (falling edge) Drive Strength Calibration Reference Voltage Reference Voltage Core Power Supply Core Power Supply Ground I/O Power Supply CA Power Supply No Connection Do Not Use 4Gb (512Mb x8) 2Gb (64Mb x32) NAND Flash LPDDR2-S4B V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V * : DNU pin of NAND must keep floating. P/N:PM2054 REV. 1.1, OCT. 24, 2014 8 MX63UxG 162-Ball MCP 7. PACKAGE INFORMATION P/N:PM2054 REV. 1.1, OCT. 24, 2014 9 MX63UxG 162-Ball MCP 8. REVISION HISTORY Revision No. Description 1.0 1. Modified PART NAME DESCRIPTION 2. Removed the title "Advanced information" 3. Revised Bus information, Page program and Block erase time 4. Revised block diagram (NAND) Page P4 All P2 P3 Date JUL/21/2014 1.1 P2 P2,4,5 OCT/24/2014 1. Added VDD definition 2. Added two part numbers: MX63U2GC1GCAXMI00 and MX63U4GC2GBAXMI00 P/N:PM2054 REV. 1.1, OCT. 24, 2014 10 MX63UxG 162-Ball MCP Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. 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