MX25L12850F

MX25L12850F
MX25L12850F
3V, 128M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
RPMC FLASH MEMORY
MX25L12850F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 6
3. PIN CONFIGURATIONS .......................................................................................................................................... 7
4. PIN DESCRIPTION................................................................................................................................................... 7
5. BLOCK DIAGRAM.................................................................................................................................................... 8
6. DATA PROTECTION................................................................................................................................................. 9
Table 1. Protected Area Sizes....................................................................................................................10
Table 2. 4K-bit Secured OTP Definition..................................................................................................... 11
7. Memory Organization............................................................................................................................................ 12
Table 3. Memory Organization...................................................................................................................12
8. DEVICE OPERATION............................................................................................................................................. 13
9. COMMAND DESCRIPTION.................................................................................................................................... 15
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
9-25.
P/N: PM2039
Table 4. Command Set...............................................................................................................................15
Write Enable (WREN)............................................................................................................................... 19
Write Disable (WRDI)................................................................................................................................ 20
Read Identification (RDID)........................................................................................................................ 21
Table 5. ID Definitions ...............................................................................................................................21
Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 22
Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 24
Read Status Register (RDSR).................................................................................................................. 25
Read Configuration Register (RDCR)....................................................................................................... 26
Table 6. Configuration Register Table........................................................................................................30
Write Status Register (WRSR).................................................................................................................. 31
Table 7. Protection Modes..........................................................................................................................32
Read Data Bytes (READ)......................................................................................................................... 34
Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 35
Dual Output Read Mode (DREAD)........................................................................................................... 36
2 x I/O Read Mode (2READ).................................................................................................................... 37
Quad Read Mode (QREAD)..................................................................................................................... 38
4 x I/O Read Mode (4READ).................................................................................................................... 39
Performance Enhance Mode.................................................................................................................... 40
Performance Enhance Mode Reset ......................................................................................................... 42
Sector Erase (SE)..................................................................................................................................... 43
Block Erase (BE32K)................................................................................................................................ 44
Block Erase (BE)...................................................................................................................................... 45
Chip Erase (CE)........................................................................................................................................ 46
Page Program (PP).................................................................................................................................. 47
4 x I/O Page Program (4PP)..................................................................................................................... 48
Deep Power-down (DP)............................................................................................................................ 49
Enter Secured OTP (ENSO)..................................................................................................................... 50
Exit Secured OTP (EXSO)........................................................................................................................ 50
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MX25L12850F
9-26. Read Security Register (RDSCUR).......................................................................................................... 50
9-27. Write Security Register (WRSCUR).......................................................................................................... 50
Table 8. Security Register Definition..........................................................................................................51
9-28. Program/Erase Suspend/Resume............................................................................................................ 52
9-29. Erase Suspend......................................................................................................................................... 52
9-30. Program Suspend..................................................................................................................................... 52
9-31. Write-Resume........................................................................................................................................... 54
9-32. No Operation (NOP)................................................................................................................................. 54
9-33. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 54
9-34. Read SFDP Mode (RDSFDP)................................................................................................................... 56
Table 9. Signature and Parameter Identification Data Values ...................................................................57
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables...............................................................58
Table 11. RPMC Parameter.......................................................................................................................65
Table 12. Parameter Table (1): Macronix Flash Parameter Tables............................................................66
10. POWER-ON STATE.............................................................................................................................................. 68
11. ELECTRICAL SPECIFICATIONS......................................................................................................................... 69
Table 13. ABSOLUTE MAXIMUM RATINGS.............................................................................................69
Table 14. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................69
Table 15. DC CHARACTERISTICS ..........................................................................................................71
Table 16. AC CHARACTERISTICS ..........................................................................................................72
12. OPERATING CONDITIONS.................................................................................................................................. 74
Table 17. Power-Up/Down Voltage and Timing..........................................................................................76
12-1. INITIAL DELIVERY STATE....................................................................................................................... 76
13. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 77
14. DATA RETENTION............................................................................................................................................... 77
15. LATCH-UP CHARACTERISTICS......................................................................................................................... 77
16. ORDERING INFORMATION................................................................................................................................. 78
17. PART NAME DESCRIPTION................................................................................................................................ 79
18. PACKAGE INFORMATION................................................................................................................................... 80
19. REVISION HISTORY ............................................................................................................................................ 83
P/N: PM2039
3
REV. 1.0, DEC. 08, 2014
MX25L12850F
3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
RPMC FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• 128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four
I/O mode) structure
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Fast read for SPI mode
- Support fast clock frequency for read operation as 104MHz
- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions
• Default Quad I/O enable (QE bit=1), and can not be change
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
RPMC FEATURES
• Support Replay Protection Monotonic Counter (RPMC)
- Four 32-bit Monotonic counters
- Volatile HMAC Key register
- Non-volatile Root Key register
RPMC related information is available at
https://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=22646
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block lock protection
- The BP0-BP3 and T/B status bit defines the size of the area to be protection against program and erase instructions
• Additional 4K bit security OTP
- Features unique identifier
- factory locked identifiable, and customer lockable
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
P/N: PM2039
4
REV. 1.0, DEC. 08, 2014
MX25L12850F
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input/Output
• SO/SIO1
- Serial Data Input/Output
• SIO2
- Serial Data Input/Output
• SIO3
- Serial Data input/Output
• PACKAGE
- 8-pin SOP (200mil)
- 8-land WSON (6x5mm)
- 8-pin PDIP (300mil)
- All devices are RoHS Compliant and Halogen-free
P/N: PM2039
5
REV. 1.0, DEC. 08, 2014
MX25L12850F
2. GENERAL DESCRIPTION
MX25L12850F is 128Mb bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in
two or four I/O mode, the structure becomes 67,108, 864 bits x 2 or 33,554,432 bits x 4. MX25L12850F feature a
serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin become SIO0 pin, SIO1 pin, SIO2 pin and
SIO3 pin for address/dummy bits input and data output.
The MX25L12850F MXSMIO (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L12850F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM2039
6
REV. 1.0, DEC. 08, 2014
MX25L12850F
3. PIN CONFIGURATIONS
4. PIN DESCRIPTION
8-PIN SOP (200mil)
CS#
SO/SIO1
SIO2
GND
SYMBOL
1
2
3
4
8
7
6
5
CS#
VCC
SIO3
SCLK
SI/SIO0
8-WSON (6x5mm)
CS#
SO/SIO1
SIO2
GND
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VCC
SIO3
SCLK
SI/SIO0
DESCRIPTION
Chip Select
SI/SIO0
Serial Data Input & Output
SO/SIO1
Serial Data Input & Output
SCLK
Clock Input
SIO2
Serial Data Input & Output
SIO3
Serial Data Input & Output
VCC
+ 3V Power Supply
GND
Ground
8-PIN PDIP (300mil)
CS#
SO/SIO1
SIO2
GND
P/N: PM2039
VCC
SIO3
SCLK
SI/SIO0
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REV. 1.0, DEC. 08, 2014
MX25L12850F
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
CS#
SIO2
SIO3
SCLK
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM2039
Sense
Amplifier
8
REV. 1.0, DEC. 08, 2014
MX25L12850F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES), and softreset command.
P/N: PM2039
9
REV. 1.0, DEC. 08, 2014
MX25L12850F
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as "Table 1. Protected Area Sizes", the protected
areas are more flexible which may protect various area by setting value of BP0-BP3 bits.
Table 1. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Protect Level
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128Mb
0 (none)
1 (1 block, protected block 255th)
2 (2 blocks, block 254th-255th)
3 (4 blocks, block 252nd-255th)
4 (8 blocks, block 248th-255th)
5 (16 blocks, block 240th-255th)
6 (32 blocks, block 224th-255th)
7 (64 blocks, block 192nd-255th)
8 (128 blocks, block 128th-255th)
9 (256 blocks, protected all)
10 (256 blocks, protected all)
11 (256 blocks, protected all)
12 (256 blocks, protected all)
13 (256 blocks, protected all)
14 (256 blocks, protected all)
15 (256 blocks, protected all)
Protected Area Sizes (T/B bit = 1)
Status bit
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P/N: PM2039
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Protect Level
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128Mb
0 (none)
1 (1 block, protected block 0th)
2 (2 blocks, protected block 0th~1th)
3 (4 blocks, protected block 0th~3rd)
4 (8 blocks, protected block 0th~7th)
5 (16 blocks, protected block 0th~15th)
6 (32 blocks, protected block 0th~31st)
7 (64 blocks, protected block 0th~63rd)
8 (128 blocks, protected block 0th~127th)
9 (256 blocks, protected all)
10 (256 blocks, protected all)
11 (256 blocks, protected all)
12 (256 blocks, protected all)
13 (256 blocks, protected all)
14 (256 blocks, protected all)
15 (256 blocks, protected all)
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REV. 1.0, DEC. 08, 2014
MX25L12850F
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command),
and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security
OTP command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 8. Security Register Definition" for security
register bit definition and "Table 2. 4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured
OTP mode, array access is not allowed.
Table 2. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxx000~xxx00F
128-bit
ESN (electrical serial number)
xxx010~xxx1FF
3968-bit
N/A
P/N: PM2039
11
Customer Lock
Determined by customer
REV. 1.0, DEC. 08, 2014
MX25L12850F
7. Memory Organization
Table 3. Memory Organization
Block(64K-byte) Block(32K-byte)
Sector
253
506
5
2
4
3
1
2
1
0
0
…
FF0FFFh
FEF000h
FEFFFFh
…
FF0000h
4079
FE8000h
FE8FFFh
4071
FE7000h
FE7FFFh
…
4072
FE0000h
FE0FFFh
4063
FDF000h
FDFFFFh
…
4064
4056
FD8000h
FD8FFFh
4055
FD7000h
FD7FFFh
4048
FD0000h
FD0FFFh
47
02F000h
02FFFFh
…
507
4080
…
508
FF7FFFh
40
028000h
028FFFh
39
027000h
027FFFh
…
254
FF8FFFh
FF7000h
32
020000h
020FFFh
31
01F000h
01FFFFh
…
509
FF8000h
4087
24
018000h
018FFFh
23
017000h
017FFFh
…
510
4088
16
010000h
010FFFh
15
00F000h
00FFFFh
…
255
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
0
P/N: PM2039
FFFFFFh
…
511
Address Range
FFF000h
…
4095
12
REV. 1.0, DEC. 08, 2014
MX25L12850F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD,
RDSFDP, RES, REMS, RDCR the shifted-in instruction sequence is followed by a data-out sequence. After
any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE,
BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, SUSPEND, RESUME, NOP, RSTEN, RST the CS#
must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM2039
13
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 2. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 3. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
P/N: PM2039
tSHQZ
ADDR.LSB IN
14
REV. 1.0, DEC. 08, 2014
MX25L12850F
9. COMMAND DESCRIPTION
Table 4. Command Set
Read/Write Array Commands
Command
(byte)
READ
(normal read)
FAST READ
(fast read data)
Address Bytes
1st byte
3
03 (hex)
3
0B (hex)
2nd byte
ADD1
3rd byte
ADD2
4th byte
ADD3
5th byte
2READ
DREAD
(1I 2O read)
4READ
(4 I/O read)
QREAD
(1I 4O read)
3
BB (hex)
3
3B (hex)
3
EB (hex)
3
6B (hex)
ADD1
ADD1
ADD1
ADD1
ADD1
ADD2
ADD2
ADD2
ADD2
ADD2
(2 x I/O read
command)
ADD3
ADD3
ADD3
ADD3
ADD3
Dummy (8)
Dummy (4)
Dummy (8)
Dummy (6)
Dummy (8)
n bytes read out
until CS# goes
high
n bytes read out
by 2 x I/O until
CS# goes high
n bytes read out
by Dual output
until CS# goes
high
n bytes read out
by 4 x I/O until
CS# goes high
n bytes read out
by Quad output
until CS# goes
high
3
BE 32K
(block erase
32KB)
3
BE
(block erase
64KB)
3
20 (hex)
52 (hex)
D8 (hex)
Data Cycles
Action
n bytes read out
until CS# goes
high
Command
(byte)
PP
(page program)
Address Bytes
3
4PP
(quad page
program)
3
1st byte
02 (hex)
38 (hex)
SE
(sector erase)
2nd byte
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
1-256
quad input to
program the
selected page
to erase the
selected sector
to erase the
selected 32K
block
to erase the
selected block
CE
(chip erase)
0
60 or C7 (hex)
5th byte
Data Cycles
Action
P/N: PM2039
1-256
to program the
selected page
15
to erase whole
chip
REV. 1.0, DEC. 08, 2014
MX25L12850F
Register/Setting Commands
Command
(byte)
1st byte
WREN
WRDI
(write enable) (write disable)
06 (hex)
04 (hex)
RDSR
(read status
register)
RDCR
(read
configuration
register)
WRSR
(write status/
configuration
register)
05 (hex)
15 (hex)
01 (hex)
2nd byte
Values
3rd byte
Values
PGM/ERS
Suspend
(Suspends
Program/
Erase)
B0 (hex)
PGM/ERS
Resume
(Resumes
Program/
Erase)
30 (hex)
4th byte
5th byte
Data Cycles
Action
sets the (WEL)
resets the
to read out the to read out the
write enable
(WEL) write
values of the values of the
latch bit
enable latch bit status register configuration
register
Command
(byte)
DP (Deep
power down)
1st byte
B9 (hex)
RDP (Release
from deep
power down)
AB (hex)
enters deep
power down
mode
release from
deep power
down mode
1-2
to write new
values of the
status/
configuration
register
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
P/N: PM2039
16
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MX25L12850F
ID/Security Commands
1st byte
REMS
RDID
RES
(read electronic
(read identific- (read electronic
manufacturer &
ation)
ID)
device ID)
0
0
0
9F (hex)
AB (hex)
90 (hex)
2nd byte
x
3rd byte
x
x
ADD2
4th byte
x
ADD1 (Note 1)
ADD3
Command
(byte)
Address Bytes
x
outputs JEDEC to read out
output the
ID: 1-byte
1-byte Device Manufacturer
Manufacturer
ID
ID & Device ID
ID & 2-byte
Device ID
Address Bytes
WRSCUR
(write security
register)
0
1st byte
2F (hex)
Command
(byte)
ENSO
(enter secured
OTP)
EXSO
(exit secured
OTP)
RDSCUR
(read security
register)
3
5A (hex)
0
B1 (hex)
0
C1 (hex)
0
2B (hex)
ADD1
5th byte
Action
RDSFDP
Dummy (8)
Read SFDP
mode
to enter the
to exit the
4K-bit secured 4K-bit secured
OTP mode
OTP mode
to read value
of security
register
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
P/N: PM2039
to set the lockdown bit as
"1" (once lockdown, cannot
be updated)
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REV. 1.0, DEC. 08, 2014
MX25L12850F
Reset Commands
Command
(byte)
1st byte
NOP
RSTEN
(No Operation) (Reset Enable)
00 (hex)
66 (hex)
RST
(Reset
Memory)
99 (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different
from 1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and AD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the
reset operation will be disabled.
Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)"
represents there are 8 clock cycles for the data in.
P/N: PM2039
18
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, WRSCUR and WRSR, which are intended to change the device content WEL bit should be set
every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Figure 4. Write Enable (WREN) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2039
06h
High-Z
19
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MX25L12850F
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Reset command completion
- WRSCUR command completion
Figure 5. Write Disable (WRDI) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2039
04h
High-Z
20
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MX25L12850F
9-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 5. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 6. Read Identification (RDID) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
9 10
8
13 14 15 16 17 18
28 29 30 31
SCLK
Mode 0
Command
SI
9Fh
Manufacturer Identification
High-Z
SO
7
6
5
2
MSB
1
Device Identification
0 15 14 13
3
2
1
0
MSB
Table 5. ID Definitions
Command Type
RDID
9Fh
RES
ABh
REMS
90h
P/N: PM2039
MX25L12850F
Manufactory ID
C2
Manufactory ID
C2
Memory type
20
Electronic ID
17
Device ID
17
21
Memory density
18
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select (CS#) must remain High for at least tRES1(max), as specified in "Table 16. AC CHARACTERISTICS". Once in
the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
The RDP instruction is only for releasing from Deep Power Down Mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 5. ID
Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction.
Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in
progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
Figure 7. Read Electronic Signature (RES) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Mode 0
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM2039
22
Stand-by Mode
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 8. Release from Deep Power-down (RDP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
tRES1
7
SCLK
Mode 0
Command
SI
SO
ABh
High-Z
Deep Power-down Mode
P/N: PM2039
23
Stand-by Mode
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-5. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes
address. After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge
of SCLK with most significant bit (MSB) first. The Device ID values are listed in "Table 5. ID Definitions". If the onebyte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The
Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 9. Read Electronic Manufacturer & Device ID (REMS) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
MSB
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2039
24
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-6. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Figure 10. Read Status Register (RDSR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2039
3
Status Register Out
25
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MX25L12850F
9-7. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation
is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO.
Figure 11. Read Configuration Register (RDCR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
High-Z
Configuration register Out
7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2039
3
Configuration register Out
26
REV. 1.0, DEC. 08, 2014
MX25L12850F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 12. Program/Erase flow with read array data
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase successfully
Program/erase
another block?
Program/erase fail
Yes
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2039
27
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MX25L12850F
Figure 13. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
Yes
P_FAIL/E_FAIL =1 ?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
Program/erase completed
P/N: PM2039
28
REV. 1.0, DEC. 08, 2014
MX25L12850F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if
it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next
program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL
bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in "Table 1. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register
(WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program
(PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if
Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as
default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, a non-volatile OTP bit which is permanently set to "1". The flash always performs Quad I/O mode.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0".
Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
SRWD (status
register write
protect)
QE
(Quad
Enable)
1=status
register write
disable
1=Quad
Enable
(note 2)
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile
bit
OTP
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Notes:
1. See the "Table 1. Protected Area Sizes".
2. The QE bit is set by factory default, and can not be changed permanently.
P/N: PM2039
29
REV. 1.0, DEC. 08, 2014
MX25L12850F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as
“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.
Table 6. Configuration Register Table
bit7
bit6
bit5
bit4
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
x
x
x
P/N: PM2039
bit3
TB
(top/bottom
selected)
0=Top area
protect
1=Bottom
area protect
(Default=0)
OTP
30
bit2
bit1
bit0
Reserved
Reserved
Reserved
x
x
x
x
x
x
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-8. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in "Table 1. Protected Area Sizes"), but has no effect on
bit1(WEL) and bit0 (WIP) of the status register.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Figure 14. Write Status Register (WRSR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
SO
command
01h
High-Z
Status
Register In
7
6
5
4
3
2
Configuration
Register In
1
0 15 14 13 12 11 10 9
8
MSB
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
P/N: PM2039
31
REV. 1.0, DEC. 08, 2014
MX25L12850F
Software Protected Mode (SPM):
- When SRWD bit=0, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2,
BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected
mode (SPM).
Table 7. Protection Modes
Mode
Software protection
mode (SPM)
Status register condition
SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
SRWD bit=0
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 1.
Protected Area Sizes".
P/N: PM2039
32
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 15. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Verify OK?
No
Yes
WRSR successfully
P/N: PM2039
WRSR fail
33
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-9. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 16. Read Data Bytes (READ) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Mode 0
SI
command
03h
24-Bit Address
23 22 21
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM2039
34
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-10.Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→ 8 dummy cycles→ data out on SO→ to end FAST_READ operation can use CS# to high at
any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 17. Read at Higher Speed (FAST_READ) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
5
6
7
8
9 10
Command
SI
SO
4
28 29 30 31
24-Bit Address
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
P/N: PM2039
3
2
1
0
7
MSB
MSB
35
6
5
4
3
2
1
0
7
MSB
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-11.Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on
SIO0→ 8 dummy cycles on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can use CS#
to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 18. Dual Read Mode Sequence
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
P/N: PM2039
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
39 40 41 42 43 44 45
A1 A0
High Impedance
Dummy Cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
36
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-12.2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte address interleave on SIO1 & SIO0→ 4 dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ
operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 19. 2 x I/O Read Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mode 3
SCLK
Mode 0
Command
SI/SIO0
SO/SIO1
P/N: PM2039
BBh
12 ADD Cycles
Dummy Cycle
Data
Out 1
Data
Out 2
A22 A20 A18
A4 A2 A0
D6 D4 D2 D0 D6 D4 D2 D0
A23 A21 A19
A5 A3 A1
D7 D5 D3 D1 D7 D5 D3 D1
37
Mode 0
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-13.Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,
the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on
SI → 8 dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS#
to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 20. Quad Read Mode Sequence
CS#
0
1
2
3
4
5
6
7
8
…
Command
SIO0
SIO1
SIO2
SIO3
P/N: PM2039
29 30 31 32 33
9
SCLK
6B
…
24 ADD Cycles
A23 A22
…
High Impedance
38 39 40 41 42
A2 A1 A0
Dummy Cycles
Data Data Data
Out 1 Out 2 Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
38
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MX25L12850F
9-14.4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction,
the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end
4READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 21. 4 x I/O Read Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Mode 3
SCLK
Mode 0
Command
6 ADD Cycles
Performance
enhance
indicator (Note 1)
Data
Out 1
Data
Out 2
Data
Out 3
Mode 0
Dummy Cycle
EBh
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3 D7 D3
SIO0
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM2039
39
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-15.Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
The “EBh” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.
Issuing ”FFh” command can also exit enhance mode. The system then will leave performance enhance mode and
return to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→sending 4
READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 3-bytes
random access address.
P/N: PM2039
40
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 22. 4 x I/O Read enhance performance Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Mode 0
Data
Out 2
Data
Out n
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Command
6 ADD Cycles
Data
Out 1
Performance
enhance
indicator (Note 1)
Dummy Cycle
EBh
SIO0
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
Mode 3
SCLK
6 ADD Cycles
Performance
enhance
indicator (Note 1)
Data
Out 1
Data
Out 2
Data
Out n
Mode 0
Dummy Cycle
SIO0
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
P/N: PM2039
41
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-16.Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be issued in 1I/O sequence.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Figure 23. Performance Enhance Mode Reset for Fast Read Quad I/O
Mode Bit Reset
for Quad I/O
CS#
Mode 3
SCLK
P/N: PM2039
０ 1
2
3
4
5
6
Mode ０
7
Mode 3
Mode ０
SIO0
FFh
SIO1
Don’t Care
SIO2
Don’t Care
SIO3
Don’t Care
42
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-17.Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 3. Memory Organization") is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the
address byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (Block Protect Mode), the Sector Erase (SE) instruction will not be executed on the
block.
Figure 24. Sector Erase (SE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
24-Bit Address
Command
20h
A23 A22
A2 A1 A0
MSB
P/N: PM2039
43
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-18.Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32K). Any address of the block (see "Table 3. Memory Organization") is a
valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address
on SI→CS# goes high.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (Block Protect Mode), the Block Erase (BE32K) instruction will not be executed on
the block.
Figure 25. Block Erase 32KB (BE32K) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
Command
24-Bit Address
52h
A23 A22
A2 A1 A0
MSB
P/N: PM2039
44
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-19.Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 3. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the
least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (Block Protect Mode), the Block Erase (BE) instruction will not be executed on the block.
Figure 26. Block Erase (BE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
Command
24-Bit Address
D8h
A23 A22
A2 A1 A0
MSB
P/N: PM2039
45
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-20.Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing,
and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode". The Chip Erase(CE) instruction will not be executed, if one (or
more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".
Figure 27. Chip Erase (CE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
SI
P/N: PM2039
Command
60h or C7h
46
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-21.Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7A0 (The eight least significant address bits) should be set to 0. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (Block Protect Mode), the Page Program (PP) instruction will not be executed.
Figure 28. Page Program (PP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
24-Bit Address
2076
Command
2075
Mode 0
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM2039
5
4
3
2
Data Byte 3
1
0
7
6
5
4
MSB
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
47
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-22.4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". The Quad Page Programming
takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (Block Protect Mode), the Quad Page Program (4PP) instruction will not be executed.
Figure 29. 4 x I/O Page Program (4PP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Mode 0
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
6 Address cycle
A0
4
0
4
0
4
0
4
0
SIO1
A21 A17 A13 A9 A5 A1
5
1
5
1
5
1
5
1
SIO2
A22 A18 A14 A10 A6 A2
6
2
6
2
6
2
6
2
SIO3
A23 A19 A15 A11 A7 A3
7
3
7
3
7
3
7
3
SIO0
P/N: PM2039
Command
38h
A20 A16 A12 A8 A4
48
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-23.Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
Figure 30. Deep Power-down (DP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
tDP
7
SCLK
Mode 0
SI
Command
B9h
Stand-by Mode
P/N: PM2039
49
Deep Power-down Mode
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-24.Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured
OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that after issuing ENSO command user can only access secure OTP region with standard read or program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.
9-25.Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
9-26.Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
9-27.Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO
bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM2039
50
REV. 1.0, DEC. 08, 2014
MX25L12850F
Security Register
The definition of the Security Register bits is as below:
Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to "1",
if the erase operation fails. It will be set to "0", if the last operation is success. Please note that it will not interrupt or
stop any operation in the flash memory.
Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be
set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is
success. Please note that it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is
"0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus­
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP
area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
Reserved
E_FAIL
P_FAIL
Reserved
-
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
-
0=Erase
is not
suspended
1= Erase
suspended
(default=0)
Reserved
Volatile bit
Volatile bit
Reserved
Volatile bit
P/N: PM2039
bit3
bit2
ESB
PSB
(Erase
(Program
Suspend bit) Suspend bit)
51
bit1
bit0
LDSO
Secured OTP
(indicate if
indicator bit
lock-down)
0 = not lock0=Program
down
0 = nonis not
1 = lock-down
factory
suspended
(cannot
lock
1= Program
program/
1 = factory
suspended
erase
lock
(default=0)
OTP)
Non-volatile
Non-volatile
Volatile bit
bit
bit (OTP)
(OTP)
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-28.Program/Erase Suspend/Resume
The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other
operations.
After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode
through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 8. Security Register Definition")
For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 31. Suspend to Read Latency", "Figure 32. Resume to Read Latency" and "Figure 33. Resume to Suspend Latency".
9-29.Erase Suspend
Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode,
the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation.
Reading the sector or Block being erase suspended is invalid.
After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including:
03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, 06h, 04h, 2Bh, 9Fh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 15h)
If the system issues an Erase Suspend command after the sector erase operation has already begun, the device
will not enter Erase-Suspended mode until 20us time has elapsed.
Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state
of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is
cleared to "0" after erase operation resumes.
9-30.Program Suspend
Program suspend allows the interruption of all program operations. After the device has entered ProgramSuspended mode, the system can read any sector(s) or Block(s) except those be­ing programmed by the suspended
program operation. Reading the sector or Block being program suspended is invalid.
After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.
(including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, 06h, 04h, 2Bh, 9Fh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h,
00h, 15h)
Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the
state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB
is cleared to "0" after program operation resumes.
P/N: PM2039
52
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 31. Suspend to Read Latency
CS#
Suspend Command
tPSL / tESL
Read Command
tPSL: Program Latency
tESL: Erase Latency
Figure 32. Resume to Read Latency
tSE / tBE / tPP
CS#
Read Command
Resume Command
Figure 33. Resume to Suspend Latency
tPRS / tERS
CS#
Resume Command
Suspend Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2039
53
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-31.Write-Resume
The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in
Status register will be changed back to “0”.
The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive
CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed
or not. The user may also wait the time lag of tSE, tBE, tPP for Sector-erase, Block-erase or Page-programming.
WREN (command "06") is not required to issue before resume. Resume to another suspend operation requires
latency time of 1ms.
Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be
resume. To restart the write command, disable the "performance enhance mode" is required. After the "performance
enhance mode" is disable, the write-resume command is effective.
9-32.No Operation (NOP)
The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
9-33.Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For details, please refer to "Table 16. AC CHARACTERISTICS" for tREADY.
P/N: PM2039
54
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 34. Software Reset Recovery
Stand-by Mode
66
CS#
99
tRCR
tRCP
tRCE
Mode
Figure 35. Reset Sequence
tSHSL
CS#
SCLK
Mode 3
Mode 3
Mode 0
Mode 0
Command
SIO0
P/N: PM2039
Command
99h
66h
55
REV. 1.0, DEC. 08, 2014
MX25L12850F
9-34.Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC Standard, JESD216A.
Figure 36. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM2039
4
56
6
5
4
3
2
1
0
7
MSB
REV. 1.0, DEC. 08, 2014
MX25L12850F
Table 9. Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
00h
07:00
53h
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
05h
05h
SFDP Major Revision Number
Start from 01h
05h
15:08
01h
01h
Number of Parameter Headers
This number is 0-based. Therefore,
0 indicates 1 parameter header.
06h
23:16
02h
02h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
05h
05h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
10h
10h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
Reserved
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Reserved
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
10h
10h
15h
15:08
01h
01h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
RPMC parameter ID
18h
07:00
03h
03h
Start from 00h
19h
15:08
00h
00h
Start from 01h
1Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
1Bh
31:24
02h
02h
1Ch
07:00
00h
00h
1Dh
15:08
01h
01h
1Eh
23:16
00h
00h
1Fh
31:24
FFh
FFh
First address of Macronix Flash
Parameter table
Reserved
ID number
(RPMC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of RPMC table
Reserved
P/N: PM2039
57
REV. 1.0, DEC. 08, 2014
MX25L12850F
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
Write Enable Instruction
Required for Writing to Volatile
Status Registers
Add (h) DW Add
(Byte)
(Bit)
01:00
01b
0: 1Byte, 1: 64Byte or larger
02
1b
0: not required
1: required 00h to be written to the
status register
03
0b
30h
0: use 50h opcode,
Write Enable Opcode Select for
Note: If target flash status register
Writing to Volatile Status Registers is nonvolatile, then bits 3 and 4
must be set to 00b.
Reserved
Data (h/b)
(Note1)
Contains 111b and can never be
changed
4KB Erase Opcode
31h
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
1b
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
0=not support 1=support
32h
Reserved
Reserved
Flash Memory Density
(1-4-4) Fast Read Number of Wait
0 0110b: 6 dummy clocks
states (Note3)
(1-4-4) Fast Read Number of
010b: 2 mode bits
Mode Bits (Note4)
38h
(1-4-4) Fast Read Opcode
39h
(1-1-4) Fast Read Number of Wait
0 1000b: 8 dummy clocks
states
(1-1-4) Fast Read Number of
000b: Mode Bits not support
Mode Bits
3Ah
(1-1-4) Fast Read Opcode
3Bh
P/N: PM2039
58
Data
(h)
20h
F1h
FFh
07FF FFFFh
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
44h
EBh
08h
6Bh
REV. 1.0, DEC. 08, 2014
MX25L12850F
Description
Comment
(1-1-2) Fast Read Number of Wait
0 1000b: 8 dummy clocks
states
(1-1-2) Fast Read Number of
000b: Mode Bits not supported
Mode Bits
Add (h) DW Add
(Byte)
(Bit)
3Ch
(1-1-2) Fast Read Opcode
3Dh
(1-2-2) Fast Read Number of Wait
0 0100b: 4 dummy clocks
states
(1-2-2) Fast Read Number of
000b: Mode Bits not supported
Mode Bits
3Eh
(1-2-2) Fast Read Opcode
3Fh
(2-2-2) Fast Read
0=not support 1=support
Reserved
(4-4-4) Fast Read
0=not support 1=support
40h
Reserved
Data (h/b)
(Note1)
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
08h
3Bh
04h
BBh
EEh
Reserved
43h:41h
31:08
FFh
FFh
Reserved
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not supported
(2-2-2) Fast Read Number of
000b: Mode Bits not supported
Mode Bits
46h
(2-2-2) Fast Read Opcode
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
Reserved
00h
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
states
Clocks) not supported
(4-4-4) Fast Read Number of
000b: Mode Bits not supported
Mode Bits
4Ah
(4-4-4) Fast Read Opcode
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
4KB
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
32KB
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
64KB
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM2039
59
00h
REV. 1.0, DEC. 08, 2014
MX25L12850F
Description
Multiplier for Sector/Chip Erase
Time (Maximum)
Comment
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
Multiplier value: 0h~Fh (0~15)
Max. time = 2 * (Multiplier + 1) *
Typical Time
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Sector Type 1 Erase Time (Typical) Units
00: 1ms, 01: 16ms
10b: 128ms, 11b: 1s
Sector Type 2 Erase Time (Typical) Units
00: 1ms, 01: 16ms
10b: 128ms, 11b: 1s
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
00: 1 ms, 01: 16 ms
10b: 128ms, 11b: 1s
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
57h:56h
Sector Type 4 Erase Time (Typical) Units
00: 1ms, 01: 16ms
10b: 128 ms, 11b: 1 s
Multiplier value: 0h~Fh (0~15)
Multiplier for Page/Byte Program
Max. time = 2 * (Multiplier + 1)
Time (Maximum)
*Typical Time
Page size = 2^N bytes
Page Program Size
2^8 = 256 bytes, 8h = 1000b
Page Program Time
(Typical)
Byte Program Time, First Byte
(Typical)
Byte Program Time, Additional
Byte
(Typical)
P/N: PM2039
58h
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Units
0: 8us, 1: 64us
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * Units
Units
0: 1us, 1: 8us
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * Units
Units
0: 1us, 1: 8us
60
0010b
08:04
0 0011b
55h:54h
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Sector Type 3 Erase Time (Typical) Units
03:00
5Ah:59h
Data
(h)
7232h
10:09
01b
15:11
0 1110b
17:16
01b
22:18
1 1101b
24:23
01b
29:25
0 0000b
31:30
00b
03:00
0010b
07:04
1000h
12:08
0 0101b
13
1b
17:14
1000b
18
0b
22:19
1000b
23
0b
00F5h
82h
4225h
REV. 1.0, DEC. 08, 2014
MX25L12850F
Description
Chip Erase Time
(Typical)
Reserved
Prohibited Operations During
Program Suspend
Prohibited Operations During
Erase Suspend
Reserved
Program Resume to Suspend
Interval (Typical)
Program Suspend Latency
(Max.)
Erase Resume to Suspend
Interval (Typical)
Erase Suspend Latency
(Max.)
Suspend / Resume supported
Program Resume Instruction
Program Suspend Instruction
Erase Resume Instruction
Erase Suspend Instruction
P/N: PM2039
Comment
Add (h) DW Add
(Byte)
(Bit)
Count value: 00h~1Fh (0~31)
Typical Time = (Count + 1) * Units
Units
5Bh
00: 16ms, 01: 256ms
10: 4s, 11: 64s
Reserved: 1b
xxx0b: May not initiate a new erase

anywhere
xx0xb: May not initiate a new page

program anywhere
x1xxb: May not initiate a read in

the program suspended
page size
1xxxb: The erase and program

restrictions in bits 1:0 are
sufficient
xxx0b: May not initiate a new erase 5Ch

anywhere
xx1xb: May not initiate a page

program in the erase
suspended sector size
x1xxb: May not initiate a read in

the erase suspended sector
size
1xxxb: The erase and program

restrictions in bits 5:4 are
sufficient
Reserved: 1b
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * 64us
Count value: 00h~1Fh (0~31)
Maximum Time = (Count + 1) * Units 5Eh:5Dh
Units
00: 128ns, 01: 1us
10: 8us, 11: 64us
Count value: 0h~Fh (0~15)
Typical Time = (Count + 1) * 64us
Count value: 00h~1Fh (0~31)
Maximum Time = (Count + 1) * Units
Units
5Fh
00: 128ns, 01: 1us
10: 8us, 11: 64us
0= Support 1= Not supported
Instruction to Resume a Program
60h
Instruction to Suspend a Program
61h
Instruction to Resume Write/Erase
62h
Instruction to Suspend Write/Erase
63h
61
Data (h/b)
(Note1)
28:24
1 0011b
30:29
10b
31
1b
03:00
1100b
Data
(h)
D3h
CCh
07:04
1100b
08
1b
12:09
1111b
17:13
1 0011b
19:18
01b
23:20
1111b
28:24
1 0011b
30:29
01b
31
07:00
15:08
23:16
31:24
0b
30h
B0h
30h
B0h
F67Fh
33h
30h
B0h
30h
B0h
REV. 1.0, DEC. 08, 2014
MX25L12850F
Description
Comment
Reserved
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
01:00
11b
Reserved: 11b
Bit 2: Read WIP bit [0] by 05h Read

instruction
64h
Status Register Polling Device
Bit 3: Read bit 7 of Status Register

Busy
by 70h Read instruction
(0=not support 1=support)
Bit 07:04, Reserved: 1111b

Count value: 00h~1Fh (0~31)
Release from Deep Power-down Maximum Time = (Count + 1) * Units
Units
(RDP) Delay
00: 128ns, 01: 1us
(Max.)
10: 8us, 11: 64us
67h:65h
Release from Deep Power-down
Instruction to Exit Deep Power Down
(RDP) Instruction
Enter Deep Power Down
Instruction to Enter Deep Power
Instruction
Down
Deep Power Down Supported
0: Supported 1: Not supported
Supported Methods to Reset QPI
4-4-4 Mode Disable Sequences Mode
xx1xb: issue F5h instruction

Supported methods to enter QPI
mode
4-4-4 Mode Enable Sequences
x_x1xxb: issue instruction 35h

1_xxxxb: Reserved

Performance Enhance Mode,
0-4-4 mode Supported
Continuous Read, Execute in Place
69h:68h
0: Not supported 1: Supported
Exit Performance Enhance Mode
xx_xxx1b: Mode Bits[7:0] = 00h will

terminate this mode at
the end of the current
0-4-4 Mode Exit Method
read peration.
xx_x1xxb: Reserved

x1_xxxxb: Reserved

1x_xxxxb: Reserved

Enter Performance Enhance Mode
xxx1b: Mode Bits[7:0] = A5h Note:

QE must be set prior to
0-4-4 Mode Entry Method
using this mode
x1xxb: Reserved

6Ah
1xxxb: Reserved

010b: QE is bit 6 of Status Register.

Quad Enable (QE) bit
where 1=Quad Enable or
Requirements
0=not Quad Enable
HOLD and WP Disable by bit 4 of
0: Not supported
Extended Configuration Register
Reserved
P/N: PM2039
6Bh
62
07:02
1111 01b
12:08
0 0011b
14:13
10b
22:15
30:23
31
Data
(h)
F7h
1010 1011b 5CD5C3h
(ABh)
1011 1001
(B9h)
0b
03:00
0000b
08:04
1 0000b
09
1b
15:10
11 1111b
19:16
1101h
FF00h
2Dh
22:20
010b
23
0b
31:24
FFh
FFh
REV. 1.0, DEC. 08, 2014
MX25L12850F
Description
Volatile or Non-Volatile Register
and Write Enable Instruction for
Status Register 1
Comment
xxx_xxx1b: Non-Volatile Status

Register 1, powers-up
to last written value,
use instruction 06h to
enable write
x1x_xxxxb: Reserved

1xx_xxxxb: Reserved

Add (h) DW Add
(Byte)
(Bit)
6Ch
Reserved
Return the device to its default
power-on state
Soft Reset and Rescue Sequence 
x1_xxxxb: issue reset enable
Support
instruction 66h, then
issue reset instruction
99h.
xx_xxxx_xxx1b: issue instruction

E9h to exit 4-Byte
address mode (write
enable instruction 06h is
not required)
xx_xxxx_x1xxb: 8-bit volatile

extended address
register used to define
A[31:A24] bits. Read
with instruction C8h.
Write instruction is C5h,
Exit 4-Byte Addressing
data length is 1 byte.
Return to lowest memory
segment by setting
A[31:24] to 00h and use
3-Byte addressing.
xx_xx1x_xxxxb: Hardware reset

xx_x1xx_xxxxb: Software reset (see

bits 13:8 in this DWORD)
xx_1xxx_xxxxb: Power cycle

x1_xxxx_xxxxb: Reserved

1x_xxxx_xxxxb: Reserved

P/N: PM2039
63
6Dh
6Eh
Data (h/b)
(Note1)
06:00
110 0001b
07
1b
13:08
11 0000b
15:14
00b
23:16
1100 0000b
Data
(h)
E1h
30h
C0h
REV. 1.0, DEC. 08, 2014
MX25L12850F
Description
Enter 4-Byte Addressing
P/N: PM2039
Comment
xxxx_xxx1b: issue instruction B7h

(preceding write enable
not required)
xxxx_x1xxb:
8-bit volatile extended

address register used
to define A[31:24] bits.
Read with instruction
C8h. Write instruction
is C5h with 1 byte of
data. Select the active
128 Mbit memory
segment by setting the
appropriate A[31:24]
bits and use 3-Byte
addressing.
xx1x_xxxxb: Supports dedicated

4-Byte address
instruction set. Consult
vendor data sheet
for the instruction set
definition.
1xxx_xxxxb: Reserved

64
Add (h) DW Add
(Byte)
(Bit)
6Fh
31:24
Data (h/b)
(Note1)
Data
(h)
1000 0000b
80h
REV. 1.0, DEC. 08, 2014
MX25L12850F
Table 11. RPMC Parameter
Description
Flash_Hardening
MC_Size
Busy_Polling_Method :
Comment
0= Flash Hardening is supported.
1=Flash Hardening is not supported
0= Monotonic counter size is 32 bit
1= Reserved
0= Poll for OP1 busy using
OP2 Extended Status[0]
1= Poll for OP1 busy using Status
Add (h)
(Byte)
100h
Reserved
Num_Counter-1:
Number of supported counters-1.
DW Add Data (h/b)
(Bit)
(Note1)
00
0b
01
0b
02
1b
03
1b
07:04
0011b
Data
(h)
3Ch
OP1 Opcode
101h
15:08
9Bh
9Bh
OP2 Opcode
102h
23:16
96h
96h
27:24
0000b
31:28
Fh
04:00
00101b
06:05
10b
07
1b
12:08
00100b
14:13
01b
15
1b
20:16
00010b
22:21
10b
23
1b
31:24
FFh
Update_Rate
: Rate of Update = 5 * (2 ^ Update_
Rate) seconds
Reserved
: Must be 0FH
Read Counter Polling Delay
Typical case to calculate HMAC
two times
103h
0 : polling delay_read counter
units (00=1us, 01=16us, 10=128us,
11=1ms)
104h
reserved
0 : polling_short_delay_write_
counter
units
(00=1us, 01=16us, 10=128us,
Write Counter Polling Short Delay
11=1ms)
105h
reserved
Bits4:0 : polling_long_delay_write_
counter
Bits
6:5 : units (00=1ms,
Write Counter Polling Long Delay
01=16ms,10=128ms, 11= 1s)
106h
Bit 7 : reserved
Reserved
P/N: PM2039
: Must be FF
107h
65
F0h
C5h
A4h
C2h
FFh
REV. 1.0, DEC. 08, 2014
MX25L12850F
Table 12. Parameter Table (1): Macronix Flash Parameter Tables
Description
Comment
Add (h) DW Add Data (h/b)
(Bit)
(Note1)
(Byte)
Data
(h)
Vcc Supply Maximum Voltage
2000h=2.000V
2700h=2.700V
3600h=3.600V
111h:110h
07:00
15:08
00h
36h
00h
36h
Vcc Supply Minimum Voltage
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
113h: 112h
23:16
31:24
00h
27h
00h
27h
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
01
0b
Deep Power Down Mode
0=not support 1=support
02
1b
S/W Reset
0=not support 1=support
03
1b
S/W Reset Opcode
Reset Enable (66h) should be
issued before Reset Opcode
Program Suspend/Resume
0=not support 1=support
12
1b
Erase Suspend/Resume
0=not support 1=support
13
1b
14
1b
15
0b
116h
23:16
FFh
FFh
117h
31:24
FFh
FFh
115h: 114h
Reserved
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
11:04
1001 1001b 799Ch
(99h)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
0b
09:02
FFh
10
0b
11
1b
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Reserved
15:14
11b
Reserved
31:16
FFh
FFh
Reserved
11Fh: 11Ch 31:00
FFh
FFh
P/N: PM2039
66
11Bh: 118h
CBFCh
REV. 1.0, DEC. 08, 2014
MX25L12850F
Note 1:h/b is hexadecimal or binary.
Note 2:(x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3:Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4:Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5:4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6:All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM2039
67
REV. 1.0, DEC. 08, 2014
MX25L12850F
10. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
Please refer to the "Figure 43. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
P/N: PM2039
68
REV. 1.0, DEC. 08, 2014
MX25L12850F
11. ELECTRICAL SPECIFICATIONS
Table 13. ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 4.0V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 37, and Figure 38.
Figure 38. Maximum Positive Overshoot Waveform
Figure 37. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
Table 14. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2039
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
69
Conditions
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 39. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC
Measurement
Level
0.8V
0.2VCC
0.5VCC
Note: Input pulse rise and fall time are <2.4ns
Figure 40. OUTPUT LOADING
25K ohm
DEVICE UNDER
TEST
CL
+3.0V
25K ohm
CL=30pF Including jig capacitance
P/N: PM2039
70
REV. 1.0, DEC. 08, 2014
MX25L12850F
Table 15. DC CHARACTERISTICS
(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VOUT = VCC or GND
ISB1
VCC Standby Current
1
10
60
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
3
20
uA
VIN = VCC or GND,
CS# = VCC
ICC1
VCC Read
1
10
17
mA
f=84MHz, (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
1
15
25
mA
15
20
mA
1
15
25
mA
Erase in Progress,
CS#=VCC
1
15
25
mA
Erase in Progress,
CS#=VCC
-0.5
0.8
V
0.7VCC
VCC+0.4
V
0.2
V
IOL = 100uA
V
IOH = -100uA
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector/Block (32K,
64K) Erase Current
(SE/BE/BE32K)
VCC Chip Erase Current
(CE)
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
VCC-0.2
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM2039
71
REV. 1.0, DEC. 08, 2014
MX25L12850F
Table 16. AC CHARACTERISTICS
(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter
Clock Frequency for all commands (FAST_READ,
fSCLK
fC RDSFDP, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI,
RDID, RDSR, WRSR)
fRSCLK
fR Clock Frequency for READ instructions
Clock Frequency for DREAD, 2READ, QREAD, 4READ
fTSCLK
instructions
Others (fSCLK)
tCH(1)
tCLH Clock High Time
Normal Read (fRSCLK)
Others (fSCLK)
(1)
tCL
tCLL Clock Low Time
Normal Read (fRSCLK)
tCLCH(2)
Clock Rise Time (peak to peak)
tCHCL(2)
Clock Fall Time (peak to peak)
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL
CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
tCHDX
tDH Data In Hold Time
tCHSH
CS# Active Hold Time (relative to SCLK)
tSHCH
CS# Not Active Setup Time (relative to SCLK)
Read
tSHSL tCSH CS# Deselect Time
Write/Erase/Program
tSHQZ(2) tDIS Output Disable Time
Loading: 30pF
Clock Low to Output Valid
tCLQV
tV
Loading: 30pF/15pF
Loading: 15pF
tCLQX
tHO Output Hold Time
tDP(2)
CS# High to Deep Power-down Mode
CS#
High to Standby Mode without Electronic Signature
tRES1(2)
Read
tRES2(2)
CS# High to Standby Mode with Electronic Signature Read
tW
Write Status/Configuration Register Cycle Time
tBP
Byte-Program
tPP
Page Program Cycle Time
tPP(4)
tSE
tBE32
tBE
tCE
tWRK
tUHK
tIMC
tRQMC
tRSL
tRSP
tESL(6)
tPSL(6)
tPRS(7)
tERS(8)
P/N: PM2039
Min.
D.C.
3.3
9
3.3
9
0.1
0.1
5
7
2
3
5
5
7
30
1
Page Program Cycle Time (n bytes)
Sector Erase Cycle Time
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
Write Root Key Time
Update HMAC Key Time
Increment Monotonic Counter Time
Request Monotonic Counter Time
Suspend during OP1 command to suspend ready time
Resume to suspend timing for OP1 command
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
72
0.3
0.3
Typ.
Max.
Unit
104
MHz
54
MHz
84
MHz
10
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
30
us
30
40
50
1.2
us
ms
us
ms
8
8
6
10
0.33
0.008+
1.2
(nx0.004) (5)
25
200
140
600
250
1000
40
120
180
510
315
445
0.045
300
65
105
20
1
20
20
1000
1000
ms
ms
ms
ms
s
us
us
ms
us
us
ms
us
us
us
us
REV. 1.0, DEC. 08, 2014
MX25L12850F
Symbol
tRCR
tRCP
tRCE
Alt. Parameter
Recovery Time from Read
Recovery Time from Program
Recovery Time from Erase
Min.
20
20
12
Typ.
Max.
Unit
us
us
ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Test condition is shown as Figure 39 and Figure 40.
4. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to program the whole 256 bytes or only a few bytes between 1~256 bytes.
5. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.
6. Latency time required to complete Erase/Program Suspend operation until WIP bit is "0".
7. For tPRS, Min. timing is needed to issue next program suspend command. However, a period of time equal to/or
longer than typ. timing is also required to complete the program progress.
8. For tERS, Min. timing is needed to issue next erase suspend command. However, a period of time equal to/or
longer than typ. timing is also required to complete the erase progress.
P/N: PM2039
73
REV. 1.0, DEC. 08, 2014
MX25L12850F
12. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 41. AC Timing at Device Power-Up" and "Figure 42. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 41. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 16. AC CHARACTERISTICS".
P/N: PM2039
74
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 42. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 43. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
P/N: PM2039
75
REV. 1.0, DEC. 08, 2014
MX25L12850F
Figure 44. Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing. Please
check the table below for more detail.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
VPWD (max.)
tPWD
Time
Table 17. Power-Up/Down Voltage and Timing
Symbol
tVSL
VWI
VPWD
tPWD
tVR
VCC
Parameter
VCC(min.) to device operation
Write Inhibit Voltage
VCC voltage needed to below VPWD for ensuring initialization will occur
The minimum duration for ensuring initialization will occur
VCC Rise Time
VCC Power Supply
Min.
800
1.5
300
20
2.7
Max.
2.5
0.9
500000
3.6
Unit
us
V
V
us
us/V
V
Note: These parameters are characterized only.
12-1.INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 40h (all Status Register bits are 0, , except QE bit: QE=1).
P/N: PM2039
76
REV. 1.0, DEC. 08, 2014
MX25L12850F
13. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (1)
Min.
Max. (2)
Unit
40
ms
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
25
200
ms
Block Erase Cycle Time (32KB)
0.14
0.6
s
Block Erase Cycle Time (64KB)
0.25
1
s
Chip Erase Cycle Time
40
120
s
Byte Program Time (via page program command)
10
50
us
0.33
1.2
ms
Page Program Time
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and all zero pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cycle with 90% confidence level.
14. DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
15. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
-1.0V
2 VCCmax
Input Voltage with respect to GND on SO
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM2039
77
REV. 1.0, DEC. 08, 2014
MX25L12850F
16. ORDERING INFORMATION
PART NO.
CLOCK (MHz)
TEMPERATURE
PACKAGE
MX25L12850FM2I-10G
104
-40°C~85°C
8-SOP (200mil)
MX25L12850FZNI-10G
104
-40°C~85°C
8-WSON (6x5mm)
MX25L12850FPI-10G
104
-40°C~85°C
8-PDIP (300mil)
P/N: PM2039
78
Remark
REV. 1.0, DEC. 08, 2014
MX25L12850F
17. PART NAME DESCRIPTION
MX 25
L
12850F M2
I
10 G
OPTION:
G: RoHS Compliant & Halogen-free
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M2: 8-SOP (200mil)
ZN: 8-WSON (6x5mm)
P: 8-PDIP (300mil)
DENSITY & MODE:
12850F: 128Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM2039
79
REV. 1.0, DEC. 08, 2014
MX25L12850F
18. PACKAGE INFORMATION
P/N: PM2039
80
REV. 1.0, DEC. 08, 2014
MX25L12850F
P/N: PM2039
81
REV. 1.0, DEC. 08, 2014
MX25L12850F
P/N: PM2039
82
REV. 1.0, DEC. 08, 2014
MX25L12850F
19. REVISION HISTORY
Revision No. Description
1.0
1. Removed "Advanced Information"
2. Modified Support fast clock frequency for read operation
3. Added parameters name for Suspend/Resume
4. Updated AC/DC and VWI values (Removed tWREAW)
and updated Sector Erase Cycle Time
5. Content correction
P/N: PM2039
83
Page
Date
All
DEC/08/2014
P4,72
P52,53,72,73
P71,72,76,77
P13,55,70,76
REV. 1.0, DEC. 08, 2014
MX25L12850F
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2014. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit,
Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au­dio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
84