MX29F400C T/B 4M-BIT [512K x 8 / 256K x 16] SINGLE VOLTAGE 5V ONLY FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 4.5 to 5.5 volt for read, erase, and program operations • 524,288 x 8 / 262,144 x 16 switchable • Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • Sector Structure - 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 7 • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotected allows code changes in previously locked sectors • Latch-up protected to 100mA from -1V to Vcc + 1V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE • High Performance - Access time: 70/90ns - Byte/Word program time: 9us/11us (typical) - Erase time: 0.7s/sector, 4s/chip (typical) • Low Power Consumption - Low active read current: 40mA (maximum) at 5MHz - Low standby current: 1uA (typical) • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode PACKAGE • 44-Pin SOP • 48-Pin TSOP • All devices are RoHS Compliant • All non RoHS Compliant devices are not recommeded for new design in P/N:PM1200 REV. 2.2, NOV. 29, 2010 1 MX29F400C T/B PIN CONFIGURATIONS 44 SOP(500mil) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 MX29F400CT/CB NC RY/BY# A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC 48 TSOP(TYPE I) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29F400C T/B P/N:PM1200 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 REV. 2.2, NOV. 29, 2010 2 MX29F400C T/B PIN DESCRIPTION SYMBOL PIN NAME A0~A17 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE# Chip Enable Input WE# Write Enable Input BYTE# Word/Byte Selection input RESET# Hardware Reset Pin/Sector Protect Unlock OE# Output Enable Input RY/BY# Ready/Busy Output VCC Power Supply Pin (+5V) GND Ground Pin LOGIC SYMBOL 18 A0-A17 Q0-Q15 (A-1) 16 or 8 CE# OE# WE# RESET# BYTE# P/N:PM1200 RY/BY# REV. 2.2, NOV. 29, 2010 3 MX29F400C T/B BLOCK DIAGRAM CE# OE# WE# RESET# BYTE# CONTROL INPUT LOGIC PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER FLASH REGISTER ARRAY ARRAY Y-DECODER AND STATE X-DECODER ADDRESS A0-AM WRITE Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER AM: MSB address P/N:PM1200 REV. 2.2, NOV. 29, 2010 4 MX29F400C T/B Table 1. SECTOR STRUCTURE MX29F400CT TOP BOOT SECTOR ADDRESS TABLE Sector A17 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 1 1 1 1 1 1 1 A16 A15 A14 A13 A12 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X 0 1 1 1 X X X X X X X X 0 0 1 X X X X X X X X 0 1 X Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address Range (in hexadecimal) (x8) (x16) Address Range Address Range 00000h-0FFFFh 00000h-07FFFh 10000h-1FFFFh 08000h-0FFFFh 20000h-2FFFFh 10000h-17FFFh 30000h-3FFFFh 18000h-1FFFFh 40000h-4FFFFh 20000h-27FFFh 50000h-5FFFFh 28000h-2FFFFh 60000h-6FFFFh 30000h-37FFFh 70000h-77FFFh 38000h-3BFFFh 78000h-79FFFh 3C000h-3CFFFh 7A000h-7BFFFh 3D000h-3DFFFh 7C000h-7FFFFh 3E000h-3FFFFh MX29F400CB BOTTOM BOOT SECTOR ADDRESS TABLE Sector A17 A16 A15 A14 A13 A12 Sector Size Address Range (in hexadecimal) (Kbytes/ (x8) (x16) Kwords) Address Range Address Range SA0 0 0 0 0 0 X 16/8 00000h-03FFFh 00000h-01FFFh SA1 0 0 0 0 1 0 8/4 04000h-05FFFh 02000h-02FFFh SA2 0 0 0 0 1 1 8/4 06000h-07FFFh 03000h-03FFFh SA3 0 0 0 1 X X 32/16 08000h-0FFFFh 04000h-07FFFh SA4 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh SA5 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh SA6 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh SA7 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh SA8 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh SA9 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh SA10 1 1 1 X X X 64/32 70000h-7FFFFh 38000h-3FFFFh Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode. P/N:PM1200 REV. 2.2, NOV. 29, 2010 5 MX29F400C T/B Table 2. BUS OPERATION Mode Pins CE# Read Silicon ID Manufacture Code Read Silicon ID OE# WE# RESET# A0 A1 A6 A9 Q0 ~ Q15 L L H H L L X Vhv X Vhv C2H (Byte mode) 00C2H (Word mode) 23H/ABH (Byte mode) Device Code Read Standby Output Disable Write Sector Protect Chip Unprotect Ve r i f y S e c t o r P r o t e c t / L L H H H L L H L L L L L L X H H H H L H X H L L L H H H H H Vhv Vhv H A0 X X A0 L L L A1 X X A1 H H H A6 A9 X X X X A6 A9 L X H X L Vhv 2223H/22ABH (Word mode) DOUT HIGH Z HIGH Z DIN DIN DIN Code(4) Unprotect Reset X X X L X X X HIGH Z X Notes: 1. Vhv is the very high voltage, 11.5V to 12.5V. 2. X means input high (Vih) or input low (Vil). 3. SA means sector address: A12~A17. 4. Code=00H/XX00H means unprotected. Code=01H/XX01H means protected. P/N:PM1200 REV. 2.2, NOV. 29, 2010 6 MX29F400C T/B REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array out. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped after a period of time no more than Treadyand the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory. P/N:PM1200 REV. 2.2, NOV. 29, 2010 7 MX29F400C T/B SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on these sectors. MX29F400C T/B provides one method for sector protection. Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details. This method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the algorithm for this method. CHIP UNPROTECT OPERATION MX29F400C T/B provides one method for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector are unprotected when shipped from the factory. This method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for algorithm of the operation. TEMPORARY SECTOR UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. AUTOMATIC SELECT OPERATION When the device is in Read array mode or erase-suspended read array mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE# and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. P/N:PM1200 REV. 2.2, NOV. 29, 2010 8 MX29F400C T/B VERIFY SECTOR PROTECT STATUS OPERATION MX29F400C T/B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to A17 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is still not being protected. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29F400C T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1200 REV. 2.2, NOV. 29, 2010 9 MX29F400C T/B TABLE 3. MX29F400C T/B COMMAND DEFINITIONS Read Mode Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Hex Addr Data Addr Data Addr Data 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle XXX F0 Manufacturer ID Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 Automatic Select Device ID Word 555 AA 2AA 55 555 90 Byte AAA AA 555 55 AAA 90 Addr X00 X00 X01 X02 Data 00C2 C2 ID ID Program Sector Protect Verify Word Byte Word Byte 555 AAA 555 AAA AA AA AA AA 2AA 555 2AA 555 55 55 55 55 555 AAA 555 AAA 90 90 A0 A0 (Sector) (Sector) Addr Addr X02 X04 XX00/ 00/01 Data Data XX01 Addr Data Addr Data Command 1st Bus Cycle Addr Data Reset Mode Sector Erase Hex Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Word 555 AA 2AA 55 555 80 555 AA 2AA 55 Sector 30 Byte AAA AA 555 55 AAA 80 AAA AA 555 55 Sector 30 Erase Suspend Erase Resume Sector B0 Sector 30 Chip Erase Word 555 AA 2AA 55 555 80 Byte AAA AA 555 55 AAA 80 555 AAA AA AA 2AA 55 555 10 555 55 AAA 10 Sector Protect Word XXX 60 Sector 60 Sector 40 Sector 00/01 Byte XXX 60 Sector 60 Sector 40 Sector 00/01 Notes: 1. Device ID: 2223H/23H for Top Boot Sector device. 22ABH/ABH for Bottom Boot Sector device. 2. For sector protect verify result, XX00H/00H means sector is not protected, XX01H/01H means sector has been protected. 3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc is for protect verify. 4.It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1200 REV. 2.2, NOV. 29, 2010 10 MX29F400C T/B RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode or sector protect verify mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Manufacturer ID Device ID Sector Protect Verify Address Data (Hex) Representation Word X00 00C2 Byte X00 C2 Word X01 2223/22AB Top/Bottom Boot Sector Byte X02 23/AB Top/Bottom Boot Sector Word (Sector address) X 02 00/01 Unprotected/protected Byte (Sector address) X 04 00/01 Unprotected/protected There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1200 REV. 2.2, NOV. 29, 2010 11 MX29F400C T/B AUTOMATIC PROGRAMMING The MX29F400C T/B can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. With the internal write state controller, the device requires the user to write the program command and data only. The typical chip program time at room temperature of the MX29F400C T/B is 3 seconds. (Word-Mode) When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 RY/BY#*2 In progress*1 Q7# Toggling 0 0 Finished Q7 Stop toggling 0 1 Exceed time limit Q7# Toggling 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us and the device returns to read array state without programing the data in the protected sector. P/N:PM1200 REV. 2.2, NOV. 29, 2010 12 MX29F400C T/B CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q2 RY/BY# In progress 0 Toggling 0 Toggling 0 Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 Toggling 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2 Time-out period 0 Toggling 0 0 Toggling 0 In progress 0 Toggling 0 1 Toggling 0 Finished 1 Stop toggling 0 1 1 1 Exceed time limit 0 Toggling 1 1 Toggling 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us and the device returned to read array status without erasing the data in the protected sector. P/N:PM1200 REV. 2.2, NOV. 29, 2010 13 MX29F400C T/B SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1(<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Erase suspend read in erase suspended sector Erase suspend read in non-erase suspended sector Q7 Q6 Q5 Q3 Q2 RY/BY# 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 Toggle 0 N/A N/A 0 Erase suspend program in non-erase suspended sector Q7# When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1200 REV. 2.2, NOV. 29, 2010 14 MX29F400C T/B ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Voltage Range Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . -0.5V to +7.0 V RESET#, A9............ .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .-0.5V to +13.5 V The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to Vcc +0.7 V Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Note: 1. Mininum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC+2V during transition and for less than 20ns during transitions. OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . 0°C to +70°C Industrial (I) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . -40°C to +85°C VCC Supply Voltages VCC range. . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . +4.5V to 5.5V P/N:PM1200 REV. 2.2, NOV. 29, 2010 15 MX29F400C T/B DC CHARACTERISTICS Symbol Description Min Typ Max Remark Iilk Input Leak ± 1.0uA Iolk Output Leak 10uA Icr1 Read Current (10MHz) 50mA CE#=Vil, OE#=Vih Icr2 Read Current (5MHz) 40mA CE#=Vil, OE#=Vih Isb1 Standby Current (TTL) 1mA Vcc=Vcc max, CE#=Vih other pin disabled Isb2 Standby current (CMOS) 1uA 5uA Vcc=Vcc max, CE#=vcc +0.3V, other pin disabled Icw Write Current 15mA 30mA CE#=Vil, OE#=Vih WE#=Vil Vil Input Low Voltage -0.3V 0.8V Vih Input High Voltage 0.7xVcc Vcc+0.3V Vhv Very High Voltage for hardware Protect/ Unprotect/Auto Select/Temporary Unprotect Vol Output Low Voltage 11.5V 12V 12.5V 0.45V Voh1 Ouput High Voltage (TTL) 2.4V Voh2 Ouput High Voltage (CMOS) Vcc-0.4V P/N:PM1200 Iol=2.1mA, Vcc=Vcc min Ioh1=-2mA Ioh2=-100uA REV. 2.2, NOV. 29, 2010 16 MX29F400C T/B SWITCHING TEST CIRCUITS Vcc R2 TESTED DEVICE 0.1uF R1 CL Vcc DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 100PF for 90ns ; 30PF for 70ns Rise/Fall Times : 10ns Input pulse levels: 0.45V/0.7xVcc Reference levels for measuring timing :0.8V, 2.0V SWITCHING TEST WAVEFORMS 0.7xVCC 2.0V 2.0V TEST POINTS 0.45V 0.8V 0.8V INPUT OUTPUT P/N:PM1200 REV. 2.2, NOV. 29, 2010 17 MX29F400C T/B AC CHARACTERISTICS Speed Option -70/90 Symbol Description Min Typ Max Unit Taa Valid data output after address 70/90 ns Tce Valid data output after CE# low 70/90 ns Toe Valid data output after OE# low 30/35 ns Tdf Data output floating after OE# high 20 ns Toh Output hold time from the earliest rising edge of Addrss, CE#, OE# Trc 0 ns Read period time 70/90 ns Twc Write period time 70/90 ns Tcwc Command write period time 70/90 ns Tas Address setup time 0 ns Tah Address hold time 45 ns Tds Data setup time 30/45 ns Tdh Data hold time 0 ns Tvcs Vcc setup time 50 us Tcs CE# Setup time 0 ns Tch CE# hold time 0 ns Toes OE# setup time 0 ns Toeh Output enable hold time Read 0 ns Toggle & Data# Polling 10 ns Tcep CE# pulse width 35/45 ns Tceph CE# pulse width high 20 ns Twp WE# pulse width 35 ns Twph WE# pulse width high 30 ns Tghwl Read recover time before write 0 ns Tbusy Program/Erase active time by RY/BY# 90 ns Tavt Program operation Byte 9 300 us Tavt Program operation Word 11 360 us Taetc Chip Erase Operation 4 32 sec Taetb Sector Erase Operation 0.7 8 sec Tbal Sector Address hold time 50 us P/N:PM1200 REV. 2.2, NOV. 29, 2010 18 MX29F400C T/B Figure 1. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Data Vih Vil DIN VA: Valid Address P/N:PM1200 REV. 2.2, NOV. 29, 2010 19 MX29F400C T/B READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS CE# Tce Vih Vil Vih WE# OE# Vil Tdf Toe Vih Vil Toh Taa Trc Vih Addresses Outputs ADD Valid Vil Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1200 REV. 2.2, NOV. 29, 2010 20 MX29F400C T/B AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 0 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write MAX 20 us Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write MAX 500 ns Figure 3. RESET# TIMING WAVEFORM Trb1 CE#, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1200 REV. 2.2, NOV. 29, 2010 21 MX29F400C T/B ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address 2AAh VA SA Tds Data Read Status Tah Tas Tdh VA In Progress Complete 55h 10h Tbusy Trb RY/BY# SA: 555h for chip erase P/N:PM1200 REV. 2.2, NOV. 29, 2010 22 MX29F400C T/B Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1200 REV. 2.2, NOV. 29, 2010 23 MX29F400C T/B Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Data Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h Tbusy 30h Trb RY/BY# P/N:PM1200 REV. 2.2, NOV. 29, 2010 24 MX29F400C T/B Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1200 REV. 2.2, NOV. 29, 2010 25 MX29F400C T/B Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 NO ERASE SUSPEND not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1200 REV. 2.2, NOV. 29, 2010 26 MX29F400C T/B Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle Address 555h VA PA Tds Data Last 2 Read Status Cycle Tah Tas VA Tdh A0h Status PD Tbusy DOUT Trb RY/BY# P/N:PM1200 REV. 2.2, NOV. 29, 2010 27 MX29F400C T/B Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Twhwh1 or Twhwh2 Tcep CE# Tceph Tghwl OE# Tah Tas Address 555h Tds Data VA PA VA Tdh A0h Status PD DOUT Tbusy RY/BY# P/N:PM1200 REV. 2.2, NOV. 29, 2010 28 MX29F400C T/B Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1200 REV. 2.2, NOV. 29, 2010 29 MX29F400C T/B SECTOR PROTECT/CHIP UNPROTECT Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) 150uS: Sector Protect 15mS: Chip Unprotect 1us CE# WE# OE# Verification Data 60h SA, A6 A1, A0 60h 40h VA VA Status VA Vhv RESET# Vih VA: valid address P/N:PM1200 REV. 2.2, NOV. 29, 2010 30 MX29F400C T/B Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No Retry Count=25? No Data=01h? Yes Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1200 REV. 2.2, NOV. 29, 2010 31 MX29F400C T/B Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No Retry Count=1000? No Data=00h? Yes Device fail Yes Temporary Unprotect Write reset CMD Chip Unprotect Done P/N:PM1200 REV. 2.2, NOV. 29, 2010 32 MX29F400C T/B Table 5. TEMPORARY SECTOR UNPROTECT Parameter Alt Description Condition Speed Unit Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us Figure 14. TEMPORARY SECTOR UNPROTECT WAVEFORMS Program or Erase Command Sequence CE# WE# Tvhhwl RY/BY# Vhv 12V RESET# 0 or 5V 0 or 5V Trpvhh Trpvhh P/N:PM1200 REV. 2.2, NOV. 29, 2010 33 MX29F400C T/B Figure 15. TEMPORARY SECTOR UNPROTECT FLOWCHART Start Apply RESET# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from RESET# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=11.5 ~ 12.5V. 2. The protected conditions of the protected sectors are the same to temporary sector unprotect mode. P/N:PM1200 REV. 2.2, NOV. 29, 2010 34 MX29F400C T/B Figure 16. SILICON ID READ TIMING WAVEFORM CE# Vih Vil Tce Vih WE# Vil Toe Vih OE# Tdf Vil Toh Toh Vhv Vih A9 A0 Vil Vih Vil Taa A1 Taa Vih Vil ADD DATA Q0-Q7 Vih Vil Vih Vil DATA OUT DATA OUT C2H 23H (TOP boot) ABH (Bottom boot) P/N:PM1200 REV. 2.2, NOV. 29, 2010 35 MX29F400C T/B WRITE OPERATION STATUS Figure 17. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Complement Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1200 REV. 2.2, NOV. 29, 2010 36 MX29F400C T/B Figure 18. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) Q7 = Data# ? No Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1200 REV. 2.2, NOV. 29, 2010 37 MX29F400C T/B Figure 19. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# Notes: 1. VA : Valid Address 2. CE# must be toggled when toggle bit toggling. P/N:PM1200 REV. 2.2, NOV. 29, 2010 38 MX29F400C T/B Figure 20. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice (Note1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice (Note1, 2) NO Q6 Toggle ? YES Program/Erase fail Write Reset CMD Program/Erase Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1200 REV. 2.2, NOV. 29, 2010 39 MX29F400C T/B RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup. If the timing in the figure is ignored, the device may not operate correctly. Vcc Vcc(min) GND Tvr Tvcs Tf CE# WE# Tce Vil Vih Vil Tf OE# WP#/ACC Tr Vil Vih Taa Tr or Tf Valid Address Vil Voh DATA Toe Vih Tr or Tf ADDRESS Tr Vih High Z Valid Ouput Vol Vih Vil Figure A. AC Timing at Device Power-Up Symbol Parameter Min. Max. Unit 20 500000 us/V Tvr Vcc Rise Time Tr Input Signal Rise Time 20 us/V Tf Input Signal Fall Time 20 us/V P/N:PM1200 REV. 2.2, NOV. 29, 2010 40 MX29F400C T/B ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. UNITS TYP. MAX. Byte Programming Time 9 300 us Word Programming Time 11 360 us Sector Erase Time 0.7 8 sec 4 32 sec Byte Mode 4.5 13.5 sec Word Mode 3 9 sec Chip Erase Time Chip Programming Time Erase/Program Cycles 100,000 Cycles Note: 1. Typical condition means 25°C, 5V. 2. Maximum condition means 90°C, 4.5V, 100K cycles. DATA RETENTION PARAMETER Condition Min. Data retention 55˚C 20 Max. UNIT years LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage difference with GND on all pins except I/O pins -1.0V 13.5V Input Voltage difference with GND on all I/O pins -1.0V Vcc + 1.0V -100mA +100mA Vcc Current Includes all pins except Vcc. Test conditions: VCC = 5V, one pin per testing TSOP AND SOP PIN CAPACITANCE Parameter Symbol Parameter Description CIN2 Control Pin Capacitance COUT Output Capacitance CIN Input Capacitance Test Set MAX UNIT VIN=0 12 pF VOUT=0 12 pF VIN=0 8 pF P/N:PM1200 TYP REV. 2.2, NOV. 29, 2010 41 MX29F400C T/B ORDERING INFORMATION PART NO. MX29F400CTMI-70 Access Time (ns) 70 Operating Current MAX.(mA) 40 Standby Current MAX.(uA) 5 Temperature Range PACKAGE Remark -40oC~85oC 44 Pin SOP Note 1 o o MX29F400CTMI-90 90 40 5 -40 C~85 C 44 Pin SOP Note 1 MX29F400CTTI-70 70 40 5 -40oC~85oC 48 Pin TSOP (Normal Type) Note 1 MX29F400CTTI-90 90 40 5 -40oC~85oC 48 Pin TSOP (Normal Type) Note 1 MX29F400CBMI-70 70 40 5 -40oC~85oC 44 Pin SOP Note 1 o o MX29F400CBMI-90 90 40 5 -40 C~85 C 44 Pin SOP Note 1 MX29F400CBTI-70 70 40 5 -40oC~85oC 48 Pin TSOP (Normal Type) Note 1 MX29F400CBTI-90 90 40 5 -40oC~85oC 48 Pin TSOP (Normal Type) Note 1 MX29F400CTMI-70G 70 40 5 -40oC~85oC 44 Pin SOP MX29F400CTMI-90G 90 40 5 -40oC~85oC 44 Pin SOP MX29F400CTTI-70G 70 40 5 -40oC~85oC MX29F400CTTI-90G 90 40 5 -40oC~85oC MX29F400CBMI-70G 70 40 5 -40oC~85oC MX29F400CBMI-90G 90 40 5 -40oC~85oC MX29F400CBTI-70G 70 40 5 -40oC~85oC MX29F400CBTI-90G 90 40 5 -40oC~85oC RoHS Compliant RoHS Compliant 48 Pin TSOP RoHS (Normal Type) Compliant 48 Pin TSOP RoHS (Normal Type) Compliant RoHS 44 Pin SOP Compliant RoHS 44 Pin SOP Compliant 48 Pin TSOP RoHS Compliant (Normal Type) 48 Pin TSOP RoHS (Normal Type) Compliant Note 1: The part no. is not recommended for new design in. P/N:PM1200 REV. 2.2, NOV. 29, 2010 42 MX29F400C T/B PART NAME DESCRIPTION MX 29 F 400 C T T I 70 G OPTION: G: RoHS Compliant package blank: normal SPEED: 70:70ns 90: 90ns TEMPERATURE RANGE: I: Industrial (-40C to 85C) PACKAGE: M:SOP T: TSOP BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot REVISION: C DENSITY & MODE: 400: 4M, x8/x16 Boot Sector TYPE: F: 5V DEVICE: 29: Flash P/N:PM1200 REV. 2.2, NOV. 29, 2010 43 MX29F400C T/B PACKAGE INFORMATION P/N:PM1200 REV. 2.2, NOV. 29, 2010 44 MX29F400C T/B P/N:PM1200 REV. 2.2, NOV. 29, 2010 45 MX29F400C T/B REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" title 2. Removed commercial grade 3. Added access time: 55ns; Removed access time: 120ns 1.1 1. Removed access time : 55ns 2. Removed sector protect/ chip unprotect without 12V 3. Added in-system sector protect/ chip unprotect 4. Added data# polling, toggle bit algorithm 5. Added RY/BY# timing waveform 1.2 1. Datasheet format changed 1.3 1. Data modification 2. Changed maximum condition as 90°C, 4.5V 100K cycles 1.4 1. Added statement 1.5 1. Data modification 1.6 1. Added recommendation for non RoHS compliant devices 2. Changed test condition : 30PF loading for 70ns 1.7 1. Added note 4 into table 3. Command Definitions 1.8 1. Modified Figure 10. CE# Controlled Write Timing Waveform 1.9 1. Modified Figure 10. CE# Controlled Write Timing Waveform (Changed "Twhwh1 or Twhwh2" into "Tavt or Taetb") 2. Modified Figure 12. DATA# POLLING TIMING WAVEFORM 2.0 1. Added Note into DC characteristics 2. Added Icw/Trc/Twp/Twph/Tghwl spec 3. Added Note for voltage undershooting 4. Revised Figure 14. TEMPORARY UNPROTECT WAVEFORMS 2.1 1. Added data retention table 2. Modified the sector erase time max from 15s to 8s 2.2 1. Modified AC CHARACTERISTICS 2. Modified description wording for "RoHS Compliant" P/N:PM1200 Page Date P1 DEC/20/2005 All All P1,19,21,22 JUN/20/2006 P38,39 P1,7,17,31~34 P33~35 P26,27 P24,28,30 All AUG/15/2006 All AUG/17/2006 P41 P47 NOV/06/2006 P2 DEC/11/2006 P1,42 MAR/19/2007 P17 P10 JAN/22/2008 P28 FEB/25/2008 P28 MAR/09/2009 P36 P15 P16, 18 P15 P33 P41 P18,41 P18 P1,42,43 MAY/25/2009 JUN/30/2009 NOV/29/2010 REV. 2.2, NOV. 29, 2010 46 MX29F400C T/B Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. Copyright© Macronix International Co., Ltd. 2005~2010. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 47