Datasheet - Macronix

MX29SL800C T/B
MX29SL802C T/B
8M-BIT [1M x 8 / 512K x 16] SINGLE VOLTAGE
1.8V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Single Power Supply Operation
- 1.65 to 2.2 volt for read, erase, and program operations
• 1,048,576 x 8 / 524,288 x 16 switchable
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Sector Structure
- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 15
• Sector protection
- Hardware method to disable any combination of sectors from program or erase operations
- Temporary sector unprotected allows code changes in previously locked sectors
• Latch-up protected to 100mA from -1V to Vcc + 1V
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Access time: 90ns
- Byte/Word program time: 12us/18us (typical)
- Erase time: 1.3s/sector, 18s/chip (typical)
• Low Power Consumption
- Low active read current: 6mA (maximum) at 5MHz
- Low standby current: 1uA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP (LFBGA/TFBGA/WFBGA)
• 48-Ball XFLGA
• All Pb-free devices are RoHS Compliant
P/N:PM1244
REV. 2.0, NOV. 20, 2008
1
MX29SL800C T/B
MX29SL802C T/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48-Ball CSP( Ball Pitch = 0.8 mm), Top View, Balls Facing Down
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
WE#
RESET#
NC
NC
Q5
Q12
VCC
Q4
RY/BY#
NC
A18
NC
Q2
Q10
Q11
Q3
A7
A17
A6
A5
Q0
Q8
Q9
Q1
A3
A4
A2
A1
A0
CE#
OE#
GND
B
C
D
E
G
H
4
3
2
1
A
P/N:PM1244
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REV. 2.0, NOV. 20, 2008
2
MX29SL800C T/B
MX29SL802C T/B
48-Ball XFLGA (Land Pitch = 0.5mm, Package Height = 0.5mm), Top View, Balls Facing Down
RESET#
A9
A11
NC
A10
A13
A14
A18
A8
A12
A15
Q8
Q10
Q4
Q11
A16
OE#
Q9
BYTE#
NC
Q5
Q6
Q7
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
Q15/
A-1
GND
C
D
E
F
G
H
6
A2
A4
A6
A17
5
A1
A3
A7
NC
4
A0
A5
3
CE#
GND
2
NC
NC
WE#
1
A
B
J
K
L
48-Ball WFBGA (Balls Facing Down, 4 x 6 x 0.75 mm for 29SL802C)
6
A2
A4
A6
A17
5
A1
A3
A7
NC
4
A0
A5
3
CE#
2
GND
1
A
NC
NC
WE#
NC
NC
A9
A11
A10
A13
A14
A18
A8
A12
A15
Q8
Q10
Q4
Q11
A16
OE#
Q9
NC
Q5
Q6
Q7
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
Q15
GND
B
C
D
E
F
G
H
J
NC
P/N:PM1244
K
L
REV. 2.0, NOV. 20, 2008
3
MX29SL800C T/B
MX29SL802C T/B
PIN DESCRIPTION
LOGIC SYMBOL
SYMBOL PIN NAME
A0~A18
Address Input
Q0~Q14
Data Input/Output
Q15/A-1
Q15 (data input/output, word mode)/
19
A0-A18
16 or 8
Q0-Q15
(A-1)
A-1(LSB address input, byte mode)
CE#
Chip Enable Input
WE#
Write Enable Input
BYTE#
Word/Byte Selection input
OE#
RESET#
Hardware Reset Pin
WE#
OE#
Output Enable Input
RY/BY#
Ready/Busy Output
VCC
Power Supply Pin (1.65V~2.2V)
GND
Ground Pin
CE#
RESET#
RY/BY#
BYTE#
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REV. 2.0, NOV. 20, 2008
4
MX29SL800C T/B
MX29SL802C T/B
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
BYTE#
WRITE
CONTROL
STATE
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
STATE
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
A0-AM
PROGRAM/ERASE
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
P/N:PM1244
REV. 2.0, NOV. 20, 2008
5
MX29SL800C T/B
MX29SL802C T/B
Table 1. BLOCK STRUCTURE
MX29SL800CT/MX29SL802CT SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode Word Mode
Address range
Sector Address
Byte Mode (x8)
Word Mode (x16) A18 A17 A16 A15 A14 A13 A12
SA0
64Kbytes
32Kwords
00000h-0FFFFh
00000h-07FFFh
0
0
0
0
X
X
X
SA1
64Kbytes
32Kwords
10000h-1FFFFh
08000h-0FFFFh
0
0
0
1
X
X
X
SA2
64Kbytes
32Kwords
20000h-2FFFFh
10000h-17FFFh
0
0
1
0
X
X
X
SA3
64Kbytes
32Kwords
30000h-3FFFFh
18000h-1FFFFh
0
0
1
1
X
X
X
SA4
64Kbytes
32Kwords
40000h-4FFFFh
20000h-27FFFh
0
1
0
0
X
X
X
SA5
64Kbytes
32Kwords
50000h-5FFFFh
28000h-2FFFFh
0
1
0
1
X
X
X
SA6
64Kbytes
32Kwords
60000h-6FFFFh
30000h-37FFFh
0
1
1
0
X
X
X
SA7
64Kbytes
32Kwords
70000h-7FFFFh
38000h-3FFFFh
0
1
1
1
X
X
X
SA8
64Kbytes
32Kwords
80000h-8FFFFh
40000h-47FFFh
1
0
0
0
X
X
X
SA9
64Kbytes
32Kwords
90000h-9FFFFh
48000h-4FFFFh
1
0
0
1
X
X
X
SA10
64Kbytes
32Kwords
A0000h-AFFFFh
50000h-57FFFh
1
0
1
0
X
X
X
SA11
64Kbytes
32Kwords
B0000h-BFFFFh
58000h-5FFFFh
1
0
1
1
X
X
X
SA12
64Kbytes
32Kwords
C0000h-CFFFFh
60000h-67FFFh
1
1
0
0
X
X
X
SA13
64Kbytes
32Kwords
D0000h-DFFFFh
68000h-6FFFFh
1
1
0
1
X
X
X
SA14
64Kbytes
32Kwords
E0000h-EFFFFh
70000h-77FFFh
1
1
1
0
X
X
X
SA15
32Kbytes
16Kwords
F0000h-F7FFFh
78000h-7BFFFh
1
1
1
1
0
X
X
SA16
8Kbytes
4Kwords
F8000h-F9FFFh
7C000h-7CFFFh
1
1
1
1
1
0
0
SA17
8Kbytes
4Kwords
FA000h-FBFFFh
7D000h-7DFFFh
1
1
1
1
1
0
1
SA18
16Kbytes
8Kwords
FC000h-FFFFFh
7E000h-7FFFFh
1
1
1
1
1
1
X
P/N:PM1244
REV. 2.0, NOV. 20, 2008
6
MX29SL800C T/B
MX29SL802C T/B
MX29SL800CB/MX29SL802CB SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode Word Mode
Address range
Sector Address
Byte Mode (x8)
Word Mode (x16) A18 A17 A16 A15 A14 A13 A12
SA0
16Kbytes
8Kwords
00000h-03FFFh
00000h-01FFFh
0
0
0
0
0
0
X
SA1
8Kbytes
4Kwords
04000h-05FFFh
02000h-02FFFh
0
0
0
0
0
1
0
SA2
8Kbytes
4Kwords
06000h-07FFFh
03000h-03FFFh
0
0
0
0
0
1
1
SA3
32Kbytes
16Kwords
08000h-0FFFFh
04000h-07FFFh
0
0
0
0
1
X
X
SA4
64Kbytes
32Kwords
10000h-1FFFFh
08000h-0FFFFh
0
0
0
1
X
X
X
SA5
64Kbytes
32Kwords
20000h-2FFFFh
10000h-17FFFh
0
0
1
0
X
X
X
SA6
64Kbytes
32Kwords
30000h-3FFFFh
18000h-1FFFFh
0
0
1
1
X
X
X
SA7
64Kbytes
32Kwords
40000h-4FFFFh
20000h-27FFFh
0
1
0
0
X
X
X
SA8
64Kbytes
32Kwords
50000h-5FFFFh
28000h-2FFFFh
0
1
0
1
X
X
X
SA9
64Kbytes
32Kwords
60000h-6FFFFh
30000h-37FFFh
0
1
1
0
X
X
X
SA10
64Kbytes
32Kwords
70000h-7FFFFh
38000h-3FFFFh
0
1
1
1
X
X
X
SA11
64Kbytes
32Kwords
80000h-8FFFFh
40000h-47FFFh
1
0
0
0
X
X
X
SA12
64Kbytes
32Kwords
90000h-9FFFFh
48000h-4FFFFh
1
0
0
1
X
X
X
SA13
64Kbytes
32Kwords
A0000h-AFFFFh
50000h-57FFFh
1
0
1
0
X
X
X
SA14
64Kbytes
32Kwords
B0000h-BFFFFh
58000h-5FFFFh
1
0
1
1
X
X
X
SA15
64Kbytes
32Kwords
C0000h-CFFFFh
60000h-67FFFh
1
1
0
0
X
X
X
SA16
64Kbytes
32Kwords
D0000h-DFFFFh
68000h-6FFFFh
1
1
0
1
X
X
X
SA17
64Kbytes
32Kwords
E0000h-EFFFFh
70000h-77FFFh
1
1
1
0
X
X
X
SA18
64Kbytes
32Kwords
F0000h-FFFFFh
78000h-7FFFFh
1
1
1
1
X
X
X
P/N:PM1244
REV. 2.0, NOV. 20, 2008
7
MX29SL800C T/B
MX29SL802C T/B
Table 2. BUS OPERATION
ADDRESS
DESCRIPTION
CE# OE# WE#RESET# A18 A11 A9
A12 A10
Read
L
L
H
A8
A2
Q8~Q14 Q15/A-1
Q8~Q14
Dout
DIN
DIN
H
L
H
AIN
Reset
X
X
X
L
X
Temporary sector
Unprotection
X
X
X
Vhv
AIN
Output Disable
L
H
H
H
VCC± X
X
VCC±
BYTE#=Vil
=Vih
Dout
L
0.3V
Q0~Q7 BYTE#
AIN
Write
Standby
A6 A5 A1 A0
A7
H
Q8~Q15
High Z High Z High Z
DIN
DIN
A-1
=High Z
X
High Z
X
X
High Z High Z High Z
X
X
High Z High Z High Z
X
0.3V
Sector Protect
L
H
L
Vhv
SA
X
X
X
L
X
H
L
DIN
X
X
L
Chip Unprotected
L
H
L
Vhv
X
X
X
X
H
X
H
L
DIN
X
X
X
Sector Protection Verify
L
L
H
H
SA
X
Vhv X
L
X
H
L CODE(4)
X
X
L
Notes:
1. Vhv is the very high voltage, 10V to 11V.
2. X means input high (Vih) or input low (Vil).
3. SA means sector address: A12~A18.
4. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
8
MX29SL800C T/B
MX29SL802C T/B
REQUIREMENTS FOR READING ARRAY DATA
Read array action is to read the data stored in the array out. While the memory device is in powered up or has been
reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the
array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the
data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will
be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there
will be no data displayed on output pin at all.
After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to
the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the
device receives the Erase suspend command, erase operation will be stopped after a period of time no more than
Tready1 and the device will return to the status of read array. At this time, the device can read the data stored in any
address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in
the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued
after erase suspend, after program operation is completed, system can still read array data in any address except the
sectors to be erased.
The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in
the array in the following two situations:
1. In program or erase operation, the programming or erasing failure causes Q5 to go high.
2. The device is in auto select mode or CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system must
issue reset command before reading array data.
WRITE COMMANDS/COMMAND SEQUENCES
To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all
address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE#
and WE#.
Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the
device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will
bring the device to an undefined state.
RESET# OPERATION
Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program
or erase operation, the reset operation will take at most a period of Tready1 for the device to return to read array mode.
Before the device returns to read array mode, the RY/BY# pin remains low (busy status).
When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger
current if RESET# pin is held at Vil but not within GND±0.3V.
It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will
be reset during system reset and allows system to read boot code from flash memory.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
9
MX29SL800C T/B
MX29SL802C T/B
SECTOR PROTECT OPERATION
When a sector is protected, program or erase operation will be disabled on these sectors. MX29SL800C/MX29SL802C
T/B provides two methods for sector protection.
Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by
asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the
algorithm for this method.
The other method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the
falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
CHIP UNPROTECT OPERATION
MX29SL800C/MX29SL802C T/B provides two methods for chip unprotect. The chip unprotect operation unprotects all
sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sectors
are unprotected when shipped from the factory.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for algorithm
of the operation.
The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect
operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
TEMPORARY SECTOR UNPROTECT OPERATION
System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously
protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once
Vhv is removed from RESET# pin and previously protected sectors are again protected.
AUTOMATIC SELECT OPERATION
When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon
ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs
continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix
Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will
reset device back to read array mode or erase-suspended read array mode.
Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While the high
voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or
erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high,
device will output Device ID.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
10
MX29SL800C T/B
MX29SL802C T/B
VERIFY SECTOR PROTECT STATUS OPERATION
MX29SL800C/MX29SL802C T/B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires
Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to A18 pins. If
the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated
sector is still not being protected.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during
power up. Besides, only after successful completion of the specified command sets will the device begin its erase or
program operation.
Other features to protect the data from accidental alternation are described as followed.
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih,
WE# a Vih, or OE# at Vil.
POWER-UP SEQUENCE
Upon power up, MX29SL800C/MX29SL802C T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences.
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the
rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
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11
MX29SL800C T/B
MX29SL802C T/B
TABLE 3. MX29SL800C/MX29SL802C T/B COMMAND DEFINITIONS
Automatic Select
Command
Read
Reset
Mode
Mode
Hex
1st Bus Cyc
2nd Bus Cyc
3rd Bus Cyc
Sector Protect
Silicon ID
Device ID
Verify
Program
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Addr
Addr
XXX
555
AAA
555
AAA
555
AAA
555
AAA
Data
Data
F0
AA
AA
AA
AA
AA
AA
AA
AA
Addr
2AA
555
2AA
555
2AA
555
2AA
555
Data
55
55
55
55
55
55
55
55
Addr
555
AAA
555
AAA
555
AAA
555
AAA
Data
90
90
90
90
90
90
A0
A0
(Sector) (Sector)
4th Bus Cyc
Addr
X00
X00
X01
X02
X02
X04
Addr
Addr
Data
C2H
C2H
ID
ID
00/01
00/01
Data
Data
5th Bus Cyc
Addr
6th Bus Cyc
Addr
Data
Data
Command
Chip Erase
Sector Erase
CFI Read
Erase
Erase
Suspend
Resume
Hex
Word
Byte
Word
Byte
Word
Byte
Word/Byte
Word/Byte
1st Bus Cyc
Addr
555
AAA
555
AAA
55
AA
XXX
XXX
Data
AA
AA
AA
AA
98
98
B0
30
2nd Bus Cyc
Addr
2AA
555
2AA
555
Data
55
55
55
55
Addr
555
AAA
555
AAA
Data
80
80
80
80
Addr
555
AAA
555
AAA
Data
AA
AA
AA
AA
Addr
2AA
555
2AA
555
Data
55
55
55
55
Addr
555
AAA
Sector
Sector
Data
10
10
30
30
3rd Bus Cyc
4th Bus Cyc
5th Bus Cyc
6th Bus Cyc
Notes:
1. Device ID: 22EAH/EAH for Top Boot Sector device.
226BH/6BH for Bottom Boot Sector device.
2. For sector protect verify result, XX00H/00H means sector is not protected, XX01H/01H means sector has been
protected.
3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc
is for protect verify.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
12
MX29SL800C T/B
MX29SL802C T/B
RESET
In the following situations, executing reset command will reset device back to read array mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program included)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Read silicon ID mode
• Sector protect verify
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device
back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must
issue reset command to reset device back to read array mode.
When the device is in program mode (not program fail) or erase mode (not erase fail), device will ignore reset command.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is
protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a
specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times
without entering another command sequence. The reset command is necessary to exit the Automatic Select mode
and back to read array. The following table shows the identification code with corresponding address.
Manufacturer ID
Device ID
Sector Protect Verify
Address
Data (Hex)
Representation
Word
X00
00C2
Byte
X00
C2
Word
X01
22EA/226B
Top/Bottom Boot Sector
Byte
X02
EA/6B
Top/Bottom Boot Sector
Word
(Sector address) X 02
00/01
Unprotected/protected
Byte
(Sector address) X 04
00/01
Unprotected/protected
There is an alternative method to that shown in Table 3, which is intended for EPROM programmers and requires Vhv
on address bit A9.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
13
MX29SL800C T/B
MX29SL802C T/B
AUTOMATIC PROGRAMMING
The MX29SL800C/MX29SL802C T/B can provide the user program function by the form of Byte-Mode or Word-Mode.
As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user
inputs will automatically be programmed into the array.
Once the program function is executed, the internal write state controller will automatically execute the algorithms and
timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the
threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not
pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the
other cells fail in verification in order to avoid over-programming.
Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from
"0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not
successfully programmed to "0".
Any command written to the device during programming will be ignored except hardware reset, which will terminate the
program operation after a period of time no more than Tready1. When the embedded program algorithm is complete or
the program operation is terminated by hardware reset, the device will return to the reading array data mode.
With the internal write state controller, the device requires the user to write the program command and data only. The
typical chip program time at room temperature of the MX29SL800C/MX29SL802C T/B is 9.6 seconds. (Word-Mode)
When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by
the following methods:
Status
Q7
Q6
Q5
RY/BY#*2
In progress*1
Q7#
Toggling
0
0
Finished
Q7
Stop toggling
0
1
Exceed time limit
Q7#
Toggling
1
0
*1: The status "in progress" means both program mode and erase-suspended program mode.
*2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor.
*3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to
toggle for about 1us or less and the device returns to read array state without programing the data in the protected
sector.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
14
MX29SL800C T/B
MX29SL802C T/B
CHIP ERASE
Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two
cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the
sixth cycle is the chip erase operation.
During chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that
chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array.
When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by
the following methods:
Status
Q7
Q6
Q5
Q2
RY/BY#
In progress
0
Toggling
0
Toggling
0
Finished
1
Stop toggling
0
1
1
Exceed time limit
0
Toggling
1
Toggling
0
SECTOR ERASE
Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The
first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles"
and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a timeout period of 50us counted internally. During the time-out period, additional sector address and sector erase command
can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If
user enters any command other than sector erase or erase suspend during time-out period, the erase command would
be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all
sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation
begins.
During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can
check the status as chip erase.
When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the
following methods:
Status
Q7
Q6
Q5
Q3
Q2
RY/BY#*2
Time-out period
0
Toggling
0
0
Toggling
0
In progress
0
Toggling
0
1
Toggling
0
Finished
1
Stop toggling
0
1
1
1
Exceed time limit
0
Toggling
1
1
Toggling
0
*1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to
another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid.
*2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor.
*3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to
toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
15
MX29SL800C T/B
MX29SL802C T/B
SECTOR ERASE SUSPEND
During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the
time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erasesuspended read array mode. If user issue erase suspend command during the sector erase is being operated, device
will suspend the ongoing erase operation, and after the Tready1(<=20us) suspend finishes and the device will enter
erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/
BY#.
After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the
speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2
to judge the sector is erasing or the erase is suspended.
Status
Q7
Q6
Q5
Q3
Q2
RY/BY#
1
1
0
0
Toggle
1
Erase suspend read in non-erase suspended sector
Data
Data
Data
Data
Data
1
Erase suspend program in non-erase suspended sector
Q7#
Toggle
0
0
1
0
Erase suspend read in erase suspended sector
When the device has suspended erasing, user can execute the command sets except sector erase and chip erase,
such as read silicon ID, sector protect verify, program, CFI query and erase resume.
SECTOR ERASE RESUME
Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can
issue another erase suspend command, but there should be a 10ms interval between erase resume and the next erase
suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will
increase.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
16
MX29SL800C T/B
MX29SL802C T/B
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29SL800C/MX29SL802C T/B features CFI mode. Host system can retrieve the operating characteristics, structure
and vendor-specified information such as identifying information, memory size, byte/word configuration, operating
voltages and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to
address "55h"/"AAh" (depending on Word/Byte mode), the device will enter the CFI Query Mode, any time the device
is ready to read array data. The system can read CFI information at the addresses given in Table 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the CFI
Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode.
TABLE 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Address
(Byte Mode)
Query-unique ASCII string "QRY"
20
22
24
Primary vendor command set and control interface ID code
26
28
Address for primary algorithm extended query table
2A
2C
Alternate vendor command set and control interface ID code (none)
2E
30
Address for secondary algorithm extended query table (none)
32
34
Address
(Word Mode)
10
11
12
13
14
15
16
17
18
19
1A
Data
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
TABLE 4-2. CFI Mode: System Interface Data Values
(All values in these tables are in hexadecimal)
Description
VCC supply, minimum (1.65V)
VCC supply, maximum (2.2V)
VPP supply, minimum (none)
VPP supply, maximum (none)
Typical timeout for single word/byte write (2N us)
Typical timeout for Minimum size buffer write (2N us)
Typical timeout for individual block erase (2N ms)
Typical timeout for full chip erase (2N ms)
Maximum timeout for single word/byte write times (2N X Typ)
Maximum timeout for buffer write times (2N X Typ)
Maximum timeout for individual block erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
P/N:PM1244
Address
(Byte Mode)
36
38
3A
3C
3E
40
42
44
46
48
4A
4C
Address
(Word Mode)
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
Data
0016
0022
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
REV. 2.0, NOV. 20, 2008
17
MX29SL800C T/B
MX29SL802C T/B
TABLE 4-3. CFI Mode: Device Geometry Data Values
(All values in these tables are in hexadecimal)
Description
Device size (2N bytes)
Flash device interface code (refer to the CFI publication 100)
Maximum number of bytes in multi-byte write (not supported)
Number of erase block regions
Index for Erase Bank Area 1 (refer to the CFI publication 100)
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4
Address
(Byte Mode)
4E
50
52
54
56
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
Address
(Word Mode)
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
Data
0014
0002
0000
0000
0000
0004
0000
0000
0040
0000
0001
0000
0020
0000
0000
0000
0080
0000
000E
0000
0000
0001
TABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
(All values in these tables are in hexadecimal)
Description
Address
(Byte Mode)
Address
(Word Mode)
Data
Query - Primary extended table, unique ASCII string, PRI
80
40
0050
Major version number, ASCII
Minor version number, ASCII
82
84
86
88
41
42
43
44
0052
0049
0031
0030
Unlock recognizes address (0= recognize, 1= don't recognize)
8A
45
0000
Erase suspend (2= to both read and program)
8C
46
0002
Sector protect (N= # of sectors/group)
Temporary sector unprotected (1=supported)
Sector protect/unprotected scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
Page mode (0=not supported)
8E
90
92
94
96
98
47
48
49
4A
4B
4C
0001
0001
0004
0000
0000
0000
P/N:PM1244
REV. 2.0, NOV. 20, 2008
18
MX29SL800C T/B
MX29SL802C T/B
ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC
Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Voltage Range
Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.0V
RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +11.5V
The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to Vcc +0.5V
Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° C to +70° C
Industrial (I) Grade
Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° C to +85° C
VCC Supply Voltages
VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65V to 2.2V
P/N:PM1244
REV. 2.0, NOV. 20, 2008
19
MX29SL800C T/B
MX29SL802C T/B
DC CHARACTERISTICS
Symbol
Description
Iilk
Input Leak
Iilk9
A9, OE#, RESET#
Min
Typ
Max
± 1.0uA
35uA
Input Leak
Iolk
Output Leak
Icr1
Read Current(10MHz)
Remark
A9, OE#,
RESET#=11V
± 1.0uA
12mA
CE#=Vil,
OE#=Vih
Icr2
Read Current(5MHz)
6mA
CE#=Vil,
OE#=Vih
Icw
Write Current
15mA
25mA
CE#=Vil,
OE#=Vih,
WE#=Vil
Isb
Standby Current
1uA
5uA
Vcc=Vcc max,
other pin disable
Isbr
Reset Current
1uA
5uA
Vcc=Vccmax,
RESET# enable,
other pin disable
Isbs
Sleep Mode Current
1uA
Vil
Input Low Voltage
-0.5V
0.2 x Vcc
Vih
Input High Voltage
0.7xVcc
Vcc+0.3V
Vhv
Very High Voltage for hardware
10V
10.5V
5uA
11V
Protect/Unprotect/
Auto Select/Temporary
Unprotect
Vol
Output Low Voltage
0.25V
Iol=2mA,
Vcc=Vcc min
0.1V
Iol=100uA,
Vcc=Vcc min
Voh1
Ouput High Voltage (TTL)
0.85xVcc
IOH1=-2mA
Voh2
Ouput High Voltage (CMOS)
Vcc-0.4V
IOH2=-100uA
Notes:
When address is not changed and remain stable for Taa + 30nS, the device automatically enter Auto sleep Mode.
P/N:PM1244
REV. 2.0, NOV. 20, 2008
20
MX29SL800C T/B
MX29SL802C T/B
SWITCHING TEST CIRCUITS
Vcc
0.1uF
R2
TESTED DEVICE
Vcc
R1
CL
R1=25K ohm
R2=25K ohm
Test Condition
Output Load Capacitance,CL : 30pF
Rise/Fall Times : 5ns
Input/Output reference levels :Vcc/2
SWITCHING TEST WAVEFORMS
Vcc
Test Points
0.0V
INPUT
OUTPUT
P/N:PM1244
REV. 2.0, NOV. 20, 2008
21
MX29SL800C T/B
MX29SL802C T/B
AC CHARACTERISTICS
Symbol
Description
Taa
Min
Max
Unit
Valid data output after address
90
ns
Tce
Valid data output after CE# low
90
ns
Toe
Valid data output after OE# low
35
ns
Tdf
Data output floating after OE# high
30
ns
Toh
Data hold time after address rising
0
ns
Trc
Read period time
90
ns
Twc
Write period time
90
ns
Tcwc
Command write period time
90
ns
Tas
Address setup time
0
ns
Tah
Address hold time
45
ns
Tds
Data setup time
45
ns
Tdh
Data hold time
0
ns
Tvcs
Vcc setup time
50
us
Tcs
CE# Setup time
0
ns
Tch
CE# hold time
0
ns
Toes
OE# setup time
0
ns
Read
0
ns
Toggle &
10
ns
Toeh
Toeh
OE# hold time
Typ
Data# Polling
Tws
WE# setup time
0
ns
Twh
WE# hold time
0
ns
Tcep
CE# pulse width
45
ns
Tceph
CE# pulse width high
30
ns
Twp
WE# pulse width
45
ns
Twph
WE# pulse width high
30
ns
Tbusy
Program/Erase active time by RY/BY#
Tghwl
Read recover time before write
0
ns
Tghel
Read recover time before write
0
ns
Twhwh1
Program operation
Byte
12
us
Twhwh1
Program operation
Word
18
us
Twhwh2
Sector erase operation
1.3
sec
Tbal
Sector add load time
90
50
P/N:PM1244
ns
us
REV. 2.0, NOV. 20, 2008
22
MX29SL800C T/B
MX29SL802C T/B
Figure 1. COMMAND WRITE OPERATION
Tcwc
CE#
Vih
Vil
Tch
Tcs
WE#
Vih
Vil
Toes
OE#
Twph
Twp
Vih
Vil
Addresses
Vih
VA
Vil
Tah
Tas
Tdh
Tds
Vih
Data
Vil
DIN
VA: Valid Address
P/N:PM1244
REV. 2.0, NOV. 20, 2008
23
MX29SL800C T/B
MX29SL802C T/B
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
Tce
Vih
CE#
Vil
Vih
WE#
Vil
Toeh
Tdf
Toe
Vih
OE#
Vil
Toh
Taa
Trc
Vih
ADD Valid
Addresses
Vil
Outputs
Voh
HIGH Z
DATA Valid
HIGH Z
Vol
P/N:PM1244
REV. 2.0, NOV. 20, 2008
24
MX29SL800C T/B
MX29SL802C T/B
AC CHARACTERISTICS
Item
Description
Setup
Speed
Unit
Trp1
RESET# Pulse Width (During Automatic Algorithms)
MIN
10
us
Trp2
RESET# Pulse Width (NOT During Automatic Algorithms)
MIN
500
ns
Trh
RESET# High Time Before Read
MIN
200
ns
Trb1
RY/BY# Recovery Time (to CE#, OE# go low)
MIN
0
ns
Trb2
RY/BY# Recovery Time (to WE# go low)
MIN
50
ns
Tready1
RESET# PIN Low (During Automatic Algorithms)
MAX
20
us
MAX
500
ns
to Read or Write
Tready2
RESET# PIN Low (NOT During Automatic
Algorithms) to Read or Write
Figure 3. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
Trb2
WE#
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
Trh
RY/BY#
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
P/N:PM1244
REV. 2.0, NOV. 20, 2008
25
MX29SL800C T/B
MX29SL802C T/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
CE#
Tch
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Twc
Address
Read Status
Tah
Tas
2AAh
VA
SA
Tds
Tdh
55h
VA
In
Progress Complete
10h
Data
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
P/N:PM1244
REV. 2.0, NOV. 20, 2008
26
MX29SL800C T/B
MX29SL802C T/B
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
P/N:PM1244
REV. 2.0, NOV. 20, 2008
27
MX29SL800C T/B
MX29SL802C T/B
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Address
Tas
Sector
Address 0
2AAh
Tds
Tdh
55h
Sector
Address 1
Sector
Address n
Tah
VA
VA
In
Progress Complete
30h
30h
30h
Data
Tbusy
Trb
RY/BY#
P/N:PM1244
REV. 2.0, NOV. 20, 2008
28
MX29SL800C T/B
MX29SL802C T/B
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Last Sector
to Erase
NO
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
Data=FFh
NO
YES
Auto Sector Erase Completed
P/N:PM1244
REV. 2.0, NOV. 20, 2008
29
MX29SL800C T/B
MX29SL802C T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO
ERASE SUSPEND
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM1244
REV. 2.0, NOV. 20, 2008
30
MX29SL800C T/B
MX29SL802C T/B
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
CE#
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Address
555h
Last 2 Read Status Cycle
Tah
Tas
VA
PA
Tds
VA
Tdh
A0h
Status
PD
DOUT
Data
Tbusy
Trb
RY/BY#
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31
MX29SL800C T/B
MX29SL802C T/B
Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Twhwh1 or Twhwh2
Tcep
CE#
Tceph
Tghwl
OE#
Tah
Tas
Address
555h
VA
PA
Tds
VA
Tdh
A0h
Status
PD
DOUT
Data
Tbusy
RY/BY#
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MX29SL800C T/B
MX29SL802C T/B
Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Read Again Data:
Program Data?
No
YES
No
Last Word to be
Programed
YES
Auto Program Completed
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MX29SL800C T/B
MX29SL802C T/B
SECTOR PROTECT/CHIP UNPROTECT
Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
150us: Sector Protect
15ms: Chip Unprotect
1us
CE#
WE#
OE#
Verification
Data
60h
SA, A6
A1, A0
60h
40h
VA
VA
Status
VA
Vhv
Vih
RESET#
VA: valid address
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34
MX29SL800C T/B
MX29SL802C T/B
Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
No
Retry Count=25?
Data=01h?
Yes
Yes
Device fail
Protect another
Yes
sector?
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
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35
MX29SL800C T/B
MX29SL802C T/B
Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
All sectors
protected?
No
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
No
Retry Count=1000?
Data=00h?
Yes
Device fail
Yes
Temporary Unprotect
Write reset CMD
Chip Unprotect Done
P/N:PM1244
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MX29SL800C T/B
MX29SL802C T/B
Figure 14. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)
CE#
Twpp1
WE#
Toesp
Verify
10.5V
1.8V
OE#
Tvlht
Tvlht
A1
A6
10.5V
1.8V
A9
Tvlht
A18-A12
Sector Address
Data
01H
F0H
Toe
Notes: Tvlht (Voltage transition time)=4us min.
Twpp1 (Write pulse width for sector protect)=100ns min, 10us(Typ.)
Twpp2 (Write pulse width for chip unprotected)=100ns min, 12ms(Typ.)
Toesp (OE# setup time to WE# active)=4us min.
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MX29SL800C T/B
MX29SL802C T/B
Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Write Sector Addr
Retry Count=0
OE#=Vhv, A9=Vhv, CE#=Vil
A6=Vil
Activate WE# Pulse
Time Out 150us
Retry Count+1
WE#=Vih, CE#=OE#=Vil
A9=Vhv
Read at Sector Address
with A1=1
No
PLSCNT=32?
.
No
Data=01H?
Yes
Device Failed
Protect Another
Sector?
Yes
Remove Vhv from A9
Write Reset Command
Sector Protect
Done
P/N:PM1244
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38
MX29SL800C T/B
MX29SL802C T/B
Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)
CE#
Twpp2
WE#
Toesp
Verify
10.5V
VCC
OE#
Tvlht
Tvlht
A1
10.5V
VCC
A9
Tvlht
A6
A18-A12
Sector Address
Data
00H
F0H
Toe
Notes: Tvlht (Voltage transition time)=4us min.
Twpp1 (Write pulse width for sector protect)=100ns min, 10us(Typ.)
Twpp2 (Write pulse width for chip unprotected)=100ns min, 12ms(Typ.)
Toesp (OE# setup time to WE# active)=4us min.
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MX29SL800C T/B
MX29SL802C T/B
Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)
START
Protect All Sectors
Retry Count=0
OE#=A9=Vhv
CE#=Vil, A6=Vih
Activate WE# Pulse
Time Out 50ms
Retry Count +1
Sector Protect Verify from
first sector with CE#=OE#=vil,
A9=Vhv, A1=1
No
Data=00H?
go to next sector
No
Yes
No
All sectors have
been verified?
PLSCNT=1000?
Yes
Device Failed
Yes
Remove Vhv from A9
Write Reset Command
Chip Unprotect
Done
* Before chip unprotect, all sectors should be protected.
P/N:PM1244
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40
MX29SL800C T/B
MX29SL802C T/B
Table 5. TEMPORARY SECTOR UNPROTECT
Parameter Alt
Description
Condition Speed
Unit
Trpvhh
Tvidr
RESET# Rise Time to Vhv and Vhv Fall Time to RESET#
MIN
500
ns
Tvhhwl
Trsp
RESET# Vhv to WE# Low
MIN
4
us
Figure 18. TEMPORARY SECTOR UNPROTECT WAVEFORMS
Program or Erase Command Sequence
CE#
WE#
Tvhhwl
RY/BY#
Vhv
10.5V
RESET#
0 or 1.8V
Vil or Vih
Trpvhh
Trpvhh
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MX29SL800C T/B
MX29SL802C T/B
Figure 19. TEMPORARY SECTOR UNPROTECT FLOWCHART
Start
Apply RESET# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from RESET#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1. Temporary unprotect all protected sectors Vhv=10~11V.
2. After leaving temporary unprotect mode, the previously protected sectors are again protected.
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MX29SL800C T/B
MX29SL802C T/B
Figure 20. SILICON ID READ TIMING WAVEFORM
Vih
CE#
Vil
Tce
Vih
WE#
Vil
Toe
Vih
OE#
Tdf
Vil
Toh
Toh
Vhv
Vih
A9
Vil
Vih
A0
Vil
Taa
A1
Taa
Vih
Vil
Vih
ADD
Vil
DATA
Q0-Q7
Vih
DATA OUT
DATA OUT
C2H
EAH (TOP boot)
6BH (Bottom boot)
Vil
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MX29SL800C T/B
MX29SL802C T/B
WRITE OPERATION STATUS
Figure 21. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
Address
VA
VA
Taa
Toh
Q7
Status Data
Complement
True
Valid Data
Q0-Q6
Status Data
Status Data
True
Valid Data
High Z
High Z
Tbusy
RY/BY#
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44
MX29SL800C T/B
MX29SL802C T/B
Figure 22. DATA# POLLING ALGORITHM
Start
Read Q7~Q0 at valid address
(Note 1)
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
Q7 = Data# ?
(Note 2)
No
Yes
FAIL
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
P/N:PM1244
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45
MX29SL800C T/B
MX29SL802C T/B
Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
Address
VA
VA
VA
VA
Taa
Toh
Q6/Q2
Valid Status
Valid Data
(second read)
(stops toggling)
Valid Status
(first read)
Valid Data
Tbusy
RY/BY#
Notes:
1. VA : Valid Address
2. CE# must be toggled when toggle bit toggling.
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46
MX29SL800C T/B
MX29SL802C T/B
Figure 24. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0 Twice
(Note1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
(Note1, 2)
NO
Q6 Toggle ?
YES
Program/Erase fail
Write Reset CMD
Program/Erase Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM1244
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47
MX29SL800C T/B
MX29SL802C T/B
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE#)
Parameter
Description
Speed
Unit
-90
Telfl/Telfh
CE# to BYTE# Switching Low/High
MAX
5
ns
Tflqz
BYTE# from L to Output High-z
MAX
30
ns
Tfhqv
BYTE# from H to Output Active
MIN
90
ns
Figure 25. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word
mode)
CE#
OE#
Telfh
BYTE#
Q0~Q14
DOUT
(Q0-Q7)
Q15/A-1
VA
DOUT
(Q0-Q14)
DOUT
(Q15)
Tfhqv
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48
MX29SL800C T/B
MX29SL802C T/B
Figure 26. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to
byte mode)
CE#
OE#
Telfl
BYTE#
DOUT
(Q0-Q14)
Q0~Q14
DOUT
(Q0-Q7)
DOUT
(Q15)
Q15/A-1
VA
Tflqz
Figure 27. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS
CE#
The last WE# signal (falling edge)
WE#
BYTE#
Tas
P/N:PM1244
Tah
REV. 2.0, NOV. 20, 2008
49
MX29SL800C T/B
MX29SL802C T/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Vcc(min)
Vcc
GND
Tvr
Tvcs
Tf
Tce
Tr
Vih
CE#
Vil
Vih
WE#
Vil
Tf
Toe
Tr
Vih
OE#
Vil
Tr or Tf
Vih
ADDRESS
Tr or Tf
Valid
Address
Vil
Voh
DATA
Taa
High Z
Valid
Ouput
Vol
Figure A. AC Timing at Device Power-Up
Symbol
Parameter
Min.
Max.
Unit
Tvr
Vcc Rise Time
20
500000
us/V
Tr
Input Signal Rise Time
20
us/V
Tf
Input Signal Fall Time
20
us/V
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50
MX29SL800C T/B
MX29SL802C T/B
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
TYP.
MAX.
UNITS
Byte Programming Time
12
72
us
Word Programming Time
18
108
us
Sector Erase Time
1.3
15
sec
Chip Erase Time
18
sec
Byte Mode
12.6
sec
Word Mode
9.6
sec
Chip Programming Time
MIN.
Erase/Program Cycles
Note:
100,000
Cycles
1. Typical condition means 25° C, 1.8V.
2. Maximum condition means 90° C, 1.65V, 100K cycles.
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage difference with GND on OE#, RESET#, A9
-1.0V
11V
Input Voltage difference with GND on all power pins, Address pins, CE# and WE#
-1.0V
2xVCC
Input Voltage difference with GND on all I/O pins
-1.0V
VCC + 1.0V
-100mA
+100mA
Vcc Current
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin per testing
TSOP PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Set
TYP
MAX
UNIT
CIN2
Control Pin Capacitance
VIN=0
7.5
9
pF
COUT
Output Capacitance
VOUT=0
8.5
12
pF
CIN
Input Capacitance
VIN=0
6
7.5
pF
P/N:PM1244
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51
MX29SL800C T/B
MX29SL802C T/B
ORDERING INFORMATION
PART NO.
MX29SL800CTTC-90G
ACCESS
TIME (ns)
90
OPERATING
Current MAX. (mA)
12
STANDBY
Current MAX. (uA)
5
MX29SL800CBTC-90G
90
12
5
MX29SL800CTXBC-90G
90
12
5
MX29SL800CBXBC-90G
90
12
5
MX29SL800CTXEC-90G
90
12
5
MX29SL800CBXEC-90G
90
12
5
MX29SL800CTTI-90G
90
12
5
MX29SL800CBTI-90G
90
12
5
MX29SL800CTXBI-90G
90
12
5
MX29SL800CBXBI-90G
90
12
5
MX29SL800CTXEI-90G
90
12
5
MX29SL800CBXEI-90G
90
12
5
MX29SL802CTXHI-90G
(4 x 6 x 0.75mm)
90
12
5
MX29SL802CBXHI-90G
(4 x 6 x 0.75mm)
90
12
5
MX29SL800CTGBI-90G
(4 x 6 x 0.5mm)
90
12
5
MX29SL800CBGBI-90G
(4 x 6 x 0.5mm)
90
12
5
P/N:PM1244
PACKAGE
Remark
48-Pin TSOP
Pb-free
(Normal Type)
48-Pin TSOP
Pb-free
(Normal Type)
48-ball CSP
Pb-free
(Ball Size:0.3mm)
48-ball CSP
Pb-free
(Ball Size:0.3mm)
48-ball CSP
Pb-free
(Ball Size:0.4mm)
48-ball CSP
Pb-free
(Ball Size:0.4mm)
48-Pin TSOP
Pb-free
(Normal Type)
48-Pin TSOP
Pb-free
(Normal Type)
48-ball CSP
Pb-free
(Ball Size:0.3mm)
48-ball CSP
Pb-free
(Ball Size:0.3mm)
48-ball CSP
Pb-free
(Ball Size:0.4mm)
48-ball CSP
Pb-free
(Ball Size:0.4mm)
48-ball WFBGA
Pb-free
(Ball Pitch:0.5mm,
Ball Size:0.3mm)
48-ball WFBGA
Pb-free
(Ball Pitch:0.5mm,
Ball Size:0.3mm)
48-ball XFLGA
Pb-free
(Land Pitch:0.5mm,
Land Opening:0.25mm,
Package Height:0.5mm)
48-ball XFLGA
Pb-free
(Land Pitch:0.5mm,
Land Opening:0.25mm,
Package Height:0.5mm)
REV. 2.0, NOV. 20, 2008
52
MX29SL800C T/B
MX29SL802C T/B
PART NAME DESCRIPTION
MX 29 SL 800 C T T C
90 G
OPTION:
G: Lead-free package
SPEED:
90: 90ns
TEMPERATURE RANGE:
C: Commercial (0˚ C to 70˚ C)
I: Industrial (-40˚ C to 85˚ C)
PACKAGE:
T: TSOP
X: CSP
XB(TFBGA) - 6 x 8 x 1.2mm, Pitch 0.8mm, 0.3mm Ball
XE(LFBGA) - 6 x 8 x 1.3mm, Pitch 0.8mm, 0.4mm Ball
XH: (WFBGA)
(802C) - 4 x 6 x 0.75mm, Pitch 0.5mm, 0.3mm Ball
GB: XFLGA - 4 x 6 x 0.5mm, Pitch 0.5mm, 0.25mm land opening
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
C
DENSITY & MODE:
800: 8M, x8/x16 Boot Sector
802: 8M, x8/x16 Boot Sector, specified WFBGA 4x6x0.75mm package
TYPE:
SL: 1.8V
DEVICE:
29: Flash
P/N:PM1244
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53
MX29SL800C T/B
MX29SL802C T/B
PACKAGE INFORMATION
P/N:PM1244
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54
MX29SL800C T/B
MX29SL802C T/B
P/N:PM1244
REV. 2.0, NOV. 20, 2008
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MX29SL800C T/B
MX29SL802C T/B
P/N:PM1244
REV. 2.0, NOV. 20, 2008
56
MX29SL800C T/B
MX29SL802C T/B
P/N:PM1244
REV. 2.0, NOV. 20, 2008
57
MX29SL800C T/B
MX29SL802C T/B
MX29SL802C-WFBGA (CSP)
P/N:PM1244
REV. 2.0, NOV. 20, 2008
58
MX29SL800C T/B
MX29SL802C T/B
REVISION HISTORY
Revision No.
1.0
1.1
1.2
1.3
1.4
1.5
Description
1. Removed "Preliminary" title
1. Added Pb-free package option
1. Datasheet format changed
1. Data modification
1. Added statement
1. Added XFLGA package
1.6
1.7
1. Modified Figure A. Recommended Operating Conditions
1. Added MX29SL802C T/B for 48-Ball WFBGA (4x6x0.75mm)
information
2. Removed non Lead-free package option
3. Revised statement
1. Modified Figure 10. CE# Controlled Write Timing Waveform
1. Modified Ordering Information
2. Modified Switching Test Circuits
1. Removed part no. MX29SL800CTXHI-90G &
MX29SL800CBXHI-90G
1.8
1.9
2.0
P/N:PM1244
Page
P1
P58
All
All
P59
P1,3,53,54,
P59
P50
P3,53,59
P52
P17
P32
P52
P21
P52,53
Date
APR/20/2006
JUN/20/2006
AUG/14/2006
AUG/17/2006
NOV/06/2006
NOV/14/2006
NOV/14/2007
DEC/18/2007
FEB/25/2008
MAR/18/2008
NOV/20/2008
REV. 2.0, NOV. 20, 2008
59
MX29SL800C T/B
MX29SL802C T/B
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure
of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons
or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix
and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due
to use of Macronix's products in the prohibited applications.
MACRONIX INTERNATIONAL CO., LTD.
Headquarters
Macronix, Int'l Co., Ltd.
Taipei Office
Macronix, Int'l Co., Ltd.
16, Li-Hsin Road, Science Park,
Hsinchu, Taiwan, R.O.C.
Tel: +886-3-5786688
Fax: +886-3-5632888
19F, 4, Min-Chuan E. Road, Sec. 3,
Taipei, Taiwan, R.O.C.
Tel: +886-2-2509-3300
Fax: +886-2-2509-2200
Macronix America, Inc.
Macronix Europe N.V.
680 North McCarthy Blvd.
Milpitas, CA 95035, U.S.A.
Tel: +1-408-262-8887
Fax: +1-408-262-8810
Email: sales.northamerica@macronix.com
Koningin Astridlaan 59, Bus 1
1780 Wemmel Belgium
Tel: +32-2-456-8020
Fax: +32-2-456-8021
Macronix Asia Limited.
Singapore Office
Macronix Pte. Ltd.
NKF Bldg. 5F, 1-2 Higashida-cho,
Kawasaki-ku Kawasaki-shi,
Kanagawa Pref. 210-0005, Japan
Tel: +81-44-246-9100
Fax: +81-44-246-9105
1 Marine Parade Central
#11-03 Parkway Centre
Singapore 449408
Tel: +65-6346-5505
Fax: +65-6348-8096
Macronix (Hong Kong) Co., Limited.
702-703, 7/F, Building 9,
Hong Kong Science Park,
5 Science Park West Avenue, Sha Tin, N.T.
Tel: +86-852-2607-4289
Fax: +86-852-2607-4229
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
60