HD74ALVC16835 18-bit Universal Bus Driver with 3-state Outputs REJ03D0053-0700 (Previous: ADE-205-192E) Rev.7.00 Apr 07, 2006 Description The HD74ALVC16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup register; the minimum value of the register is determined ined by the current sinking capability of the driver. Features • • • • • • Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V) Ordering Information Part Name Package Type HD74ALVC16835TEL TSSOP-56 pin Package Code (Previous code) PTSP0056KA-A (TTP-56DAV) Package Abbreviation T Taping Abbreviation (Quantity) EL (1,000 pcs / Reel) Function Table Inputs H: L: X: Z: ↑: Notes: OE LE CLK A H L L L L L L X H H L L L L X X X ↑ ↑ H L X L H L H X X Output Y Z L H L H *1 Y0 Y0 *2 High level Low level Immaterial High impedance Low to high transition 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low. 2. Output level before the indicated steady-state input conditions were established. Rev.7.00 Apr 07, 2006 page 1 of 11 HD74ALVC16835 Pin Arrangement NC 1 56 GND NC 2 55 NC Y1 3 54 A1 53 GND GND 4 Y2 5 52 A2 Y3 6 51 A3 VCC 7 50 VCC Y4 8 49 A4 Y5 9 48 A5 Y6 10 47 A6 46 GND GND 11 Y7 12 45 A7 Y8 13 44 A8 Y9 14 43 A9 Y10 15 42 A10 Y11 16 41 A11 Y12 17 40 A12 GND 18 39 GND Y13 19 38 A13 Y14 20 37 A14 Y15 21 36 A15 VCC 22 35 VCC Y16 23 34 A16 Y17 24 33 A17 GND 25 32 GND Y18 26 31 A18 OE 27 30 CLK LE 28 29 GND (Top view) Rev.7.00 Apr 07, 2006 page 2 of 11 HD74ALVC16835 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation *3 at Ta = 55°C (in still air) Storage temperature range Symbol VCC Ratings –0.5 to 4.6 Unit V VI VO IIK IOK IO ICC or IGND PT –0.5 to 4.6 –0.5 to VCC+0.5 –50 ±50 ±50 ±100 1 V V mA mA mA mA W Tstg –65 to 150 °C Conditions VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TSSOP Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 1. The input and output negative-voltage ratings may be exceeded if the he input and output clamp current ratings are observed. 2. The input and output positive-voltage ive-voltage ratings may be exceeded up to 4.6 V if the input and output clampcurrent ratings are observed. 3. The maximum power dissipation is calculated using g a junction temperature of 150°C and board trace length of 750 mils. Recommended Operating Conditions Item Symbol VCC Min 2.3 Max 3.6 Unit V Input voltage Output voltage High-level output current VI VO IOH IOL VCC VCC –12 –12 –24 12 12 V V mA Low-level output current 0 0 — — — — — Supply voltage mA Input transition rise or fall rate ∆t/∆v ∆t/∆v — 0 24 10 ns/V Operating free-air temperature Ta –40 85 °C Note: Unused or floating control pins must be held high or low. Rev.7.00 Apr 07, 2006 page 3 of 11 Conditions VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V HD74ALVC16835 Logic Diagram OE CLK LE A1 27 30 28 54 1D C1 CLK 3 Y1 To 17 Other Channels Electrical Characteristics (Ta = –40 to 85°C) Item Input voltage Symbol VCC (V) Min Max Unit VIH 2.3 to 2.7 2.7 to 3.6 2.3 to 2.7 2.7 to 3.6 2.3 to 3.6 2.3 2.3 2.7 3.0 3.0 2.3 to 3.6 2.3 2.3 2.7 3.0 3.6 3.6 3.6 3.0 to 3.6 1.7 2.0 — — VCC–0.2 2.0 1.7 2.2 2.4 2.0 — — — — — — — — — — — 0.7 0.8 — — — — — — 0.2 0.4 0.7 0.4 0.55 ±5.0 ±10 40 750 V VIL Output voltage VOH VOL Input current Off state output current Quiescent supply current IIN IOZ ICC ∆ICC Rev.7.00 Apr 07, 2006 page 4 of 11 Test Conditions V V V µA µA µA µA IOH = –100 µA IOH = –6 mA, VIH = 1.7 V IOH = –12 mA, VIH = 1.7 V IOH = –12 mA, VIH = 2.0 V IOH = –12 mA, VIH = 2.0 V IOH = –24 mA, VIH = 2.0 V IOL = 100 µA IOL = 6 mA, VIL = 0.7 V IOL = 12 mA, VIL = 0.7 V IOL = 12 mA, VIL = 0.8 V IOL = 24 mA, VIL = 0.8 V VIN = VCC or GND VOUT = VCC or GND VIN = VCC or GND One input at (VCC–0.6)V, other inputs at VCC or GND HD74ALVC16835 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit Maximum clock frequency fmax tPLH tPHL 150 150 150 1.0 — 1.0 1.3 — 1.3 1.4 — 1.4 — — — — — — — — — — — — — — — 4.2 4.2 3.6 5.0 4.9 4.2 5.5 5.2 4.5 MHz Propagation delay time 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 ns From (Input) To (Output) A Y LE Y CLK Y Output enable time tZH tZL 2.5±0.2 2.7 3.3±0.3 1.4 — 1.1 — — — 5.5 5.6 4.6 ns OE Y Output disable time tHZ tLZ 2.5±0.2 2.7 3.3±0.3 1.0 — 1.3 — — — 4.5 4.3 3.9 ns OE Y Input capacitance CIN CO 3.0 3.0 3.0 4.5 6.0 7.0 7.0 9.0 9.0 pF Output capacitance 3.3 3.3 3.3 pF Control inputs Data inputs Y ports Setup time tsu 2.5±0.2 2.2 — — ns Data before CLK↑ 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 2.1 1.7 1.9 1.6 1.5 1.3 1.1 — — — — — — — — — — — — — — 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 2.5±0.2 2.7 3.3±0.3 1.0 0.6 0.6 0.7 1.4 1.7 1.4 3.3 3.3 3.3 3.3 3.3 3.3 — — — — — — — — — — — — — — — — — — — — — — — — — — Hold time Pulse width th tw Rev.7.00 Apr 07, 2006 page 5 of 11 Data before LE↓ CLK “H” Data before LE↓ CLK “L” ns Data after CLK↑ Data after LE↓ CLK “H” or “L” ns LE “H” CLK “H” or “L” HD74ALVC16835 Switching Characteristics (cont.) (Ta = 0 to 85°C) Item Symbol CL=0pF *1 CL=50pF CL=0pF *1 CL=50pF CL=50pF CL=50pF Propagation delay time Output rise / fall time VCC (V) tPLH, tPHL 3.3±0.165 3.3±0.165 3.3±0.165 3.3±0.165 *1, 2 tSSO 3.3±0.165 tTLH, tTHL *1 3.3±0.165 Min Typ Max Unit 0.9 1.0 1.5 1.7 1.7 1.0 — — — — — — 2.0 4.5 3.0 4.5 4.8 2.5 ns FROM (Input) TO (Output) A Y CLK Y CLK, A Y Y volts/ ns Notes: 1. This parameter is characterized but not tested. 2. tSSO : Simultaneous switching output time. Operating Characteristics (Ta = 25°C) Item Power dissipation capacitance Symbol Outputs enable Cpd Outputs disable VCC = 2.5±0.2 V VCC = 3.3±0.3 V Typ Typ 22.0 24.5 5.0 6.0 Unit pF Test Conditions CL = 0, f = 10 MHz Test Circuit See under table 500 Ω S1 OPEN GND *1 CL 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN t su / t h / t w t ZH/ t HZ t ZL / t LZ CL Note: GND GND 2 × VCC 30 pF 6.0 V 50 pF 1. CL includes probe and jig capacitance. Rev.7.00 Apr 07, 2006 page 6 of 11 HD74ALVC16835 Waveforms – 1 tf tr 90 % Input VIH 90 % Vref Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND Rev.7.00 Apr 07, 2006 page 7 of 11 HD74ALVC16835 Waveforms – 3 tf Output Control tr VIH 90 % 90 % Vref Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B Vref1 VOL t HZ VOH Vref2 Vref ≈VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1 Notes: Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V VCC 2.7 V 1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH–0.15 V VOH–0.3 V VCC 3.0 V GND GND 1. All input pulses are supplied by generators rators having the following characteristics : PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V) PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V) 2. Waveform–A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform–B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The outputs are measured one at a time with one transition per measurement. Rev.7.00 Apr 07, 2006 page 8 of 11 HD74ALVC16835 IV Characteristics for Register Output (Measured value) Weak condition HIGH Vcc = 3.15 V, Ta = 85°C VOH (V) 0.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.5 3.0 3.5 I OH (mA) -20 -40 -60 -80 -100 Strong condition HIGH Vcc = 3.45 V, Ta = 0°C VOH (V) 0.0 0 I OH (mA) -30 -60 -90 -120 -150 Rev.7.00 Apr 07, 2006 page 9 of 11 0.5 1.0 1.5 2.0 HD74ALVC16835 Weak condition LOW Vcc = 3.15 V, Ta = 85°C 120 100 I OL (mA) 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.5 3.0 3.5 VOL (V) Strong condition LOW Vcc = 3.45 V, Ta = 0°C 200 I OL (mA) 150 100 50 0 0.0 0.5 1.0 1.5 2.0 VOL (V) Rev.7.00 Apr 07, 2006 page 10 of 11 HD74ALVC16835 Package Dimensions JEITA Package Code P-TSSOP56-6.1x14-0.50 RENESAS Code PTSP0056KA-A *1 Previous Code TTP-56DAV MASS[Typ.] 0.32g D F 56 29 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HE *2 E c bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 28 1 e *3 Reference Dimension in Millimeters Symbol L1 bp x Min M A Z A1 θ y L Detail F Rev.7.00 Apr 07, 2006 page 11 of 11 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Nom Max 14.0 14.2 6.10 0.08 0.13 0.18 1.20 0.14 0.19 0.24 0.10 0.15 0.20 0° 8° 7.90 8.10 8.30 0.50 0.08 0.10 0.65 0.4 0.5 0.6 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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