IRDC3823-P1V2 SupIRBuck TM USER GUIDE FOR IRDC3823 EVALUATION BOARD 1.2Vout DESCRIPTION The IR3823 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 3.5mm X 3.5 mm Power QFN package. Key features offered by the IR3823 include selectable Digital Soft Start, precision 0.6Vreference voltage, Power Good, thermal protection, programmable switching frequency, Enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal LDO and pre-bias start-up. Output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous MOSFET for optimum cost and performance and the current limit is thermally compensated. This user guide contains the schematic and bill of materials for the IRDC3823 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3823 is available in the IR3823 data sheet. BOARD FEATURES • Vin = +12V (+ 13.2V Max) •Vout = +1.2V @ 0- 3A • Fs=1000kHz • L= 1.0uH (4.0mm X 4.0mm X 2.1mm, DCR=10.8mΩ) • Cin= 2x10uF (25V, ceramic 1206) + 1X100uF (25V, electrolytic) • Cout=1x22uF (6.3V, ceramic 0805) 5/7/2013 1 IRDC3823-P1V2 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 3A load should be connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I. IR3823 has only one input supply and internal LDO generates Vcc from Vin. If operation with an external Vcc is required, remove R7 and solder a zero ohm resistor for R5. Then an external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin and Vcc/LDO_Out pins should be shorted together for the external Vcc operation. Table I. Connections Connection Signal Name VIN+ Vin (+12V) VIN- Ground of Vin Vout+ Vout(+1.2V) Vout- Ground for Vout Vcc+ Vcc/ LDO_Out Pin Vcc- Ground for Vcc input Enable Enable PGood Power Good Signal Sync Synchronization Gnd Analog ground Vcc: SS time = 1.5m sec SS_Select (Soft-start Selection) Float: SS time = 3m sec Gnd: SS time = 6 m sec LAYOUT The PCB is a 2.6”x 2.2” 4-layer board using FR4 material. All layers use 2 Oz. copper. The PCB thickness is 0.062”. The IR3823 and other major power components are mounted on the top side of the board. Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to IR3823. The feedback resistors are connected to the output at the point of regulation and are located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 5/7/2013 2 IRDC3823-P1V2 Connection Diagram Vin Gnd Gnd Vout Top View Bottom View Fig. 1: Connection Diagram of IR3823 Evaluation Boards 5/7/2013 3 IRDC3823-P1V2 Single point connection between AGnd and PGnd Fig. 2: Board Layout-Top Layer Fig. 3: Board Layout-Bottom Layer 5/7/2013 4 IRDC3823-P1V2 Fig. 4: Board Layout-Mid Layer 1 Fig. 5: Board Layout-Mid Layer 2 5/7/2013 5 1 PG OOD 1 Vcc- 49.9K R17 Vcc+ 1 VCC R9 6 16 4 5 3 1 U1 IR3823 C23 2.2uF 10 11 12 0 ohm R10 SS_Select SW1 PGnd SW PVin C32 1.0uF PG ND N38703 C7 0.1uF 0.1uF C24 R7 0 R5 N/S SW R3 4.02k 2200pF 127 4.02k R2 C8 R4 A R6 20 ohm B L1 1.0uH VCC SS_Se le ct: FLO AT=3m se c, Vcc=1.5m se c, GND=6m se c VCC PGOOD Gnd Gnd Rt_Sy nc COMP FB N/S 1 + C35 N/S C28 N/S 0 ohm R51 N/S R50 C27 N/S C5 N/S C20 N/S C4 10uF C19 N/S C18 N/S C3 10uF G nd C15 22uF 1 1 1 1 1 1 1 C12 0.1uF 1 Vout C1 100uF/25V G nd C16 N/S + G nd C17 N/S C2 N/S Single Point Conne ction Be twe e n AGND and PGND C14 N/S C6 0.1uF Fig. 6: Schematic of the IRDC3823 evaluation board Vin=12V, Vo=1.2V, Iomax=3A 23.2k N/S R11 4.7nF 1.0k SYNC C26 R1 56pF C11 C37 R19 2 SS_Sele 7.5K 1 1 15 Enable 7 Vin 9 Gnd 14 Boot 13 VCC 8 3 4 1 2 R18 1 49.9K 1 Enable 1 Gnd 1 1 5/7/2013 1 Vin Vout- Vout- Vout+ Vout+ (1.2V/3A) Vin- Vin- Vin+ Vin+ (+12V) IRDC3823-P1V2 6 IRDC3823-P1V2 Bill of Materials Item Qty Part Reference Value Description Manufacturer Part Number 1 1 C1 100uF CAP ALUM 100UF 25V 20% SMD Panasonic EEE-1EA101XP 2 2 C3, C4 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M 3 4 C6, C7, C12, C24 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B 4 1 C11 56pF 0603, 50V, NP0, 5% TDK C1608C0G1H560J080AA 5 1 C15 22uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J226M 6 1 C8 2200pF 0603,50V,X7R Murata GRM188R71H222KA01B 7 1 C23 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M 8 1 C26 4700pF 0603, 50V 10% X7R Murata GRM188R71H472KA01D 9 1 C32 1.0uF 0603, 25V, X5R, 10% Murata GRM188R61E105KA12D 10 1 R1 1.0k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1001V 11 2 R2, R3 4.02k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4021V 12 1 R4 127 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1270V 13 1 R6 20 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF20R0V 14 3 R7, R10, R51 0 Thick Film, 0603,1/10W Panasonic ERJ-3GEY0R00V 15 1 R9 23.2k Thick Film, 0603,1/10W Panasonic ERJ-3EKF2322V 16 2 R17, R18 49.9k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V 17 1 R19 7.5k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF7501V 18 1 L 1.0uH SMD, 4.0mmx4.0mmx2.1mm, 10.8mΩ Coilcraft XFL4020-102 19 1 U1 IR3823 3A POL, PQFN 3.5mm x3.5mm IR IR3823 5/7/2013 7 IRDC3823-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, no airflow Fig. 7: Start up at 3A Load with SS_Select pin floating Ch1:Vin, Ch2:PGood, Ch3:Vo ,Ch4:Enable Fig. 9: Start up with 1V Pre Bias , 0A Load, Ch2:PGood, Ch3:Vo Fig. 11: Inductor node at 3A load Ch3:LX 5/7/2013 Fig. 8: Start up at 3A Load with SS_Select pin floating Ch1:Vin, Ch2:Vcc, Ch3:Vo ,Ch4:Enable Fig. 10: Output Voltage Ripple, 3A load Ch2: Vout , Fig. 12: Short circuit (Hiccup) Recovery, with SS_Select pin floating, Ch3:Vout , Ch4:Iout 8 IRDC3823-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-3A, Room Temperature, no air flow Fig. 13: Transient Response, 2.0A to 3A step Ch4-Iout Ch2:Vout 5/7/2013 9 IRDC3823-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-3A, Room Temperature, no air flow Fig. 14: Bode Plot at 3A load shows a bandwidth of 188kHz and phase margin of 53 degrees and gain margin of -10dB 5/7/2013 10 IRDC3823-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-3A, Room Temperature, no air flow Fig 15. Feed Forward for Vin change from 7 to 14V and back to 7V Ch3-Vout Ch4-Vin 5/7/2013 11 IRDC3823-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-3A, Room Temperature, no air flow Fig.16 : Efficiency versus load current Fig.17: Power loss versus load current 5/7/2013 12 IRDC3823-P1V2 THERMAL IMAGES Vin=12.0V, Vo=1.2V, Io=3A, Room Temperature, No Air flow Fig. 19: Thermal Image of the board at 3A load Test point 1 is IR3823 Test point 2 is inductor 5/7/2013 13 IRDC3823-P1V2 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 20: PCB Metal Pad Spacing (all dimensions in mm) 5/7/2013 14 IRDC3823-P1V2 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 21: Solder Resist (all dimensions in mm) 5/7/2013 15 IRDC3823-P1V2 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses. Figure 22: Stencil Pad Spacing (all dimensions in mm) 5/7/2013 16 IRDC3823-P1V2 PACKAGE INFORMATION Figure 23: Package Dimensions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 5/7/2013 17