Application Note AN-1169 IRPLLED5 40V/1.4A Low Voltage LED Driver using IRS2548D By Peter B. Green Table of Contents Page 1. Introduction…………………………………………………….………...…2 2. PFC Section………………………………………………………………...3 3. LLC Resonant Half Bridge Section……………………………………....8 4. Transformer and Resonant Circuit Design...........................................15 5. IRPLLED5 Board Schematics..............................................................23 6. Auxiliary VCC Supply...........................................................................27 7. Magnetic Specifications.......................................................................28 8. Output Current Regulation...................................................................31 9. 0 to 10V Dimming................................................................................32 10. Test Results ......................................................................................33 11. Bill of Materials ………………………..………………...…………........37 12. PCB Layout ……………………………………………...….....…..........39 www.irf.com AN-1169 1 EVALUATION BOARD - IRPLLED5 1. Introduction Solid state light sources are now available that offer viable alternatives to Fluorescent and HID lamps and far surpass incandescent lamps. Luminous efficacy expressed in Lumens per Watt has now reached levels enabling LEDs to be used for general illumination. High brightness LEDs also possess the added advantages of longer operating life span up to 50000 hours and greater robustness than other less efficient light sources making them suitable for outside applications such as street lighting. High power LEDs are ideally driven with constant regulated DC current, requiring a "driver" or "converter" to provide the required current from an AC or DC power source. A two stage power converter based around the IRS2548D PFC plus half bridge LED driver IC provides a controlled current output over a wide AC line voltage input range with high power factor and low THD. The IRPLLED5 evaluation board is an off line isolated low voltage / high output current LED driver designed to supply a 1.4A regulated DC output current over a voltage range of 30V to 60V operating from an AC line input voltage between 90 and 305VAC 50/60Hz. It also includes 1-10V dimming capability from 0 to 100% of light output. The outputs of this LED driver are fully protected against short circuit and limit the open circuit voltage to below 60VDC for safety compliance. EMI Filter Rectifier Half Bridge Stage PFC Synchronous Rectification Output Control LEDs Line IRS2548D Interface Dim Input PFC Driver Half-Bridge Driver IR1168 Figure 1: IRPLLED5 Block Diagram www.irf.com AN-1169 2 2. PFC Section The IRPLLED5 board includes a power factor correction Boost converter front end stage, which operates in critical conduction mode. During each switching cycle of the PFC MOSFET the IRS2548D detects the point at which the inductor current has discharged to zero thereby detecting when the stored energy has been completely transferred to the output. The PFC MOSFET is then turned on to start the next switching cycle. DPFC LPFC (+) DC Bus + MPFC CBUS (-) Figure 2: PFC Boost converter circuit. When the switch MPFC is turned on the inductor LPFC is connected between the rectified line input (+) and (-) return causing the current in LPFC to rise linearly. When MPFC is turned off LPFC current is redirected from the rectified line input (+) bus to the DC bus capacitor CBUS through diode DPFC. The stored energy in LPFC is thereby transferred to CBUS. MPFC is switched on and off at a high frequency and the voltage on CBUS charges to a defined voltage. The PFC feedback loop of the IRS2548D regulates this voltage to by continuously monitoring the DC bus voltage and adjusting the on-time of MPFC accordingly. Negative feedback control is performed by a transconductance error amplifier (OTA) with a slow loop speed such that the average inductor current smoothly follows the low frequency line input voltage. This produce a sinusoidal input current yielding high power factor and low THD. The on-time of MPFC is therefore effectively constant (with an additional modulation to be discussed later) only changing over several cycles of the line voltage. With fixed on-time and off-time determined by the inductor current discharging to zero the switching frequency changes from a high frequency near the zero crossing of the AC input line voltage to a lower frequency at the peaks (Figure 3). www.irf.com AN-1169 3 V, I t Figure 3: Sinusoidal line input voltage (solid line), triangular PFC Inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the AC line. When the line input voltage is low close to the zero crossing, the inductor current also rises to a relatively low peak so the discharge time is also shorter resulting in a high switching frequency. When the input line voltage is high near the peak the inductor current rises to a much higher peak and the discharge time is therefore longer resulting in a lower switching frequency. The PFC control circuit of the IRS2548D (Figure 4) includes five control pins: VBUS, COMP, ZX, PFC and OC. The VBUS pin measures the DC bus voltage via an external resistor voltage divider. The COMP pin voltage at the error amplifier output sets the ontime of and the speed of the feedback loop with an external capacitor. The ZX (zero crossing) pin detects when the inductor current discharges to zero during the off time using a secondary winding from the PFC inductor. The PFC pin is the gate driver output for the external MOSFET, MPFC and the OC pin senses the current flowing through MPFC providing cycle-by-cycle over-current protection. LPFC (+) DFPC RVBUS1 RZX RVBUS2 VBUS ZX PFC Control CBUS PFC RPFC MPFC OC COMP COM ROC RVBUS CCOMP (-) Figure 4: IRS2548D simplified PFC control circuit. www.irf.com AN-1169 4 The VBUS pin is regulated against a fixed internal 4V reference voltage for regulation of the output DC bus voltage (Figure 5). The feedback loop error amplifier sinks or sources a current to the external capacitor at the COMP pin. The IRS2548D PFC section operates in voltage mode with the COMP pin voltage providing the threshold for the charging the internal timing capacitor (C1, Figure 5) to control the on-time of MPFC. Fault Mode Signal VBUS 1 4.0V VCC COMP4 OTA1 4.3V RS3 COMP5 COMP 3 M1 S Q R Q WATCH DOG TIMER COMP2 Discharge VCC to UVLO- 3.0V C1 M2 S Q R1 R2 Q 5 PFC 6 OC 1.2V RS4 COMP3 ZX 4 5.1V 2.0V Figure 5: IRS2548D detailed PFC control circuit. The zero current level is detected by a secondary winding on LPFC connected to the ZX pin through an external current limiting resistor RZX. A positive-going edge exceeding the internal 2V threshold (VZXTH+) signals the beginning of the off-time. A negative-going edge on the ZX pin falling below 1.7V (VZXTH+ VZXHYS) will occur when the LPFC current discharges to zero, which signals the end of the off-time and MPFC is turned on again (Figure 6). The cycle repeats itself indefinitely until the PFC section is disabled due to a fault detected by the half-bridge driver section (Fault Mode), an over-voltage or condition on the DC bus or the negative transition of ZX pin voltage does not occur. Should the negative edge on the ZX pin fail to be detected for any reason MPFC will remain off until the internal “watch-dog” timer forces a restart. Watch-dog pulses occur every 400us (tW) until a correct positive and negative-going signal is detected on the ZX pin and normal PFC operation is resumed. Should the OC pin exceed the 1.2V (VOCTH+) over-current threshold during the on-time, the PFC output will turn off. The circuit will then wait for a negative-going transition on the ZX pin or a forced turn-on from the watch-dog timer to turn the PFC output on again. www.irf.com AN-1169 5 ILPFC ... PFC ... ZX ... 1.2V OC Figure ... 6: Inductor current, PFC pin, ZX pin and OC pin timing diagram. A fixed on-time of MPFC over an entire cycle of the line input voltage produces a peak inductor current that naturally follows the sinusoidal shape of the line input voltage. The smoothed averaged line input current is in phase with the line input voltage to provide a high power factor. Some harmonic distortion of the line current still remains mostly due to cross-over distortion near the zero-crossings. To achieve low THD additional on-time modulation circuit is built into the IRS2548D PFC control. This function dynamically increases the on-time of MPFC as the line input voltage nears the zero-crossings (Figure 7). This causes the peak LPFC current, and therefore the smoothed line input current, to increase slightly higher near the zero-crossings of the line input voltage. ILPFC 0 PFC pin 0 near peak region of rectified AC line near zero-crossing region of rectified AC line Figure 7: On-time modulation circuit timing diagram Should over-voltage occur on the DC bus and the VBUS pin exceed the internal 4.3V threshold (VBUSOV+) the PFC output will transition to switch off MPFC. www.irf.com AN-1169 6 When the DC bus decreases again and the VBUS pin voltage decreases below the internal 4.15V threshold (VBUSOV-) PFC operation is resumed. The PFC inductor value can be calculated from the following formula: LPFC 2 (VBUS − 2 ⋅ VAC MIN ) ⋅ VAC MIN ⋅η = 2 ⋅ f MIN ⋅ POUT ⋅ VBUS [Henries] where, VBUS VAC MIN η f MIN POUT = = = = = DC bus voltage Minimum RMS AC input voltage PFC efficiency (typically 0.95) Minimum PFC switching frequency at minimum AC input voltage System output power The peak current in the PFC inductor is given by: i PK = 2 ⋅ 2 ⋅ POUT VAC MIN ⋅ η [Amps Peak] The PFC inductor should be designed so that it does not saturate at i PK at maximum operating temperature. This involves adequate sizing of the core and air-gap. The value of the PFC current sense resistor (ROC) is calculated from the following formula and rounded up to the nearest preferred value. ROC = 1.25 i PK www.irf.com where VCSTH+ = 1.25V [Ohms] AN-1169 7 3. LLC Resonant Half Bridge Section The run frequency is programmed with the timing resistor RFMIN at the FMIN pin. The graph in Figure 6 (RFMIN vs. Frequency) can be used to select RFMIN value for desired run frequency. 180 Frequency (KHz) 160 140 120 100 80 60 40 20 10 15 20 25 30 35 40 45 50 Equivalent RFMIN (Kohms) Figure 8: Graph of frequency against RFMIN The maximum current is programmed with the external resistor RCS and an internal threshold of 1.25V (VCSTH+). This threshold determines the overcurrent limit of the system: I MAX = 1.25 RCS [Amps Peak] 1.25 I MAX [Ohms] or RCS = The half-bridge LLC resonant converter offers high efficiency due to zero voltage switching operation which also eliminates switching noise. Since the switching losses are negligible no heat sinking is required for the half-bridge MOSFETs. This topology can achieve high power density due to the efficient utilization of the transformer operating in two quadrants of the B-H curve. The resonant topology requires an additional series inductance to be added to the circuit in order to construct a complex resonant tank with Buck-Boost transfer characteristics in the soft switching region. Although it is possible to incorporate this additional www.irf.com AN-1169 8 inductance into the transformer, for simplicity the IRPLLED5 design uses a standard transformer design with the additional inductance added externally. The typical power stage schematic for this topology is shown in figure 9. M1 D1 HO Vin VS Lr n:1:1 Lm M2 LO COUT LOAD D2 Cr Figure 9: Typical schematic of a DC-DC half-bridge resonant converter The half-bridge switches operate at 50% duty cycle where the output voltage is regulated by varying the switching frequency. Since the IRPLLED5 drives an LED load which can be approximately represented by a voltage source with a series resistor. The current is regulated by adjusting the half-bridge switching frequency. The frequency is adjusted to provide the required drive current for varying numbers of LEDs connected to the output up to a total series voltage of 60V. The LLC half-bridge stage has two resonant frequencies, the first determined by the series inductor (Lr) and resonant capacitor (Cr) and the second determined by the transformer magnetizing inductance (Lm) and the resonant capacitor. While the frequency remains in the inductive region soft switching will occur. Below Resonant ZVS Region 2nVout Vin 2 1 3 Below Resonant ZCS Region 1 Above Resonant ZVS Region fmin Fr1 fmax Frequency Figure 10: Typical frequency response of an LLC resonant converter www.irf.com AN-1169 9 The characteristics of an LLC resonant converter can be divided into three regions based on the three different modes of operation. The first region is for switching frequency above the resonant frequency Fr1: 1 Fr1 = 2π Lr ⋅ C r In region 1 of figure 10 (the purple shaded area) the switching frequency is higher than resonant frequency Fr1. The converter operation is very similar to a series resonant converter. Here Lm never resonates with resonant capacitor (Cr) it is clamped by the output voltage and acts as the load of the series resonant tank. This is the inductive load region and the converter is always under ZVS operation regardless of the load condition. In region 2 (the pink shaded area) the switching frequency is higher than the lower resonant frequency but lower than Fr1. The lower resonant frequency varies with load so the boundary of region 2 and region 3 traces the peak of the family load vs gain curves. In this complex region the LLC resonant operation can be divided into two time intervals; in the first time interval Lr resonates with Cr and Lm and is clamped by output voltage. When the current in the resonant inductor Lr resonates back to the same level as the magnetizing current Lr and Cr stop resonating. Lm now participates in the resonant operation and the second time interval begins. During this time interval the dominant resonant components become Cr and Lm in series with Lr. The ZVS operation in region 2 is guaranteed by operating the converter to the right side of the load gain curve. For a switching frequency below resonant Fr1 it could fall in either region 2 or region 3 depending on the load condition. In the ZCS range below fr1, the LLC resonant converter operates in capacitive mode; M1 and M2 are hard switching with high switching losses. For this reason ZCS operation should always be avoided. The waveforms in figures 11,12 and 13 show the behavior of the system in each of the operating regions. The typical voltage conversion ratio of a LLC resonant converter is shown in Figure 12. www.irf.com AN-1169 10 HO LO VCr VS ILr ILm ID1 ID2 Above resonant (Fsw>Fr1) ZVS switching Figure 11: Typical waveform of above resonant ZVS switching LO HO VS VCr ILr ID2 ILm ID1 Output Current DCM Below resonant (Fsw<Fr1) ZVS switching Figure 12: Typical waveform of below resonant ZVS switching The waveforms in figure 12 indicate that the secondary rectifier diode currents move from continuous current mode (CCM) to discontinuous current mode (DCM) when the switching frequency changes from above resonant ZVS to below resonant ZVS due to load increasing. The ripple voltage on the resonant capacitor Cr also increases in the below resonant ZVS mode. www.irf.com AN-1169 11 HO LO VCr VS ILr ILm Output Current ID2 ID1 Below resonant (Fsw<Fr1) ZCS switching Figure 13: Typical waveform of below resonant ZCS switching In ZCS mode, the two switching devices M1 and M2 are turned off under zero current condition. The turn-on of the two switches is hard switched (non-ZVS). The turn-on switching loss is high especially under high voltage bus voltage. The resonant capacitor Cr also has high voltage stress. ZCS operation should always be avoided. Q - Low (no load) 2nVout Vin Q - High (full load) Frequency modulation range @ low line 2nVout Vinmin Frequency modulation range @ high line 2nVout Vinmax Over load or Short Circuit Fr1 fmin fmax Frequency Figure 14: Typical voltage conversion ratio of a LLC resonant converter With a regulated DC bus voltage supplied from the PFC stage the converter switching frequency can be adjusted to regulate the output voltage and current over the load range keeping the same conversion ratio over the family of curves with different Q. Given a fixed load the converter adjusts the switching frequency along the corresponding load line to regulate the output over input voltage range. www.irf.com AN-1169 12 The procedure used to design the LLC resonant half-bridge converter uses the First Harmonic Approximation (FHA) to obtain an equivalent circuit model. All the components are moved to the primary side to simplify analysis. Rac represents the equivalent load resistance in parallel with transformer primary inductance Lm. M1 D1 Cr Vin n:1:1 Lr M2 Lm COUT LOAD D2 Cr 2⋅ Vin Lr n ⋅ Vout ⋅ π 4 π Vf und Rac Rac 2 n ⋅ RLOAD⋅ 8 2 π Lm Figure 15: The FHA equivalent circuit The input voltage of the resonant tank is a square wave with amplitude equal to the DC bus voltage Vbus. The fundamental component of the square waveform is: 2 ⋅Vbus π sin(ω ⋅ t ) The output voltage of the resonant tank is the voltage across Lm. It is very close to a square waveform with amplitude swinging from − n ⋅ Vout to + n ⋅ Vout . So the fundamental component of the output square waveform is: 4 ⋅ n ⋅ Vout π www.irf.com sin(ω ⋅ t ) AN-1169 13 The power dissipation on the equivalent AC resistor is equal to the power dissipation of the load represented by a resistor RLOAD, which can be derived by dividing the maximum output voltage by the output current, written as: 4 ⋅ n ⋅ Vout 2 Vout 2π = RLOAD Rac 2 Re-arranging the formula gives the equivalent AC resistor: Rac = 8 ⋅ n2 R LOAD π2 The transfer ratio of the equivalent circuit can be obtained as following: j ⋅ ω ⋅ Lm⋅ Rac j ⋅ ω ⋅ Lm+ Rac M j⋅ ω⋅ Lr + 1 + j⋅ ω⋅ Cr j⋅ ω⋅ Lm⋅ Rac j⋅ ω⋅ Lm + Rac Simplifying to: 1 M 1+ Lr Lm − 1 + 2 ω ⋅ Lm⋅ Cr jω⋅ Lr Rac − j ω⋅ Cr⋅ Rac With the following definitions, calculation of M can be further simplified: Fr1 = k= 1 , 2π Lr ⋅ C r Lm , Lr Rac = x= Fsw , Fr1 8 ⋅ n 2 ⋅ RLOAD π 2 x , Lr ⋅ C r ϖ = 2πFsw = 2π ⋅ x ⋅ Fr1 = Q= , 2πFr1 ⋅ Lr 1 = Rac 2πFr1 ⋅ C r ⋅ Rac 1 M 1+ 1 ⋅ 1 − k + j⋅ Q⋅ x − 2 x 1 1 x Or, M 1 2 1 + 1 ⋅ 1 − 1 + Q⋅ x − 2 k x www.irf.com AN-1169 1 2 x 14 Per Figure 15, M is also equal to the output voltage to bus voltage ratio: M = n ⋅ Vout ⋅ 2⋅ 4 π = Vout ⋅ 2 ⋅ n Vbus Vbus π So the conversion ratio of output voltage Vout to bus voltage Vbus is: Vout M = Vbus 2 ⋅ n 4. Transformer and Resonant Circuit Design The system input data: Parameter Vbusmax Vbusmin Vbusnom Vout Iout Fr1 Fmax Dmax Unit V V V V A kHz kHz Description The maximum DC bus voltage The minimum DC bus voltage The nominal DC bus voltage The DC output voltage The output load current The resonant frequency The maximum switching frequency The maximum duty-cycle Transformer core size Value 480 440 460 48 1.4 60 120 0.5 E32/16/9 Note: Typically Fmax < 2 x Fr1 becuase the parasitic capacitance in the system introduces a third resonant frequency that could cause the output voltage to increase with switching frequency at no load if the maximum switching frequency is higher than the limit. Step 1: Calculate the transformer turns ratio n= Vbus(max) , 2 ⋅ Vout n= 480 =5 2 ⋅ 48 The transformer turns ratio is calculated with the maximum input voltage to make sure the output is always under regulation, including the worst case high-line voltage and no load condition. www.irf.com AN-1169 15 Step 2: Choose k value k is the ratio between the transformer magnetizing inductance and the resonant inductance. Smaller k value gives steeper gain curve, especially at the below resonant ZVS region as shown in figure 16. The output voltage is more sensitive to frequency variation with smaller k factor. 3 2.5 k=5 2 1.5 k=10 1 0.5 0 Figure16: k factor A higher k value results in higher magnetizing inductance and thus lower magnetizing current in the transformer primary winding resulting in lower circulating power losses. However higher magnetic inductance could also cause non-ZVS switching at high line and zero load condition where the circulating current is too small to fully charge / discharge the VS node during dead-time. The recommended range of k is from 3 to 10. In this case k = 7 is chosen. Step 3: Calculate Qmax to maintain ZVS operation at the maximum load under the minimum input voltage The input impedance of the equivalent resonant circuit (Figure 15) is given by: Zin j⋅ ω⋅ Lr + 1 j⋅ ω⋅ Cr 2 2 Zin Q⋅ Rac k ⋅x ⋅Q 2 2 2 1 + k ⋅x ⋅Q www.irf.com + j⋅ ω⋅ Lm⋅ Rac j⋅ ω⋅ Lm + Rac + j x − AN-1169 1 x + x⋅ k 2 2 2 1 + k ⋅x ⋅Q 16 To keep the converter working in soft switching mode the operating point should remain in the ZVS region as shown in figure 10. The ZVS-ZCS boundary line is defined by the phase angle of Zin Ф(Zin)= 0 (the boundary condition between capacitive and inductive load), i.e. the imaginary part of Zin is zero. With this condition we can calculate the maximum Q which allows the converter to stay in ZVS. The maximum Q happens at the minimum input voltage and the maximum load. 1 + k⋅ 1 − Qmax 1 k ⋅ 1 2 Mmax 1 + k⋅ 1 − 2 Mmax − 1 1 k ⋅ Vout 2⋅ n ⋅ Vinmin 1 2 2 2⋅ n ⋅ Vout − 1 Vinmin Where Mmax is the maximum conversion ratio at the minimum input voltage, Q max = 0.523 Step 4: Calculate the minimum switching frequency The minimum switching frequency occurs at the maximum load and minimum input voltage with the previous calculated maximum Qmax. As Qmax is defined by Im(Zin)=0, x⋅ k 0 x − 1 + x 2 2 2 1 + k ⋅ x ⋅ Qmax The Fmin can be calculated with: xmin 1 1 1 + k⋅ 1 − 2 Mmax 1 1 + k⋅ 1 − 2n ⋅ Vout Vinmin 1 2 x min = 0.736 F min = x min⋅ Fr1 = 44.2 KHz Step 5: Calculate Lr, Cr and Lm As Qmax happens at the maximum load, so the resonant components Lr, Cr and Lm can be calculated per the Qmax value that had obtained in step 3: RLOAD = www.irf.com Vout 48V = = 34.3Ω Iout 1.4 A AN-1169 17 Rac = Lr = Cr = 8 ⋅ n 2 ⋅ RLOAD π2 = 8 × 5 2 × 34.5 π2 = 699Ω Q max⋅ Rac 0.523 × 699 = = 1.32mH 2 ⋅ π ⋅ Fr1 2 ⋅ π ⋅ 44.2 ⋅ 10 3 1 1 = = 9.85nF 2 ⋅ π ⋅ Fr1 ⋅ Q max⋅ Rac 2 ⋅ π ⋅ 44.2 ⋅ 10 3 × 0.523 × 699 Choose the nearest standard capacitor value for Cr, C r = 10nF Recalculate Fr1 to keep the same Qmax with the selected Cr capacitor: Fr1 = 1 = 43.5kHz 2 ⋅ π ⋅ C r ⋅ Q max⋅ Rac Recalculate Lr with the selected Cr and Fr1: Lr = Q max⋅ Rac = 1.33mH 2 ⋅ π ⋅ Fr1 The actual Lr value should be lower than the calculated value to stay in ZVS region. Now calculate Lm value based on Lr and the k factor that preset in step 2: Lm = Lr ⋅ k = 1.33 × 7 = 9.31mH Step 6: Calculate transformer primary and secondary turns The standard half-bridge equation for the transformer turns number calculation is used here: Np = Vin min⋅ D max 2 ⋅ ∆B ⋅ Ae ⋅ F min With ∆B = 0.2T , Ae = 0.83cm (ETD49), F min = 28kHz , Vin min = 440V , D max = 0.5 2 Np = 440 × 0.5 × 10 = 235 2 × 0.2 × 0.83 × 28 Ns = www.irf.com Np 235 = = 47 n 5 AN-1169 18 The transformer was designed to be capable of operating down to 28kHz to provide a safety margin although the minimum frequency is 43.5kHz in this design. Np was rounded to the nearest number divisible by n so that Ns would come out as a whole number. Step 7: Calculate transformer primary and secondary current In most LLC converter designs the minimum switching frequency is set below the resonant frequency Fr1 in order to maintain output voltage regulation at low line and full load. When the switching frequency is lower than the resonant frequency Fr1, the current waveform is shown as in figure 17. VS VCr I1 ILr ILm Figure17: Transformer primary current at full load and minimum input voltage I1 is the current where the resonant current in Lr equals the magnetizing current in Lm. This is also the point where Cr and Lr cease to resonanate for the first halfperiod of Fr1. At this point, no more energy is delivered to the load and the output diodes are not conducting. Cr starts to resonate with Lr + Lm until the switching MOSFETs changes state. I1 can be calculated as: I1 = n ⋅ Vout = 0.15 A 2 ⋅ Lm ⋅ 2 ⋅ Fr1 The peak and RMS value of primary current can be estimated as: Iout ⋅ π 2 Ipri ( pk ) = + I1 = 0.47 A 2⋅n Ipri( pk ) IpriRMS = = 0.33 A 2 2 The RMS current is calculated by assuming a purely sinusoidal current waveform. The actual primary RMS current is therefore higher than the calculated value. The current in each secondary winding is very close to a half-sinusoid, thus the peak and RMS current can be estimated by: www.irf.com AN-1169 19 Ispk = Iout ⋅ π = 2.2 A 2 Isrms = Iout ⋅ π = 1.1A 4 The wire gauge of primary and secondary windings should be selected according to the calculated RMS current. Step 8: Calculate resonant capacitor voltage The Cr waveform is shown as in Figure 18: VS Vin VCr Vin/2 ILm ILr Figure 18: Typical resonant tank voltage and current waveforms ILm is the transformer primary magnetizing current, not including the current delivered to the secondary load through an ideal transformer in parallel with Lm. The difference between ILr and ILm is the output current. M1 Ideal Transformer D1 Cr M2 Lr ILr Lm ILm COUT Iout/n LOAD D2 Figure 19: Lm and ideal transformer www.irf.com AN-1169 20 The VCr voltage reaches its peak when Lr current is crossing zero and it is at the mid-point of the input voltage when Lr current reaches its peak. The Cr voltage is at the maximum value when the VS node is at zero and is at the minimum value when the VS node is equal to Vin. VCrmin and VCrmax can be calculated as: VC r max = n ⋅ Vout + Ipri ( pk ) × Lr Cr VC r min = Vin − n ⋅ Vout − Ipri ( pk ) × Lr Cr The peak to peak voltage ripple of VCr is VCrmax-VCrmin: VC rpk _ pk = 2n ⋅ Vout + 2 ⋅ Ipri ( pk ) × Lr − Vin Cr It can be seen that the maximum peak-to-peak voltage occurs at the maximum load and the minimum DC input Vinmin, the switching frequency is at the minimum Fmin. In this example: Vcrpk _ pk = 2 × 5 × 48V + 2 × 0.47 A × 1.33mH − 460V = 363V 10nF The resonant capacitor Cr should be selected according to the capacitance value together with its voltage and current rating. A Polypropylene film capacitor should be used for minimum lower power loss. Polypropylene film capacitors are rated at DC voltage or 50Hz AC voltage with voltage de-rating at high frequency. The ability to withstand high frequency voltages is limited by thermal losses (power dissipation) and peak current capability. Even though the calculation result shows the maximum AC RMS voltage is 363V, a capacitor with higher voltage rating should be selected according to its frequency curve. Below is an example of EPCOS MKP capacitor B32612 (1000Vdc/250Vac). www.irf.com AN-1169 21 Figure 20: Vrms vs. frequency curve of MKP capacitor B32612 @ Ta<=90°C In practice the transformer (T1) used on the IRPLLED5 board has a magnetizing inductance of 12mH and the series resonant inductor (L5) has a value of 1.5mH. This allows a low cost off the shelf inductor to be used for L5 while maintaining a similar ratio between Lm and Lr. www.irf.com AN-1169 22 ENN 1 2 3 4 5 2 DIM 3 4 www.irf.com 1 BR1 DF10S AN-1169 100nF C2 F1 8 1 L2 3n3 C13 L1 D2 DL4148 22K R16 14 2 5 6 7 C1 220nF X2 R13 0.5R R1 100R M1 IPP60R250CP VDR1 C36 10nF 1K R14 D1 US1J-13 R4 15K R3 820K R2 820K 1.5mH L7 47K R12 C6 1 IC1 C8 470pF C10 470pF 680nF R7 15K 7 6 5 4 3 2 47K R10 HO VCC VB VS CS LO COM C9 100nF IRS2548D ENN OC PFC ZX COMP FMIN VBUS 14 8 9 10 11 12 13 C7 470pF C5 100nF 10R R15 47K R11 C12 100nF N/F IC6 PC357 _VCC R53 330K R52 330K R49 R54 330K C4 47uF/250V + C3 + 47uF/250V C11 220nF X2 1 P1 C35 100nF 1K R6 1 _COM IC5 PC357 15R R9 15R R8 R5 1R M3 IRFBC30 M2 IRFBC30 1 _VS COM OPTO1-K OPTO1-A VCC VS OPTO2-K OPTO2-A VBUS VBR+ 5. IRPLLED5 Board Schematics 23 ISO-RTN www.irf.com AN-1169 24 COM VBR+ C14 100nF/500V US1J-13F D7 D17 2.7V 2 1uF 4 3 1 C17 R63 100K R57 100K R56 100K R55 100K CS VDC ZX COM PFC VCC C41 10uF/50V COMP VBUS IC2 IRS2500 + 5 6 7 8 C16 1nF/1kV C15 10uF 10R R58 1N4148 D14 1N4148 D16 D4 US1J-13 R26 100K/1W 2 6 4 5 R59 2.2 M6 SPA03N60C3 3 1 T2 R60 1K D15 1N4148 + C40 33nF US1B-13F D6 C18 47uF/50V D5 US1B-13F L4 10uH TDK NLCV R24 1K C20 + 0.1uF/25V C21 47uF/50V D8 LED C19 0.1uF/25V L3 10uH TDK NLCV R25 33R R62 10K R61 43K VCC_P ISO-RTN VCC_S VCC_S OPTO1-K OPTO1-A COM VS R50 6K8 R27 12K 1.5mH L5 5V C22 10nF T1 LM4040D50 D12 R28 4.7K 7 12mH 1 VTR 1 R30 1K C23 0.1uF R31 33K 0.275V R29 14.3K 8 10 12 14 10R VD2 VS2 D9 IR11682 VD1 VS1 VCC GND Gate1 Gate2 IC3 D10 1N4148 4.7uF C24 1N4148 IC4 LM358N(8) 1 1IN- 1OUT 7 1IN+ 2OUT 2IN+ 2IN- C39 N/F R51 39K 2 3 5 6 330K R32 4 3 2 1 R39 M5 IRFR24N15D 10R R38 M4 IRFR24N15D 8 VSS VCC AN-1169 4 www.irf.com 25 8 5 6 7 R33 2K2 C25 D11 1N4148 R34 1.5K 1uF C26 0.1uF N/F 1K C37 R36 15K R35 C27 10uF 220uH L6 C28 10uF 0.22/1W R37 ISO-RTN OPTO2-A OPTO2-K VOUT- VOUT+ ISO-RTN DIM VCC-S C29 1uF C30 100nF R41 47K R40 18K D13 10V R42 10K C34 10uF R44 43K R43 10K C31 1uF 100K 2.2K R47 R46 C38 1nF Q1 MMBT2907 R45 390 C32 22nF 5 6 2 3 1N4148 IN2(+) IN2(-) IN1(-) OUT1 IN1(+) OUT2 IC7 LM393 D3 COM 4 VCC AN-1169 8 www.irf.com 26 1 7 R48 4K7 IC8 PC357 C33 100nF ENN VCC 6. Auxiliary VCC Supply The IRPLLED5 LED driver board requires two low voltage power supplies to provide VCC voltages for the primary and secondary circuitry. The primary circuitry including the IRS2548D (IC1) is supplied by VCC_P and the secondary circuitry including the IR11682 synchronous rectification controller (IC3) is supplied by VCC_S. The VCC_P supply does not require safety isolation but the VCC_S supply does, since it is connected to the isolated output circuitry of the driver. The system utilizes PWM dimming that pulses both the half-bridge drive and the PFC on and off in order to adjust the LED light level in burst mode. It is not possible to obtain VCC_P and VCC_S from the PFC or from the half-bridge by means of a charge pump since this voltage is interrupted during dimming. At low dimming levels the system would be switching for insufficient time to maintain the VCC supplies. The system can be dimmed all the way to zero output where it would be impossible to supply any low voltage circuitry with a charge pump. A small Flyback power supply supplied by the rectified AC line voltage has been used to produce VCC_P and VCC_S independent of the PFC and half-bridge switching operations. The Flyback converter is based on the IRS2500 (IC2) SMPS/PWM controller with a 600V switching MOSFET (M6) in conjunction with the Flyback inductor (T2). On startup C15 is charged from the rectified AC line through R55,R56 and R57 until the UVLO is reached and IC2 starts to provide gate drive to M6. C15 is required to be 10uF in order that the system can continue to switch long enough for VCC_P to come up and take over supplying VCC to IC2. An additional isolated winding on T2 provides VCC_S. An LED (D8) has been included on the board to indicate that this auxiliary power supply circuit is operating. The voltages provided at VCC_P and VCC_S are regulated by IC2 at approximately 14V. Voltage feedback is provided via R61 and R62 dividing 14V down to the 2.5V regulation voltage of the IRS2500. Primary peak current limiting is provided through R59 which prevents the primary current of T2 reaching a high enough level for saturation to occur. Primary side cycle by cycle peak current limit also prevents damage occurring if either VCC_P or VCC_S become short circuited. In this design the Flyback converter is operating in discontinuous conduction mode (DCM) using the zero crossing detection input of IC2 to produce a fixed off time determined by the time constant of R60 and C40. During the period of the switching cycle when M6 turns off, the voltage at T2 pin 6 transitions from negative to positive and C40 is charged through D15. When all of the energy stored in T2 has been transferred the voltage at pin 6 of T2 drops to zero and C40 discharges through R60. When the voltage at the ZX input of IC2 drops below an internal threshold the start of the next cycle is triggered. Since the power requirement for this Flyback converter is less than one Watt, the off time can be very long compared to the on time and the conduction time in which energy is transferred to the VCC_P and VCC_S outputs. The end result is a power supply operating within a fairly narrow frequency range determined by R60 and C40. www.irf.com AN-1169 27 7. Magnetics Specifications PFC INDUCTOR SPECIFICATION Supplier: Murata CORE SIZE E32/16/9 (EF32) BOBBIN HORIZONTAL Part Number: CD1488C PINS 14 Philips 3C85, Epcos N27 or equivalent CORE MATERIAL PRIMARY INDUCTANCE 0.95 mH AIR GAP LENGTH 1.0 mm PRIMARY PK TO PK VOLTAGE 500 Vpk MAXIMUM CORE TEMPERATURE 100 ºC 2000 V WINDING ISOLATION (Pri to Sec) WINDING START PIN FINISH PIN Primary Secondary TURNS WIRE DIAMETER (mm) 1 7 83 5 Strands of AWG 32 14 8 8 1 Strand of AWG 32 ELECTRICAL LAYOUT PHYSICAL LAYOUT TOP VIEW 5.08mm 22.4mm 5.08mm 37.5mm TEST (TEST FREQUENCY = 50kHz) PRIMARY WINDING INDUCTANCE MIN 0.85 SECONDARY WINDING RESISTANCE MAX 0.1 www.irf.com AN-1169 mH MAX 1.05 mH Ohms 28 TRANSFORMER SPECIFICATION Supplier: Murata CORE SIZE E32/16/9 (EF32) BOBBIN HORIZONTAL Part Number: CD1490C PINS 14 Philips 3C85, Epcos N27 or equivalent CORE MATERIAL PRIMARY INDUCTANCE 12 mH AIR GAP LENGTH 0.4 mm PRIMARY PK TO PK VOLTAGE 500 Vpk MAXIMUM CORE TEMPERATURE 100 ºC 2000 V WINDING ISOLATION (Pri to Sec) WINDING START PIN FINISH PIN TURNS WIRE DIAMETER (mm) 1 7 235 1 Strand of AWG 32 Secondary (1) 14 12 47 5 Strands of AWG 32 Secondary (2) 10 8 47 5 Strands of AWG 32 Primary ELECTRICAL LAYOUT PHYSICAL LAYOUT TOP VIEW 5.08mm 22.4mm 5.08mm 37.5mm TEST (TEST FREQUENCY = 50kHz) PRIMARY WINDING INDUCTANCE MIN 11 mH SECONDARY WINDING RESISTANCE MAX 0.1 Ohms www.irf.com AN-1169 MAX 13 mH 29 FLYBACK INDUCTOR SPECIFICATION Supplier: Murata Part Number: CD1491C E20/10/6 (EF32) CORE SIZE PINS VERTICAL BOBBIN 6 Philips 3C85, Epcos N27 or equivalent CORE MATERIAL 1.4 mH ~0.13 mm PRIMARY PK TO PK VOLTAGE 500 Vpk MAXIMUM CORE TEMPERATURE 100 ºC PRIMARY INDUCTANCE AIR GAP LENGTH WINDING ISOLATION (Pri to Sec, Pri to Iso) 1000, 2000 WINDING START PIN FINISH PIN TURNS WIRE DIAMETER (mm) Primary 1 3 71 1 Strand of AWG 35 Secondary 2 6 11 1 Strand of AWG 30 Isolated 4 5 11 1 Strand of AWG 30 ELECTRICAL LAYOUT V PHYSICAL LAYOUT TOP VIEW 22mm 5.08mm 5.08mm 20mm TEST (TEST FREQUENCY = 50kHz) PRIMARY WINDING INDUCTANCE MIN 1.2 mH SECONDARY WINDING RESISTANCE MAX 0.1 Ohms www.irf.com AN-1169 MAX 1.6 mH 30 8. Output Current Regulation The IRPLLED5 LED driver produces a regulated constant current output at a nominal 1.4A. The current is regulated by adjusting the frequency of the halfbridge LLC resonant power stage. The maximum available output occurs at minimum frequency, which is programmed by R12 (also referred to as RFMIN). Figure 8 shows the relationship between this value and the frequency. The IRS2548D has a fixed dead time of approximately 1.8uS, which is long enough to accommodate the half-bridge voltage transition without allowing additional ringing oscillations to occur. The frequency is increased by sinking additional current from IC1 pin 2 (FMIN) through R10 and R11 and opto-isolator IC5. The half-bridge oscillates at maximum frequency when the transistor in IC5 is fully switched on and this frequency is programmed by the values of R10 and R11. Capacitors C9 and C35 have been added to remove noise transients since the FMIN input of the IRS2548D is very sensitive and this can cause frequency jittering resulting in flicker. It is also necessary for R10 and C9 to be located very close to IC1 with very short traces and a direct connection to the signal ground at the COM pin. IC5 is driven by the feedback circuitry at the isolated output. The output current is sensed through shunt resistor R37 and compared with a reference voltage of 0.275V set by R29 and R30. D12 provides a temperature stable accurate 5V reference voltage from which the current reference is derived. IC4 is an LM358 dual operational amplifier where one half is used for the current feedback error amplifier and the other half is used for over voltage protection. The outputs are OR’d together via diodes D10 and D11 to provide a current sink for the diode of IC5. The current feedback loop has a very slow response time. This is in order to avoid interference with the operation of the PFC front end stage whose error amplifier has a response time covering several AC line half cycles. As mentioned earlier, the IRS2548D contains circuitry to extend the PFC on time close to the AC line zero crossings to optimize THD, however this has negligible effect on the overall operation of the bus voltage regulation loop. Boost PFC front end stages produce ripple on the DC bus at twice the line frequency as a result of the slow control loop response. The back end stage current regulation loop must be slower than the PFC loop to prevent interference between the two loops that could introduce a sub-harmonic oscillation in the system and produce instability in the light output. If the current loop were to be made much faster than the PFC loop there would be distortion of the input current waveform since the effective load would be changing dynamically within the AC line cycle. The current control loop speed is determined by R36, R51 and C24. R36 remains at 1K to provide a low input impedance to the current error amplifier, which greatly reduces error caused by noise pickup. Since the half-bridge produces high dV/dT during switching, the system is liable to pick up noise at sensitive nodes and therefore each part of the circuit has been designed to minimize noise sensitivity. www.irf.com AN-1169 31 The output voltage is sensed through R35 and R34. If the output exceeds the safety low voltage limit of 60V, IC4 pin 2 exceeds 5V and the output at pin 1 is driven low. This causes the half-bridge frequency to be forced to maximum and also switches on opto isolator IC6 to pull up on the ENN pin and disable IC1. The PFC and half-bridge gate drives remain off until the output voltage drops to a low level because of the hysteresis provided by R32 and D9. This means that under an open circuit condition the output will operate in hiccup mode continuously pulsing to 60V and then decaying. This burst mode of operation provides minimum power consumption during an open circuit condition. 9. 0 to 10V Dimming Dimming is implemented using the PWM / burst mode operation controlled through the ENN input of IC1. A square wave signal is supplied to this input during dimming through opto isolator IC8. When this input exceeds the ENN input threshold the gate drive to the PFC and half-bridge MOSFETs are disabled. The compensation capacitor C6 at IC1 pin 3 is not discharged during this period and retains its voltage so that when switching starts up again the DC bus voltage can be regulated to the required level rapidly since C6 does not need to charge from zero to its previous level each time. This allows the DC bus voltage to remain quite stable even though the load is being pulsed on and off. This method of dimming allows stable control down to low levels. The output can be dimmed all the way to zero and back up again. The dimming control circuitry is referenced to the output so that it is isolated from the AC line input and can be safely connected to any 0-10V dimming control source. It has an internal pull up so that if no dimming input is connected the system defaults to maximum output. This is compatible with most current sinking 0-10V dimmer controls that are often powered from the ballast itself. A saw-tooth waveform varying from 0 to 10V is generated using current source Q1 in conjunction with C31. The frequency is around 150Hz (above the flicker limit of 120Hz) and can be adjusted via R45, however at higher frequencies the delay in IC8 could become significant. The saw-tooth waveform is compared with the 0-10V dimming control input to produce a rectangular waveform with a duty cycle that varies from 0 to 100% proportionally with the 0-10V dimming input. Dual comparator IC7 uses one comparator to create the saw-tooth oscillator and the other to compare this with the control input and produce the PWM output to IC8. It would be possible to replace this circuitry with a digital scheme such as a DALI interface based on a micro-controller to produce a similar PWM control input. www.irf.com AN-1169 32 10. Test Results Load: 2 x TT Electronics OPA731 connected in series VACin Pin PF THDi Fs Vout Iout Pout (Vrms) (W) (%) (kHz) (Vdc) (Adc) (W) 100 51.1 0.998 3.2 49.5 32.1 1.32 42.4 120 49.8 0.997 7.2 49.5 32.0 1.32 42.2 220 49.3 0.973 15.3 49.3 31.9 1.32 42.1 240 48.9 0.965 16.5 49.7 31.8 1.32 42.0 277 48.9 0.94 20.0 49.6 31.8 1.32 42.0 Eff (%) 82.9 84.8 85.4 85.8 85.8 Load: 2 x Eco Lumens EPAD connected in series VACin Pin PF THDi Fs Vout Iout (Vrms) (W) (%) (kHz) (Vdc) (Adc) 100 55.1 0.999 2.3 42.8 39.2 1.22 120 55.4 0.998 6.4 42.8 39.1 1.23 220 55.0 0.979 13.1 42.8 39.1 1.24 240 55.1 0.972 15.6 42.8 39.1 1.24 277 55.5 0.952 18.3 42.8 39.1 1.25 Eff (%) 86.8 86.8 88.2 88.0 88.1 Pout (W) 47.8 48.1 48.5 48.5 48.9 Short circuit current = 1.5A (at frequency 60.2kHz) Figure 21: Short Circuit Current www.irf.com AN-1169 33 Open circuit voltage = 54V Open circuit power consumption = 1.4W @ 120VAC and 1.6W @ 230VAC Figure 22: Open Circuit Operation Channel 1 (orange) shows the half bridge operating in burst mode during an open circuit condition which limits the output to below 60V while minimizing power consumption. Voltage vs Current 60 Voltage (V) 50 40 30 V-I 20 10 1. 6 1. 4 1. 2 1 0. 8 0. 6 0. 4 0. 2 0 0 Current (A) Figure 23: Output V-I Characteristic Figure 23 shows the output voltage to current characteristic of the converter. This indicates the constant current limiting operation. When tested with a resistive www.irf.com AN-1169 34 active load the voltage remains fairly flat over the range of current until the current reaches the regulation limit. For an LED load the voltage is clamped by the sum of the forward voltages of the series LEDs. Figure 24: Output Voltage and Current Figure 25: Output Voltage and Current Dimmed In figure 24, channel 2 (green) shows the output voltage driving an LED load and channel 9 (blue) shows the output current at an average of 1.3A. The current www.irf.com AN-1169 35 ripple is 200mApp which is approximately 15%. This has been accomplished without the addition of any electrolytic capacitors at the output. Figure 25 shows the output current and voltage during dimming operation. During the off phase of PWM / burst mode dimming the LED voltage drops rapidly as the output capacitors discharge to the voltage level where no more current flows through the LEDs because of the forward voltage drop. The current drops to zero during this phase and takes a finite time to recover during the on phase since the output capacitors need to be replenished and the current control loop is slow for reasons described earlier. The peak current drops linearly as the PWM duty cycle is reduced the result of which is an effective combined PWM / linear dimming operation allowing dimming to very low levels. Some audible noise can be heard during dimming operation since the power supply is being pulsed on and off at a frequency in the region of 150Hz. This would be greatly reduced by varnishing the inductors and placing the board inside an enclosure. It is also possible to increase the PWM dimming frequency although delays in the opto isolators would need to be considered. Figure 26: Half Bridge Switching Voltage Figure 26 shows the half bridge switching waveform operating in the soft switching region with the bus voltage at 469V. The DC bus voltage contains a component of ripple at 120Hz of approximately 15Vpp. The efficiency for the IRPLLED5 demo board measures between 85% and 90%. This will exceed 90% in higher power designs, however this demo board has been designed to operate at lower power in order to avoid the need for very large and expensive LED loads for test and evaluation. www.irf.com AN-1169 36 11. Bill of Materials Item Qty Manufacturer Part Number Description Reference 1 2 3 4 5 6 7 8 1 1 1 1 3 1 1 2 IR IR IR STM Toshiba STM Infineon Vishay LED Combo Controller, SO14 Flyback controller, SO8 Sync Rectifier Controller, SO8 Dual Opamp, SO8 Opto Isolator, DIP4 Dual Comparator MOSFET, 650V, TO220 MOSFET, 600V, TO220 IC1 IC2 IC3 IC4 IC5,IC6,IC8 IC7 M1 M2,M3 9 2 IR MOSFET, 100V, DPAK M4,M5 10 11 12 1 1 5 Infineon Diodes Inc Diodes Inc IRS2548DS IRS2500S IR11682 LM358DT TLP621(BL,T,F) LM393DT IPP60R250CP IRFBC30A IRFR24N15DTRLP BF SPA03N60C3 MMBT2907 US1J-13 MOSFET, 650V, TO220 Transistor, PNP, 60V, SOT23 Diode, 600V, 1A, SMA 13 8 Diodes Inc LL4148 Diode, 100V, 200mA, SOD80 14 15 16 17 18 19 20 1 1 1 1 1 1 1 Dialight Diodes Zetex Diodes Inc Diodes Inc Fairchild Murata Murata 521-9327F LM4040D50FTA ZMM5240B-7 BZT52C2V7-7-F DF10S CD1490C CD1491C 21 1 Panasonic ELF-15N007A 22 23 24 25 1 2 2 1 Murata TDK Delevan Delevan CD1488C NLCV25T-100K-PF 4590R-155K 4590R-224K LED, Green Voltage Reference, 5V Diode, Zener 10V Diode, Zener 2.7V Bridge, 1000v, 1.5A, 4SDIP Transformer, Resonant, 12mH Flyback Inductor, 1.4mH EMI Common Mode Line Filter, 250V Inductor, PFC, 0.95mH Inductor Inductor, 1.5mH, 460mA,Axial Inductor, 220uH, 2A, Axial M6 Q1 D1,D4,D5,D6,D7 D2,D3,D9,D10, D11,D14,D15,D16 D8 D12 D13 D17 BR1 T1 T2 26 10 Panasonic ERJ-8GEYJ104V Capacitor, 0.1µF, 50V, 1206 27 2 Panasonic ECQ-U2A224ML 28 1 Panasonic ECQ-U2A104BC1 29 2 Panasonic EEU-EB2E470S 30 1 TDK 31 3 Yageo C3216X7R1H684K CC1206KRX7R9BB 471 32 1 EPCOS 33 1 Vishay 34 35 36 37 38 39 40 2 4 1 1 1 1 1 TDK Panasonic AVX TDK TDK TDK Vishay www.irf.com B32652A7103J VY1332M59Y5UQ6 3V0 C4532X7R1E106M ECJ-3YB1E105K 12063C102MAT2A C3216X7R1E475K C3216C0G1E103J C3216C0G1E223J VJ1812Y104KXEAT Capacitor, 220nF,275VAC,X2,TH,.6” Capacitor, 100nF, 275V, TH,O.6” Capacitor, 47uF, 250V,TH.RAD,0.3” Capacitor, 680nF, 50V, 1206 Capacitor, 470pF, 50V, 1206 Capacitor, 10nF, 1.25KV, Polypro, 0.6” Capacitor, 3.3nF, 500VAC, 0.3” disk Capacitor, 10uF, 50V, 1812 Capacitor, 1uF, 25V, X7R, 1206 Capacitor, 1nF, 25V, 1206 Capacitor, 4.7uF, 25V, 1206 Capacitor, 10nF, 25V, 1206 Capacitor, 22nF, 25V, 1206 Capacitor, 100nF, 500V, 1812 AN-1169 L1 L2 L3,L4 L5,L7 L6 C5,C9,C12,C19,C20 ,C23,C26,C30,C33, C35 C1,C11 C2 C3,C4 C6 C7,C8,C10 C22 C13 C27,C28 C17,C25,C29,C31 C38 C24 C36 C32 C14 37 Vitramon GRM31BR73A102K W01L EEU-FC1H470 C1216X5R1E106M EEU-EB1H100S C3216C0G1E333J LTR18EZPJ101 ERJ-8GEYJ824V ERJ-8GEYJ153V PR01000101008JR 500 41 1 Murata 42 43 44 45 46 47 48 2 2 1 1 1 2 1 Panasonic TDK Panasonic TDK Rohm Semi Panasonic Panasonic 49 1 Vishay 50 6 Panasonic ERJ-P08J102V Resistor, 1K, 5%, 1206 51 52 53 54 2 2 4 2 Panasonic Panasonic Panasonic Panasonic Resistor, 15K, 5%, 1206 Resistor, 15R, 5%, 1206 Resistor, 47K, 5%, 1206 Resistor, 43K, 5%, 1206 55 1 Vishay / BC Resistor, 0.5R, 1W, TH 0.5” R13 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 4 1 1 1 2 1 1 4 1 1 1 1 3 1 1 Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ERJ-8GEYJ153V ERJ-8GEYJ150V ERJ-8GEYJ473V ERJ-8GEYJ433V PAC100005007FA1 000 ERJ-8GEYJ100V ERJ-P08J223V ERJ-P08J330V ERJ-P08J123V ERJ-P08J472V ERG-8ENF1432V ERJ-8GEYJ333V ERJ-8GEYJ334V ERJ-P08J222V ERJ-8GEYJ152V ERJ-1TRQJR22U ERJ-P08J183V ERJ-8GEYJ103V ERJ-P08J391V ERJ-8GEYJ222V R6,R14,R24,R30,R3 6,R60 R7,R35 R8, R9 R10,R11,R12,R41 R44,R61 Resistor, 10R, 5%, 1206 Resistor, 22K, 5%, 1206 Resistor, 33R, 5%, 1206 Resistor, 12K, 5%, 1206 Resistor, 4.7K, 5%, 1206 Resistor, 14.3K, 1%, 1206 Resistor, 33K, 5%, 1206 Resistor, 330K, 5%, 1206 Resistor, 2.2K, 5%, 1206 Resistor, 1.5K, 5%, 1206 Resistor, 0.22Ohm, 1W, 2512 Resistor, 18K, 5%, 1206 Resistor, 10K, 5%, 1206 Resistor, 390R, 5%, 1206 Resistor, 2.2K, 5%, 1206 71 5 Panasonic ERJ-8GEYJ104V Resistor, 100K, 5%, 1206 72 73 74 1 1 1 Panasonic Panasonic Panasonic Resistor, 6.8K, 5%, 1206 Resistor, 39K, 5%, 1206 Resistor, 100K, 1W, 2512 R15,R38,R39,R58 R16 R25 R27 R28,R48 R29 R31 R32,R52,R53,R54 R33 R34 R37 R40 R42,R43,R62 R45 R46 R47,R55,R56,R57,R 63 R50 R51 R26 Resistor, 100K, 5%, 1W, 2512 R26 (alternate) Resistor, 2.2Ohm, 5%, 1206 Varistor, 320VAC, 10mm Diameter Fuse, 2A, Fast, 250V Connector, 5 Way, Light Gray Connector, 2 Way, Light Gray NF NF NF R59 76 1 Panasonic ERJ-8GEYJ682V ERJ-8GEYJ393V ERJ-1TYJ104U CRCW2512100KJN EG ERJ-8GEYJ2R2V 77 1 Panasonic ERZ-V10D511 78 79 80 81 82 83 1 1 1 1 1 1 Littelfuse Wago Wago 0263002.MXL 235-205 235-202 75 Vishay www.irf.com Capacitor, 1nF, 1kV, 1206 C16 Capacitor, 47uF, 50V, Radial Capacitor, 10uF, 25V, 1206 Capacitor, 10uF, 50V, Radial Capacitor, 33nF, 25V, 1206 Resistor, 100R, 5%, 1206 Resistor, 820K, 5%, 1206 Resistor, 15K, 5%, 1206 C18,C21 C15,C34 C41 C40 R1 R2, R3 R4 Resistor, 1R, 1W, TH 0.5” R5 AN-1169 VDR1 F1 P1 P2 R49 C39 C37 38 12. PCB Layout Top Overlay www.irf.com Top Metal AN-1169 39 Bottom Overlay www.irf.com Bottom Metal AN-1169 40 References: IRS2548DS Datasheet (International Rectifier) IRS2500S Datasheet (International Rectifier) AN-1160 Helen Ding (International Rectifier) IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 05/09/2014 www.irf.com AN-1169 41