Characterization of Cdv/dt Induced Power Loss in Synchronous Buck DC-DC Converters Qun Zhao and Goran Stojcic International Rectifier As Presented at APEC 2004 Abstract — Good understanding of power loss in a high frequency synchronous buck converter is important for design optimization of both power MOSFET and circuit itself. Most of the MOSFET power losses are relatively easy to quantify. The exception is the power loss associated with Cdv/dt induced turn on of the low-side MOSFET (synchronous rectifier). This paper characterizes the Cdv/dt induced power loss in two ways. First, detailed device characterization, in-circuit testing, and modeling are used for a comparative loss calculation. This method requires specialized test equipment and is rather complicated and time consuming. A simple method is then introduced to very accurately quantify the Cdv/dt loss. With this method, the impacts of the Cdv/dt power loss on synchronous buck converters at different operation conditions can be readily assessed. The impacts of Cdv/dt induced turn on different applications are addressed. pacitances, internal gate resistance, threshold voltage, body diode properties, and package characteristics) , driver capability, layout, etc. In this paper, a comparison study is conducted first to quantify the Cdv/dt induced power loss based on detailed device characterization, loss modeling, and in-circuit testing. A simple and practical method is then introduced to experimentally quantify the Cdv/dt induced turn on loss. The results show that the Cdv/dt loss could be significant - depending on switching frequency, input voltage, and load conditions. The results also point out certain benefits of Cdv/dt induced turn on - the reduction of sync FET Vds ringing induced by the body diode reverse recovery and loop parasitic inductance. MOSFET packaging inductance and body diode reverse recovery have to be minimized in order to allow optimally designed silicon (with high Cdv/dt immunity) to maximize circuit efficiency without generating excessive parasitic ringing. Index Terms — Synchronous rectifier, switching loss. I. INTRODUCTION The stringent requirements for low voltage, high current voltage regulators (VRs) impose various challenges to the power management design . High conversion efficiency is one of the most critical issues in order to improve power density . Careful MOSFET and driver optimization as well as layout are the key factors to achieve high conversion efficiency. Synchronous buck converter is the most popular topology for today’s VRs. In this converter, the freewheeling Schottky diode of the regular buck converter is replaced with a power MOSFET. This results in tremendous conduction loss reduction, but also creates new challenges and device requirements. One of the issues frequently discussed but not fully understood or characterized is so-called Cdv/dt induced switching loss of MOSFETs used as synchronous rectifiers (referred to in this paper as sync FETs) . Cdv/dt induced turn on of the sync FET can happen after its body diode recovers; the increased voltage across the sync FET induces a voltage on the gate through the drain-to-source capacitor, Cgd. The induced voltage can possibly turn on the sync FET for a short time. The overlapping of the Vds voltage and the current generates additional switching loss. The issues of Cdv/dt induced turn on are not well understood because of the complexity resulting from the involvement of the Vds slope (which is also determined by many factors) and various MOSFET characteristics (such as interelectrode cawww.irf.com II. METHODOLOGY OF THE STUDY Analytical calculation of the Cdv/dt induced power loss is not very practical, since many of the involved parameters cannot be easily extracted or accurately modeled. An alternative approach is to compare two sync FETs with similar parameters – except those that dominate the Cdv/dt induced turn on. The sync FET No.1 (Case 1) turns off without Cdv/dt induced turn on. For the sync FET No.2, (Case 2), the Cdv/dt induced gate-source voltage is high enough to turn the channel on, and introduce additional switching losses. The Cdv/dt induced turn-on loss is then quantified by the comparing the losses between the two cases. This method, described in Section V, can be quite accurate, however, it requires complete sync FET device characterization (obtained with special testers), detailed incircuit waveforms, as well as measurements of the in-circuit efficiency and device operating temperature. It is therefore very time consuming and in general not practical for most design engineers. A more practical engineering approach that does not need any device characterization is described in Section VI. The idea is to modify the gate drive circuit so that an adjustable negative gate-source offset voltage can be generated. 1 The purpose of the negative offset voltage is to shift the induced gate voltage below the gate threshold voltage, By applying a sufficient negative offset, the Cdv/dt induced turn on loss can be completely eliminated. III. SYNC FET TURN-OFF LOSSES WITHOUT CDV/DT INDUCED TURN-ON Fig. 1 shows a synchronous buck converter with control FET denoted as Q1, and sync FET denoted as Q2. In this figure, Q2 is shown with its body diode, three parasitic capacitors (drain-gate capacitor Cgd, gate-source capacitor Cgs, and drain-source capacitor Cds) and an internal gate resistor Rg_in. The inductance of the current transition loop (comprised of input cap ESL, PCB parasitic inductance, and package capacitance of Q1 and Q2) is lumped as Lkloop. Lkloop [T5 – T6]: The current through Q1 is equal to the inductor current at t5, and Q2 current is zero. Starting from t5, reverse recovery current flows through Q2’s body diode. At t6 the reverse recovery current reaches its peak value Irrm, and the body diode recovers. The energy stored in the loop parasitic inductor, Lkloop, at time t6 is: 1 2 Eloop = ⋅ Lk loop ⋅ I rrm 2 [T6 – T8]: The recovered body diode starts to block the voltage at t6. The Vds-Q2 rises with a very high dv/dt slope. This voltage rise is capacitively coupled into the gate thru the gate-drain capacitor, Cgd, resulting in an induced voltage at the gate of the sync FET. However, this voltage for Case 1 is lower than the threshold voltage, and therefore insufficient to turn on the Q2. Driver delay VGS_Q1 Q1 Eq. 1 t L Gate Driver Cgd Rg_ext Rg_in Cds TP VGS_Q2 IL t Co Cgs VDS_Q2 Q2 Fig. 1. A synchronous buck converter with a simplified model of the FET Q2. Key switching waveforms for the Case 1 (the sync FET has high Cdv/dt immunity and the induced gate voltage is not high enough to turn on the sync FET), are given in Fig. 2. The turn-off transition of the sync FET can be briefly described as follows: [T0 – T2]: At t0, the sync FET gate turns off and the Vgs decays exponentially determined by Ciss and total gate impedance. As the gate voltage of Q2 falls below its threshold voltage at t2, all the Q2 channel current is diverted back into its body diode. [T3 – T5]: After a predetermined driver delay, the top switch Q1 begins to turn on (at t3). The gate voltage on Q1 quickly reaches and exceeds the threshold voltage, Vth-Q1, commencing the current transition. Because of high di/dt and the package leakage inductance, the Vds voltage of Q2 increases slightly from about –0.7V negative to some small positive voltage. Vin Vf t ID_Q2 (body diode) t7 t0 t1 t2 t t3 t5 t 4 t6 t8 Fig. 2. Key waveforms during the transition of the current from Q2 to Q1 without Cdv/dt induced turn on. The loop parasitic inductor now forms a resonant circuit with Q2’s output capacitor Coss, resulting in Vds oscillations. Approximately all of the leakage energy is transferred to the output capacitor of Q2 in the initial resonant cycle. The resonance is then damped over many cycles by the high frequency AC resistance in the Cin-Q1-Q2 loop, resulting in the final Vds voltage being equal to Vin. The remaining Coss energy at Vin is recycled at the next cycle (since the turn-on of the sync FET is with zero Vds voltage). Therefore, the energy dissipated at Q2 turn off can be expressed as: 1 Poff _ Coss _ case1 = (Qoss (Vpk ) ⋅ V pk − Qoss(Vin) ⋅ Vin ) ⋅ f s 2 Eq. 2 For standard MOSFET packages, such as SO8 and D-Pak, parasitic package inductance is the key component of the loop inductance. When silicon die with good Cdv/dt immunity is used in these packages, the Vds ringing caused by the inductance and body diode reverse recovery current can easily exceed 30V with 12V input voltage. High peak voltage as well as ringing can result in excessive EMI and can reduce controller/driver reliability. It was shown in  that by replacing a SO8 package with a package with much lower ® inductance (such as DirectFET ), the switch node voltage ringing can be reduced by as much as 50%. IV. SYNC FET OPERATION AND LOSSES WITH CDV/DT INDUCED TURN ON For Case 2, the Cdv/dt induced gate-source voltage is high enough to turn on the sync FET. Once the sync FET is turned on, the dv/dt is reduced. This prevent further gate voltage rise. Consequentially, the value of the induced gate voltage is whatever is required to support the peak reverse recovery current Irrm. (Note that due to internal Rg_in, the gate-source voltage measured at the gate terminal of a sync FET is different from the internal voltage across individual cells). Fig. 3 shows the key waveforms of the converter during this mode of operation. The circuit operation and losses are significantly different for this case. The Vds-Q2 will be either clamped (as shown in Fig. 3) or will have reduced dv/dt increase rate. For this study we consider clamped Vds case. Driver delay VGS_Q1 t Case 2 VGS_Q2 VDS_Q2 Case 1 Case 2 Vin Vf t 7’ ID_Q2 (body diode) t7 t0 t1 t2 t3 t5 t 4 t 6 t8 t tcl= t8- t7’ Case 1 Case 2 Fig. 3. Key waveforms during the transition of the current from Q2 to Q1 with Cdv/dt induced turn on. Up to time instance t6, the circuit operation is the same regardless of Cdv/dt immunity of the sync FET. After T6, the operation is as follows: [T6 – T7’]: The Q2 body diode recovers and starts to block the voltage at t6. The voltage change dv/dt of Vds-Q2 is coupled to the gate via gate-drain capacitor, and an induced gate voltage is now higher than the threshold voltage. [T7’ – T8]: At time t7’, the Cdv/dt induced turn on happens and the voltage Vds-Q2 is clamped. The FET turns off at time t8. The duration of this clamped time period is tcl (t8-t7’). Multiple factors determine the Cdv/dt immunity. These include the slope of the Vds, internal gate resistance, threshold voltage, body diode properties, package characteristics, driver capability , and layout, etc. However, one of the key factors for well-designed circuit with typical driver resistance and FET gate resistance is the gate charge ratio (CR) . CR is defined as: CR = Q gd / Q gs1 , Eq. 3 where Qgd is the gate-drain (Miller) charge at a specified Vds voltage, and Qgs1 is pre-threshold gate-source charge. During Cdv/dt induced turn on, the Vds of Q2 is clamped due to the channel conduction. With the assumption that the clamped voltage is constant (also observed in experimental test), the induced switching loss during the Q2’s clamping time for Case 2 can be expressed as: Poff _ Clamp _ case 2 ≈ Vcl ⋅ I rr m 2 ⋅ t cl ⋅ f s , Eq. 4 where Vcl is the value of the clamped Vds voltage; fs is the switching frequency; Irrm is the peak reverse recovery current; and tcl is the time for the reverse recovery current to reduce from Irrm to zero. Vcl and tcl are most accurately determined from the circuit waveforms, while Irrm needs to be determined with a special tester (it is not possible to measure Irrm inside the circuit because insertion of a current sense element would significantly alter circuit operation). Note that Eq. 4 is most accurate when Vcl is up to about 2Vin. If a device measures higher Vcl (better Cdv/dt immunity), the reverse recovery current that needs to be entered in the Eq. 4 will be lower than Irrm. This is due to Lkloop – Coss resonance, which reduces reverse recovery current toward zero as the Vds increase toward its peak oscillation value. Aside form Cdv/dt turn on loss, there is still power loss associated with Coss high frequency resonance, given by Eq. 5 below. However, due to the clamping action, the peak Vds voltage will be reduced, and there will be less energy transferred into Coss. Consequently the power dissipated in the Cin-Q1-Q2 loop will be lower than that using the device with better Cdv/dt immunity. 1 Poff _ Coss _ case2 = (Qoss (Vcl ) ⋅Vcl − Qoss(Vin) ⋅Vin ) ⋅ f s 2 Eq. 5 Total turn off power loss for the sync FET with Cdv/dt induced turn on is the sum of Eq. 4 and Eq. 5 Poff _ case 2 ≈ Poff _ Clamp _ case 2 +Poff _ Coss _ case 2 40 35 Eq. 6 PCdv / dt _ case 2 ≈ Poff _ case 2 −Poff _ Coss _ case1 Qoss (nC) The Cdv/dt induced turn-on causes sync FET to dissipate an additional energy from the source, higher than the loop leakage energy given by Eq. 1. If other parameters can be excluded from affecting the loss difference, then the Cdv/dt induced loss can be expressed as: Device No.2 (Low RDS-on, High CR) 30 25 Device No.1 (High RDS-on, Low CR) 20 15 10 Eq. 7 5 0 0 V. QUANTIFICATION OF CDV/DT LOSS BASED ON THE ANALYSIS METHOD 4.0 Loss (W) 4.83 Qgs1 (nC) 8.81 10.85 1.5 Ggd (nC) 8.59 16.37 1.0 Rg (Ω) 1.4 1.4 Qrr (nC) @10A 62.85 74.88 2.0 Device No.1 (High RDS-on, Low CR) Vin=14V, Vo=1.3V 0.5 2 4 Io(A) 6 8 10 Fig. 5. Loss comparison between two sync fets processed in different ways (one with low CR, and one with high CR). Table 1. The comparison of device parameters. 9 40 8 35 Case 1 7 Case 2 6 Vgs [V] The measured Qoss vs. the drain-source voltage of the two devices is shown in Fig. 4. Fig. 5 shows the performance comparison for the two devices in the sync FET socket using the same Q1 (10mΩ, lowcharge device) in 1MHz, 14Vin , 1.3V sync buck circuit. The loss difference at 10A is about 0.72W. This loss difference is due to the different Rds_on, Coss and CR of the two devices. To find the exact Cdv/dt induced loss, in-circuit switching waveforms, device temperature and reverse recovery peak current are also necessary. Fig. 6 compares Vds and Vgs waveforms for the sync FETs. Case 1 does not have the Cdv/dt induced turn on (the peak Vds voltage is 35V), while a 23V clamped drain-to-source voltage can be observed for the case 2. The clamping time can be found as 7ns. 2.5 30 25 5 20 4 15 3 10 2 5 1 0 0 -5 -1 Vds [V] 2.08 Device No.2 (Low RDS-on, High CR) 3.0 5.38 2.02 0.72W 3.5 RDS_on (mΩ) @ 25oC Vth (V) 40 4.5 Device No.2 1.51 30 Fig. 4. Measured output charge of the two devices at different drain-source voltage. Device No. 1 0.98 20 Vds (V) A typical 5mΩ sync FET power MOSFET in SO8 package was processed in two different ways for the purpose of Cdv/dt power loss calculation. With varying trench channel depth, it was possible to find one device with higher RDS-on and lower CR (better Cdv/dt immunity), and the other one with much higher CR and lower RDS-on. Most of the other relevant parameters were the same or very similar. The relevant device parameters are shown in Table 1. CR (Qgd / Qgs1) 10 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Time [nS] Fig. 6. Waveform comparison for loss quantification between two sync fets (one with low CR, and one with high CR). Table 2 summarizes the calculated power loss based on the device information and in-circuit waveforms. It can be seen that the calculated loss using a device with high CR (poor Cdv/dt immunity) at 10A output current is 0.70W higher than the loss using a low CR device. This value matches the measured 0.72W very well. The Cdv/dt inducted loss for this circuit and under given operating conditions can be calculated as 0.75W. Since all device parameters are very similar, this loss difference can be attributed to high CR and Cdv/dt induced switching losses. At 10A, 1MHz operation condition, the Cdv/dt induced loss for the device No. 2 is 18% of the total circuit loss, which is very significant. RDS_on (mΩ) @ Temp PCond (W) Vpk/Vcl (V) Qoss (nC) @ (Vpk/Vcl) Qoss (nC) @ (Vin) Poff_Coss (W) Irr (A) @10A Tcl (ns) @10A Poff_Clamp (W) ∆ Loss (W) Cdv/dt Loss (W) Device No. 1 Device No.2 6.73 6.28 0.76 0.71 35 23 33 (@ 35V) 32 (@23V) 20 22 0.46 0.24 12.0 12.0 7 0.97 (Eq. 4) 0.70W 0.75W (Eq. 7) Fig. 8 shows the loss measurement (excluding control power, the PCB and inductor loss), obtained in a 12Vin, 1.7Vout, 1MHz, 20A VR module using single control FET and a single sync FET. The on-state Vgs was kept constant at 5V, in order to keep the RDS-on (and conduction loses) constant. The off-state gate drive was varied from zero to –2V. In this way, all the measured power loss difference can be associated with Cdv/dt loss. VDriver Q1 Gate Driver Rs SSYNC Q2 VDriver It was shown in the previous section that the Cdv/dt issues relate to many factors such as the voltage rising slope, charge ratio, tradeoffs between Qgd and Rds(on), threshold voltage, and total gate impedance. Furthermore, extracting some of the device parameters required for Cdv/dt power loss characterization requires specialized test equipment, typically not available to most circuit designers. Therefore, this process can be both time-consuming and costly. A faster, more practical way for a designer to quantify Cdv/dt induced power loss is to use simple circuit shown in Fig. 7. The purpose of this circuit is to create a negative gate drive voltage (rather than zero) during the turn-off time of the sync FET. This negative voltage will prevent sync FET from turning on due to Cdv/dt effect. The purpose of Cs is to change the standard gate drive signal coming from a driver IC into an AC signal with positive and negative values proportional to the duty cycle. The purpose of the V+ is to offset the new gate drive signal and allow negative gate bias to be varied in order to identify Cdv/dt induced power loss, and/or find optimum negative gate drive. Negative Bias (Controlled by +V) Fig. 7. Modified driver circuit to generate negative voltage. It can be seen from Fig. 8 that the loss can be reduced by 0.57W with –1V bias and by 0.84W with up –2V negative bias. The loss remains constant as the negative gate bias is further increased, indicating that all Cdv/dt induced power loss have been eliminated. 5.0 4.5 4.0 Loss (W) INDUCED POWER LOSS Cs V+ 0 Table 2. Calculation of Cdv/dt induced power loss. VI. PRACTICAL WAY TO QUANTIFY CDV/DT +V 3.5 3.0 2.5 2.0 -3.0 Vin=12V, Vo=1.7V, Io=20A, Fs=1MHz -2.0 -1.0 Negative bias (V) Fig. 8. Loss measurement with a fixed V+=5V and variable negative bias. 0.0 VII. IMPACTS OF CDV/DT INDUCED LOSS ON THE DEVICE AND CIRCUIT DESIGN As a switching loss, the Cdv/dt induced loss is proportional to the switching frequency. It has been demonstrated that the Cdv/dt loss could be a significant part of the total circuit loss at 1MHz. The Cdv/dt induced loss imposes challenges on both device and circuit design for high frequency VRs, which is a future direction of VR’s. At prevailing 200-500KHz operating frequency, Cdv/dt induced loss could also be a serious problem depending on the applications. Three devices with the parameters shown in Table 3 are used as the sync FET for the comparison in notebook applications. The major difference of the three devices is the Miller charge, therefore, the CR. Device No.1 with CR=1 outperforms the part with CR=1.4. The efficiency improvement is about 5% at 4A, around where device would be running most of the time in typical notebook application. For the three evaluated devices, Qgs1 varies only 5%, while Qgd varies by over 45%. Qgd is a key factor for achieving optimized device design. The conduction loss reduction due to the Rds-on reduction is very small and does not offset the increased Cdv/dt loss. As discussed and demonstrated in Sessions III to V, the Cdv/dt induced turn on can help to reduce the voltage spike of the sync FET. Aside from EMI reduction, the spike reduction makes it easier to use more efficient 20VN devices for 12Vin processor power applications for desktop and servers. VIII. CONCLUSION Device No. 1 Device No.2 Device No.3 RDS_on (mΩ) @ 25oC 3.6 3.5 3.3 Vth(V) 1.7 1.8 1.8 CR 1.0 1.2 1.4 Qgd (nC) 10.9 13.6 15.9 Eff (%) @ 4A 85.94 83.88 81.00 Table 3. The comparison of device parameters and the efficiency at light load. The converter input voltage is 19V and the output voltage is 1.3V. Fig. 9 shows the measured efficiency. 88 References:  Intel, “VRM 9.0 DC-DC converter design guidelines,” Jan. 2002 86 Efficiency (%) This paper presents detailed characterization of the power loss associated with Cdv/dt induced turn on of a MOSFET used as synchronous rectifier in high frequency synchronous buck converters. A simple and effective method is also introduced that allows engineers to accurately quantify Cdv/dt loss. On one hand, the Cdv/dt induced turn on can introduce quite significant loss depending on switching frequency, input voltage, and load conditions; on the other hand, the Cdv/dt induced turn on can reduce the voltage stress of the sync FET. The Cdv/dt induced switching loss imposes challenges on device and circuit design not only for high frequency VRs, but also for the applications running at light load conditions most of the time, such as notebook applications.  P. Xu, “Multiphase voltage regulator modules with magnetic integration to power microprocessors, ” Dissertation, Virginia polytechnic Institute and state university, January 2002. #1 84  T. Wu, “Cdv/dt induced turn-on in synchronous buck regulations,” report on International Rectifier website (www.irf.com). #2 82  Kaiwei Yao, F. C. Lee, “A novel resonant gate driver for high frequency synchronous buck converters”, IEEE Trans. Power Electron., Mar. 2002, Vol. 17, No. 2, pp. 180-186. #3 80  P. Markowski, “Estimation MOSFET switching losses means higher performance buck converter,” report on planet analog website (www.planetanalog.com). Vin=19V; Vo=1.3V; FS=300KHz 78 3 6 Io(A) 9 Fig. 9. Impact of Cdv/dt induced loss on notebook applications. 12  L. Spaziani, “A study of MOSFET performance in processor targeted buck and synchronous rectifier buck converters,” in HFPC Power Conversion Proc., 1996, pp.123-137.  M. Pavier, A Sawle, A Woodworth, R Monteiro, J. Chiu, C. Blake, “ High frequency DC: DC power conversion: the influence of package parasitics,” in APEC’03 Proc., pp.699-704.