IRDC3838 SupIRBuck TM USER GUIDE FOR IR3838 EVALUATION BOARD DESCRIPTION The IR3838 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3838 a space-efficient solution, providing accurate power delivery for low output voltage applications. IR3838 is a versatile regulator which offers programmability of switching frequency and current limit while operates in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. Key features includes: Internal LDO, Pre-Bias startup, protection functions, such as hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. This user guide contains the schematic and bill of materials for the IR3838 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3838 is available in the IR3838 data sheet. BOARD FEATURES • Vin = +12V • Vout = +1.8V @ 0 – 10A • Fs = 600kHz • L = 0.6uH • Cin= 4x10uF (ceramic 1206) + 1x330uF (electrolytic) • Cout=5x47uF (ceramic 0805) 1 IRDC3838 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 10A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IR3838 has only one input supply, the input voltage (Vin). Internal LDO circuitry generates Vcc voltage (=5.2V). One option for using a separate +5V supply for Vcc voltage, as required in a certain application, is to remove R15 (zero Ohm resistor), which disables the internal LDO circuit. In this case Vcc input should be a well regulated 4.5V-7.5V supply and it would be connected to Vcc+ and Vcc-. Table I. Connections Connection Signal Name VIN+ Vin (+12V) VIN- Ground of Vin VOUT+ Vout (+1.8V) VOUT- Ground of Vout Vref Internal Reference-Voltage SEQ Sequence input Vcc+ VCC/LDO_out pin Vcc- Connected to PGND Sync Synchronous input LAYOUT The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3838 and other components are mounted on the top and bottom side of the board. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3838. The feedback resistors are connected to the output voltage at the point of regulation and are located close to IR3838. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 2 IRDC3838 Connection Diagram Vin GROUND Enable Vref GROUND SEQ VOUT Vcc/LDO_out PGood SYNC Fig. 1: Connection diagram of IR3838 evaluation board (top and bottom) 3 IRDC3838 Fig. 2: Board layout, top layer Fig. 3: Board layout, bottom layer 4 IRDC3838 Single point connection between AGND and PGND. Fig. 4: Board layout, mid-layer I Fig. 5: Board layout, mid-layer II 5 Fig.8: Schematic of the IR3838 evaluation board IRDC3838 6 IRDC3838 Bill of Materials Item NumQuantity 1 1 2 4 3 5 4 1 5 1 6 1 7 1 8 1 9 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 16 1 4 1 1 1 1 1 1 1 1 1 1 3 1 Part Reference C1 C3 C4 C5 C6 C7 C10 C12 C14 C24 C8 C11 C23 C26 C32 C15 C16 C33 C35 C36 C2 C9 C17 C18 C19 C20 C27 C28 C29 C30 C31 C34 C37 C38 C39 C40 L1 R10 R15 R16 R29 R1 R2 R3 R4 R6 R9 R12 R17 R18 R19 R14 R21 R28 U1 Value 330uF/25V 10uF 0.1uF 2200pF 150pF 2.2uF 5.6nF 1.0uF 47uF Description SMD Elecrolytic, Fsize, 25V, 20% Ceramic,16V,1206,X7R,20% 0603-50V-X7R-10% Ceramic,50V,0603,C0G,5% Ceramic,50V,0603,NP0 Ceramic, 16V, 0603, X5R, 20% Ceramic,25V,0603,C0G,5% Ceramic,25V,0603,X5R,10% CAP, Ceramic, 6.3V X5R 0805 N/S 0.6uH 0 3.32K 4.02K 2K 127 20 23.7K 5.9K 10K 49.9K 7.5K N/S IR3838 No Stuff SMT-Inductor,1.5mOhms,11.5x10x4mm Thick-film,0603,1/10W,5% Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,5% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% No Stuff IR3838 PQFN Manufacturer Panasonic Panasonic - ECG Panasonic TDK Corporation Kemet AVX Corporation TDK Corporation Murata Electronics Taiyo Yuden Manufacturer Part Number EEE-FK1E331P ECJ-3YX1C106K ECJ-1VB1H104K C1608C0G1H222J C0603C151J5GACTU 0603YD225MAT2A C1608C0G1E562J GRM188R61E105KA12D JMK212BJ476MG-T Delta Vishay/Dale Rohm Rohm Rohm Rohm Vishay/Dale Rohm Rohm Rohm Rohm Rohm MPL104-0R6 CRCW06030000Z0EA MCR03EZPFX3321 MCR03EZPFX4021 MCR03EZPFX2001 MCR03EZPFX1270 CRCW060320R0FKEA MCR03EZPFX2372 MCR03EZPFX5901 MCR03EZPFX1002 MCR03EZPFX4992 MCR03EZPFX7501 IR IR3838MPbF 7 IRDC3838 TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO=5.2V, Vo=1.8V, Io=0-10A, Room Temperature, No Air Flow Fig. 9: Start up at 10A Load (Note 1) Ch1:Vout Ch2:PGood Ch3:EN Ch4: Vin Fig. 11: Start up with 1.62V Prebias, 0A Load, Ch1:Vout Ch2: PGood Ch3: EN Fig. 13: Inductor node at 10A load Ch3:SW Fig. 10: Start up at 10A Load (Note 1) Ch1:Vout Ch2:PGood Ch3:Vcc Ch4: Vin Fig. 12: Output Voltage Ripple, 10A load (Note2) Ch1: Vout Fig. 14: Short (Hiccup) Recovery Ch1:Vout, Ch2:PGood , Ch4:Iout 8 IRDC3838 TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO=5.2V, Vo=1.8V, Room Temperature, No Air Flow Fig. 15: Transient Response 1A-4A load (0.5A/us) Ch1:Vout, Ch4:Io Note1: Enable is tied to Vin via a resistor divider and triggered when Vin is exceeding above 10.2V. Note2: Vo ripple signal is taken across C17 cap. 9 IRDC3838 TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO=5.2V, Vo=1.8V, Io=0-10A, Room Temperature, No Air Flow Fig.16: Bode Plot at 10A load shows a bandwidth of 94kHz and phase margin of 51 degrees 10 IRDC3838 TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc/LDO=5.2V, Vo=1.8V, Io=0-10A, Room Temperature, No Air Flow 92 90 88 Efficiency [%] 86 84 82 80 78 76 74 72 70 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 6.5 7.5 8.5 9.5 10.5 Io [A] 2.4 2.1 PLoss [W] 1.8 1.5 1.2 0.9 0.6 0.3 0.5 1.5 2.5 3.5 4.5 5.5 Io [A] Fig.17: Efficiency and power loss vs. load current 11 IRDC3838 THERMAL IMAGES Vin=12V, Vcc/LDO=5.2V, Vo=1.8V, Io=10A, Room Temperature, No Air Flow Fig.18: Thermal Image at 10A load Test Point 1: IR3838, Test Point 2: Inductor 12 IRDC3838 PCB Metal and Components Placement The lead lands (the 13 IC pins) width should be equal to the nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. The pad lands (the 4 big pads other than the 13 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper. IRDC3838 Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. IRDC3838 Stencil Design • • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. IRDC3838 DIM A A1 b b1 c D E e e1 e2 MILIMITERS MIN MAX 0.800 1.000 0.000 0.050 0.375 0.475 0.250 0.350 0.203 REF. 5.000 BASIC 6.000 BASIC 1.033 BASIC 0.650 BASIC 0.852 BASIC INCHES MIN MAX 0.0315 0.0394 0.0000 0.0020 0.1477 0.1871 0.0098 0.1379 0.008 REF. 1.969 BASIC 2.362 BASIC 0.0407 BASIC 0.0256 BASIC 0.0335 BASIC DIM L M N O P Q R S t1, t2, t3 t4 t5 MILIMITERS MIN MAX 0.350 0.450 2.441 2.541 0.703 0.803 2.079 2.179 3.242 3.342 1.265 1.365 2.644 2.744 1.500 1.600 0.401 BASIC 1.153 BASIC 0.727 BASIC INCHES MIN MAX 0.0138 0.0177 0.0961 0.1000 0.0277 0.0316 0.0819 0.0858 0.1276 0.1316 0.0498 0.0537 0.1041 0.1080 0.0591 0.0630 0.016 BACIS 0.045 BASIC 0.0286 BASIC IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 03/10