LS2085A Layerscape Power Rail Diagram by International Rectifier

12V
Multi-phase Controller CORE & PLATFORM 1.0V ±3% / 120A (VDD=1V0)
& PowIRStage®
VID read FUSESR (via I2C) for optimum Vcore for setting
IR3565B
I2C BUS
+IR3550 (4 phase)
+ IR3550 (2 phase)
PMBus
I2C
VID: Core Voltage Setting
DDR: Voltage Setting
Telemetry: Vin, Vout, Iout, Temp
Control: Tuning / Validation
Fault Programming & Ops
Inventory
Remote Configuration
5V
International Rectifier is a
Proven Power Partner of Freescale
KEY CORE, PLATFORM, SERDES RAILS
POL Regulators
PMBus SupIRBuck®
IR38063
POL Regulators
SupIRBuck®
IR3897
POL Regulators
SupIRBuck®
IR3897
POL Regulators
SupIRBuck®
IR3897
GVDD 1.2V / 40A (G1,2,3VDD=1V2 DDR)
GVDD uDIMM’s DDR#1,2,3
OVDD 1.8V / 25A
LS2: OVDD, TH_VDD } GEN I / O & AVDD_CGx, PLAT, D1-D
and General Purpose 1.8V rail
Freescale
Layerscape 2
LS2085A
64-Bit
Quad/Octal A57 Core
High Speed Serial Interface: SerDes
• Two x 8-lane 10 Gbps SerDes:
total 16 lanes
• Ethernet Interfaces:
10 Gbps: 8 x XFI or 2 x XAUI
1 Gbps: 16 x SGMII, 4 x QSGMII(16 ports)
OVDD 1.89V - FUSE (PROG_SFP, PROG_MTR)
IR38060 is PMBus alternative to IR3897 (check IR for alternative low ripple SERDES Designs.
Example: IR38060 can set XnVDD/SnVDD to 5mV resolution via PMBus with low ripple.
X1234 1.35V (XnVDD Serdes Xmit)
Special Filter
AVDD_SD_PLL
Special Filter
S1234 1.00V (SnVDD Serdes Rcvr)
Special Filter
see IR recommend SERDES rails + filters to meet < 10mV ripple from T4240 design
POL Regulators
SupIRBuck®
IR3897
POL Regulators
PMBus SupIRBuck®
IR38060
1.2V
to MII, XFI
10 / 100 / 1000 to 10Gb
Alternatives: IR3473 for 1V
Core Voltage ± 3% Accuracy
DC/AC - IR3565B Meets Accuracy
specs . First DC DC solution on
Freescale’s LS2085A QDS and RDB
Reference Designs.
SFP+
2.5V / 5A
To XFI Retimers & MII1 Interface
10GE
Retimers
3.3V
POL Regulators
PMBus SupIRBuck®
IR38060
POL Regulators
PMBus SupIRBuck®
IR38060
Switches; Voltage Translator;
I2C ;Thermal Monitor; RS-232;
PCIexpress Slots (3V3_AUX),
Clocks, NOR Flash
3.3V / 5A
General Purpose
3.3V rail
power sequencing
System
FPGA
1.5V / 5A
http://www.irf.com/reference-designs/design-family/_/N~1njcj9#tab-tab1
SERDES Voltage Supplies - 1.35V, 1.8V, 1.0V
SnVdd and XnVdd and AVDD_CGx (see OVDD)
Absolute peak ripple/noise should not
exceed 10mV when measured from
50kHz to 500MHz.
IR implemented special filters to meet
these specs.