KNOWN GOOD DIE THE SureCHIP PROCESS TM THE IR ADVANTAGE ◗ KGD testing equal to package part testing ◗ 100% Avalanche capability for more than 75A ◗ Singulated testing, eliminating lateral current paths ◗ Accurate testing for RDS(on) ◗ Voltage ratings up to 1200V ◗ Leakage current testing down to nA range ◗ Pogo pins provide accurate voltage and resistance readings ◗ Hybrid modifications enable cleaner noise environment ◗ Each die is warranted to be electrically good KGD PACKAGE OPTIONS T&R option: T&R dimensions are according to die Size. Chip pack option: International Rectifier’s SureCHIP Program is a process regimen that combines high-volume manufacturing and assembly with precision parametric testing and special packaging to deliver Known Good Die (KGD) power semiconductors. The KGD process provides measurably higher yields and is an economically viable solution in the manufacturing of multi-chip modules (MCMs). As part of the SureCHIP process, individual good die from probed and sawn wafers are transferred to a custom-designed test nest for 100% electrical and visual testing. SureCHIP power semiconductor die are packaged into tape and reel in a nitrogen atmosphere or into chip trays for shipment. The SureCHIP KGD process is qualified for 100% DC parametric testing. Additionally, avalanche testing on MOSFETs and short circuit testing on IGBTs can be performed. Tray packaging option can be either 4” x 4” or 2” x 2” (outside dimensions). die.irf.com For technical support, call our Technical Assistance Center in N. America at +1.310.252.7105 and in Europe at +44.208.645.8015 THE POWER MANAGEMENT LEADER Comparison of Wafer Level Testing of RDS(on) vs. IR’s KGD Solution WAFER LEVEL TESTING THE POWER MANAGEMENT LEADER Probe Needles Die Probe Needles Wafer Vacuum Chuck Individual Die from probed and sawn wafer are transferred to a custom designed test nest for electrical testing Sense Power 1. Multiple contacts between backside of wafer and chuck tester 2. Die to Die interference cannot be isolated 3. RDS(on) accurate down to 20mΩ 4. IDRAIN measurements constrained to less than 10A 5. Parallel testing resulting in multiple signal paths that can effect results 6. Key measurements impacted by Kelvin contacts over entire backside of wafer 7. High risk for final application due to dicing operation SureCHIP is packaged in tape after passing 100% electrical testing and visual inspection IR’S KGD LEVEL TESTING Probe Needles Die is fully tested in the proprietary test nest with the true Kelvin connections to enable measurements as high current Probe Needles Die SAMPLE AVALANCHE TEST RESULTS Sense Power 1. Pogo pins provide uniform contact 2. Direct contact with isolated Die 3. RDS(on) accurate down to 2.5mΩ 4. IDRAIN Measurements possible to greater than 75A 5. Singulated testing, eliminating lateral current paths 6. Hybrid modifications enable cleaner noise environment 7. Kelvin contact fixed to single location for single die 8. Singulated die usually pre-screened for mechanical defects die.irf.com FS8272