Datasheet - International Rectifier

PD - 93912B
IRFPS3810
HEXFET® Power MOSFET
l
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
D
VDSS = 100V
RDS(on) = 0.009Ω
G
ID = 170A†
S
Description
The HEXFET® Power MOSFETs from International
Rectifier utilize advanced processing techniques to
achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed
and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in
a wide variety of applications.
Super-247™
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
170†
120†
670
580
3.8
± 30
1350
100
58
2.3
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
Max.
Units
–––
0.24
–––
0.26
–––
40
°C/W
1
04/26/02
IRFPS3810
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
100
–––
–––
3.0
52
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance …
–––
–––
–––
–––
–––
–––
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Typ.
–––
0.11
–––
–––
–––
–––
–––
–––
–––
260
49
160
24
270
45
140
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.009
Ω
VGS = 10V, ID = 100A „
5.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 50V, ID = 100A
25
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 30V
nA
-100
VGS = -30V
390
ID = 100A
74
nC
VDS = 80V
250
VGS = 10V„
–––
VDD = 50V
–––
ID = 100A
ns
–––
RG = 1.03Ω
–––
VGS = 10V „
D
Between lead,
5.0 –––
6mm (0.25in.)
nH
G
from package
13 –––
and center of die contact
S
6790 –––
VGS = 0V
2470 –––
pF
VDS = 25V
990 –––
ƒ = 1.0MHz, See Fig. 5
10740 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
1180 –––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
2210 –––
VGS = 0V, VDS = 0V to 80V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 170†
showing the
A
G
integral reverse
––– ––– 670
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 100A, VGS = 0V „
––– 220 330
ns
TJ = 25°C, IF = 100A
––– 1640 2460 nC di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
‚ Starting TJ = 25°C, L = 0.27mH
R G = 25Ω, IAS = 100A. (See Figure 12)
ƒ ISD ≤ 100A, di/dt ≤ 350A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
†
as Coss while VDS is rising from 0 to 80% VDSS
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 105A.
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IRFPS3810
1000
1000
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
100
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
100
10
1
5.0V
0.1
50µs PULSE WIDTH
T = 25 C
°
J
0.01
0.1
1
10
5.0V
10
100
3.0
TJ = 175 ° C
100
TJ = 25 ° C
10
V DS = 50V
50µs PULSE WIDTH
7
8
9
10
11
12
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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13
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
1000
6
1
10
100
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
5
°
J
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
1
50µs PULSE WIDTH
T = 175 C
1
0.1
ID = 170A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFPS3810
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
10000
Ciss
5000
Coss
Crss
VGS , Gate-to-Source Voltage (V)
20
15000
ID = 100A
VDS = 80V
VDS = 50V
VDS = 20V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
100
0
0
VDS , Drain-to-Source Voltage (V)
200
300
400
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10000
1000
ID , Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
TJ = 175 ° C
100
TJ = 25 ° C
10
0.2
V GS = 0 V
0.8
1.4
2.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100
Q G , Total Gate Charge (nC)
2.6
100
100µsec
1msec
10
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFPS3810
200
VDS
LIMITED BY PACKAGE
VGS
I D , Drain Current (A)
160
RD
D.U.T.
RG
+
-VDD
120
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
80
Fig 10a. Switching Time Test Circuit
40
VDS
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.1
0.01
0.20
0.10
0.05
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS3810
EAS , Single Pulse Avalanche Energy (mJ)
3000
1 5V
ID
41A
71A
BOTTOM 100A
TOP
2500
D R IV E R
L
VDS
2000
D .U .T
RG
+
V
- DD
IA S
20V
A
0 .0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
1500
1000
500
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
.2µF
.3µF
QGS
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFPS3810
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFPS3810
Super-247™ Package Outline
0.13 [.005]
16.10 [.632]
15.10 [.595]
2X R 3.00 [.118]
2.00 [.079]
0.25 [.010]
5.50 [.216]
4.50 [.178]
A
B A
13.90 [.547]
13.30 [.524]
2.15 [.084]
1.45 [.058]
1.30 [.051]
0.70 [.028]
4
20.80 [.818]
19.80 [.780]
16.10 [.633]
15.50 [.611]
4
C
1
2
3
B
14.80 [.582]
13.80 [.544]
5.45 [.215]
2X
Ø 1.60 [.063]
MAX.
4.25 [.167]
3.85 [.152]
3X
1.60 [.062]
1.45 [.058]
0.25 [.010]
B A
3X
1.30 [.051]
1.10 [.044]
2.35 [.092]
1.65 [.065]
S ECT ION E-E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. DIMENS IONS ARE S HOWN IN MILLIMETERS [INCHES]
3. CONTROLLING DIMENSION: MILLIMETER
4. OUTLINE CONFORMS TO JEDEC OUTLINE TO-274AA
E
E
LEAD ASS IGNMENTS
MOS FET
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
IGBT
1 - GATE
2 - COLLECTOR
3 - EMITTER
4 - COLLECTOR
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/02
8
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