Dual output, 6A/Phase, Highly Integrated SupIRBuck® Single-Input Voltage, Synchronous Buck Regulator FEATURES IR3892 DESCRIPTION • Single 5V to 21V application The IR3892 SupIRBuck® is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3892 a space-efficient solution, providing accurate power delivery for low output voltage. • Wide Input Voltage Range from 1V to 21V with external Vcc • Output Voltage Range: 0.5V to 0.86*PVin • Dual output, 6A/Phase • Enhanced Line/Load Regulation with FeedForward • Programmable Switching Frequency up to 1.0MHz • Internal Digital Soft-Start • Enable input with Voltage Monitoring Capability The switching frequency is programmable from 300kHz to 1.0MHz for an optimum solution. • Thermally compensated current limit and Hiccup Mode Over Current Protection • External synchronization with Smooth Clocking • Precision Reference Voltage (0.5V +/-1%) • Seq pin for Sequencing Applications • Integrated MOSFETs, drivers and Bootstrap diode • Thermal Shut Down IR3892 is a versatile regulator which offers programmability of switching frequency and a fixed current limit while operating in wide input and output voltage range. It also features important protection functions, Over Voltage Protection (OVP), Pre-Bias hiccup current limit and thermal shutdown required system level security in the event conditions. such as startup, to give of fault APPLICATIONS • Open Feedback Line Protection • Over Voltage Protection • Sever Applications • Interleaved Phases to reduce Input Capacitors • Netcom Applications • Monotonic Start-Up • Set Top Box Applications • Operating Junction Temp: -40 C<Tj<125 C • Storage Applications • Small Size 5mm x 6mm PQFN • Embedded telecom Systems • Lead-free, Halogen-free, and RoHS Compliant • Distributed Point of Load Power Architectures o o • Computing Peripheral Voltage regulators • General DC-DC Converters ORDERING INFORMATION Base Part Number IR3892 Standard Pack Package Type PQFN 5mm x 6mm Orderable Part Form Quantity Number Tape and Reel 4000 IR3892MTRPBF IR3892 PBF TR M 1 www.irf.com © 2014 International Rectifier Lead Free Tape and Reel Package Type Submit Datasheet Feedback May 29, 2014 IR3892 BASIC APPLICATION 5V < Vin < 21V EN2 EN1 PG2 PG1 Boot2 Seq Vcc Vin PVin1/2 Boot1 Vo2 SW2 Vo1 SW1 Vsns2 Vsns1 Fb2 Fb1 Comp2 Rt/ Sync Comp1 Gnd PGnd1/2 Figure 1: IR3892 Basic Application Circuit Figure 2: Efficiency [Vin=12V, Fsw=600kHz] PIN DIAGRAM 5mm X 6mm POWER QFN Top View 22 20 21 19 PGnd1 23 18 PGnd2 PGnd1 24 SW1 17 PGnd2 SW2 PGnd1 25 16 PGnd2 PVin1 26 15 PVin2 PVin1 27 14 PVin2 Boot1 28 13 Boot2 PGood1 29 12 PGood2 Comp1 30 11 Comp2 10 FB2 2 www.irf.com 5 EN1 Vin VCC/LDO_out GND © 2014 International Rectifier 6 7 8 9 Vsns2 4 EN2 3 RT/Sync 2 Seq 1 Vsns1 FB1 31 Submit Datasheet Feedback May 29, 2014 IR3892 FUNCTIONAL BLOCK DIAGRAM Vin VCC/LDO_out LDO + UVLO VCC + Gnd Comp VREF Seq* + + + E/A - PVin - FB Vin SOFT START UVEN FAULT LDin SSOK UVEN VREF POR UVLO POR VREF FB UV/ OV/OLFP Vsns Rff HDrv HDin Intl_SS POR FAULT CONTROL FAULT + FAULT EN Boot THERMAL TSD SHUTDOWN OV/OFLP POR OC VLDO_REF - fb UVLO CONTROL LOGIC OC GATE DRIVE LOGIC SW VCC OVER CURRENT PROTECTION LDrv PGnd UV/ OV/OLFP Rt/Sync PGood *The Seq pin is only available for channel 2 Figure 3: IR3892 Simplified Block Diagram (one phase) 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 PIN DESCRIPTIONS PIN # PIN NAME 1, 9 Vsns 1/2 2, 8 EN 1/2 3 Vin 4 VCC/LDO_out 5 GND 6 Seq 7 Rt/Sync 10, 31 FB 2/1 11, 30 Comp 2/1 12, 29 PGood 2/1 13, 28 Boot 2/1 14, 15, 26, 27 PVin 2/1 Input voltage for power stage. 16, 17, 18, 23, 24, 25 PGnd 2/1 Power Ground. These pins serve as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 19, 20, 21, 22 SW 2/1 4 www.irf.com PIN DESCRIPTION Sense pins for over-voltage protection and PGood. A resistor divider with the same ratio as the respective feedback resistor divider should be connected between each Vsns pin and its respective Vout. Enable pins for turning on and off the regulator. Input voltage for Internal LDO. A 1.0µF capacitor should be connected between this pin and PGnd. If external supply is connected to VCC pin, this pin should be shorted to VCC pin. Input Bias Voltage, output of the internal LDO. Place a minimum 2.2µF cap from this pin to PGnd. Signal ground for internal reference and control circuitry. Input to error amplifier for sequencing purposes. Can be left floating for non-sequencing applications. It is only connected to the Error-Amplifier of channel 2. Multi-function pin to set switching frequency. Use an external resistor from this pin to Gnd to set the free-running switching frequency. Or use an external clock signal to connect to this pin through a diode, the device’s switching frequency is synchronized with the external clock. Inverting inputs to the error amplifiers. These pins are connected directly to the outputs of the regulator via resistor dividers to set the output voltages and provide feedback to the error amplifiers. Output of the error amplifiers. External resistor and capacitor networks are typically connected from these pins to its respective Fb pin to provide loop compensation. Power Good status pins are open drain outputs. The pins are typically connected to VCC via pull up resistors. Supply voltages for high side drivers, 100nF capacitors should be connected between these pins and their respective SW pin. Switch nodes. These pins are connected to the output inductors. © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin Vin VCC SW BOOT BOOT to SW EN, PGood Other Input/Output pins PGnd to GND Junction Temperature Range Storage Temperature Range Machine Model ESD -0.3V to 25V -0.3V to 25V -0.3V to 8V (Note 1) -0.3V to 25V (DC), -4V to 25V (AC, 100ns) -0.3V to 33V -0.3V to VCC + 0.3V (Note 2) -0.3V to VCC + 0.3V (Note 2) -0.3V to 3.9V -0.3V to + 0.3V -40°C to 150°C -55°C to 150°C Class A Human Body Model Class 1C Charged Device Model Class III Moisture Sensitivity level JEDEC Level 2 @ 260°C RoHS Compliant Yes Note: 1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C. 2. Must not exceed 8V. THERMAL INFORMATION Thermal Resistance, Junction to Case Top (θJC_TOP) 36 °C/W Thermal Resistance, Junction to PCB (θJB) 3.6 °C/W Thermal Resistance, Junction to Ambient (θJA) (Note 3) 24.7 °C/W Note: 3. Thermal resistance (θJA) is measured with components mounted on a high effective thermal conductivity test board in free air. 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL DEFINITION MIN PVin Input Bus Voltage * 1.0 Vin Supply Voltage 5.0 VCC Supply Voltage ** 4.5 Boot to SW Supply Voltage 4.5 VO Output Voltage 0.5 IO Output Current 0 Fs Switching Frequency 300 TJ Junction Temperature -40 * SW1/2 node must not exceed 25V ** When VCC is connected to an externally regulated supply, also connect Vin. UNIT MAX 21 21 7.5 7.5 0.86 * PVin 6 1000 125 V A / Phase kHz °C ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over, 6.8V < Vin=PVin < 21V in 0°C < TJ < 125°C. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Power Stage Power Losses PLOSS Top Switch Rds(on)_Top Bottom Switch Rds(on)_Bot Bootstrap Diode Forward Voltage SW Leakage Current Dead Band Time Vin = 12V, Vout1 = 1.8V, Vout2 = 1.2V, IO = 6A/phase, Fs = 600kHz, L1 =1.0uH, L2=1.0uH, Note 4 VBoot - Vsw= 5.5V, IO = 4A, Tj = 25°C Vcc = 5.5V, IO = 4A, Tj = 25°C 2.72 I(Boot) = 10mA ISW Tdb SW = 0V, Enable = 0V SW = 0V, Enable = high, VSeq = 0V Note 4 10 W 27.5 36.4 19.5 24.2 300 450 mV 1 µA 2 µA 30 ns 20 mΩ Supply Current VIN Supply Current (standby) Iin(Standby) VIN Supply Current (dynamic) Iin(Dyn) EN = Low, No Switching 100 EN = High, Fs = 600kHz, 175 µA mA 12.0 17 5.3 5.6 V 0.75 V VCC LDO Output Output Voltage Vcc VCC Dropout Vcc_drop Short Circuit Current Ishort 6 www.irf.com © 2014 International Rectifier Vin(min) = 6.8V, Io = 060mA, Cload = 2.2uF 5 Icc = 60mA, Cload = 2.2uF 120 Submit Datasheet Feedback mA May 29, 2014 IR3892 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Oscillator Rt Voltage Vrt Frequency Range Fs Ramp Amplitude Vramp Min Pulse Width Tmin(ctrl) Max Duty Cycle Dmax Fixed Off Time Toff 1.0 Rt = 80.6K 270 300 330 Rt = 39.2K 540 600 660 Rt = 23.2K, Note 4 900 1000 1100 Vin = 6.8V, Vin slew rate max = 1V/μs, Note 4 1.02 Vin = 12V, Vin slew rate max = 1V/μs, Note 4 1.80 Vin = 21V, Vin slew rate max = 1V/μs, Note 4 3.15 Vcc=Vin = 5V, For external Vcc operation, Note 4 0.75 Note 4 Fs = 300kHz, Vin=Pvin=12V 86 Note 4 270 Sync Pulse Duration Tsync 100 High 3 ns % 200 Fsync kHz Vp-p 60 Sync Frequency Range Sync Level Threshold V 250 ns 1100 kHz 200 Low ns 0.6 V Error Amplifier Seq Input Offset Voltage Input Bias Current Seq Input impedance Sink Current Source Current Slew Rate Gain-Bandwidth Product DC Gain Vos_VSeq IFb(E/A) Rin_Seq(E/A) +3 % -200 +200 nA Internal Seq pull-up resistor kΩ 300 0.4 0.85 1.2 mA Isource(E/A) 3 4 7 mA Note 4 7 12 20 V/µs Note 4 20 30 40 MHz Note 4 80 90 110 dB 1.7 2 2.3 V 120 220 mV 0.77 V SR GBWP Gain Vmax(E/A) Minimum Voltage Vmin(E/A) Vseq Common Mode Voltage www.irf.com -3 Isink(E/A) Maximum Voltage 7 VSeq – Vfb; VSeq=250mV 0 © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Reference Voltage Feedback Voltage Vfb VSeq=3.3V 0°C < Tj < 85°C Accuracy -40°C < Tj < 125°C, Note 5 0.5 V -1 +1 -1.5 +1.5 % Soft Start Soft Start Ramp Rate Ramp (SS_start) 0.14 0.18 0.22 7.8 9 10.4 65 0.1 115 20.48 70 0.3 120 75 0.5 125 mV / µs Fault Protecion Current Limit ICC Hiccup blanking time OFLP Trip Threshold OFLP Fault Prop Delay OVP Trip Threshold OVP Trip Threshold Hysteresis Tblk_Hiccup OFLP(threshold) OFLP(delay) OVP(threshold) OVP_Hys OVP Comparator Delay Thermal Shutdown Thermal Hysteresis VCC-Start-Threshold VCC-Stop-Threshold Vcc=5.5V, Tj = 25°C Note 4 Fb Falling Vsns Rising Vsns falling from above 120% of Vref, Sync_FET turns off afterwards OVP(delay) VCC_UVLO_Start VCC_UVLO_Stop Note 4 Note 4 VCC Rising Trip Level VCC Falling Trip Level 4.0 3.7 A/ Phase ms %Vref µs %Vref 25 mV 2 140 20 4.2 3.9 µs °C °C 4.4 4.1 V Input / Output Signals Enable-Start-Threshold EN_UVLO_Start Supply ramping up 1.14 1.2 1.26 V Enable-Stop-Threshold EN_UVLO_Stop Supply ramping down 0.95 1 1.05 Enable leakage current Ien Enable=3.3V 3 4.5 µA Power Good upper VPG(upper) Vsns Rising 80 85 90 %Vref Threshold Power Good lower VPG(lower) Vsns Falling 75 80 85 %Vref Threshold Lower Threshold Delay VPG(lower)_Dly Vsns Rising 1 1.3 1.6 ms PGood Voltage Low PG(voltage) IPgood= -5mA 0.5 V Note: 4. Guaranteed by design but not tested in production. 5. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. 8 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = Internal LDO, Io=0-6A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement while running a single channel and disabling the other. VOUT (V) 1.0 1.2 1.8 3.3 5.0 9 www.irf.com LOUT (uH) 0.82 1.0 1.0 2.2 2.2 P/N SPM6550T-R82M (TDK) SPM6550T-1R0M100A (TDK) SPM6550T-1R0M100A (TDK) 7443340220 (Wurth Electronik) 7443340220 (Wurth Electronik) © 2014 International Rectifier Submit Datasheet Feedback DCR (mΩ) 4.2 4.7 4.7 4.4 4.4 May 29, 2014 IR3892 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vin = Vcc = 5V, Io=0-6A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement while running a single channel and disabling the other. VOUT (V) 1.0 1.2 1.8 3.3 5.0 10 www.irf.com LOUT (uH) 0.82 1.0 1.0 2.2 2.2 P/N SPM6550T-R82M (TDK) SPM6550T-1R0M100A (TDK) SPM6550T-1R0M100A (TDK) 7443340220 (Wurth Electronik) 7443340220 (Wurth Electronik) © 2014 International Rectifier Submit Datasheet Feedback DCR (mΩ) 4.2 4.7 4.7 4.4 4.4 May 29, 2014 IR3892 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 5V, Vcc = 5V, Io=0-6A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement while running a single channel and disabling the other. VOUT (V) 1.0 1.2 1.8 3.3 LOUT (uH) 0.68 0.82 0.82 1.0 DCR (mΩ) 3.9 4.2 4.2 4.7 P/N PCMB065T-R65MS (Cyntec) SPM6550T-R82M (TDK) SPM6550T-R82M (TDK) SPM6550T-1R0M100A (TDK) Efficiency (%) 98 96 94 92 90 88 86 84 82 80 78 76 74 0 1 2 3 4 5 6 5 6 Iout(A) 1.0Vout 1.2Vout 1.8Vout 3.3 Vout Power Loss (W) 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 Iout(A) 1.0Vout 11 www.irf.com 1.2Vout © 2014 International Rectifier 1.8Vout 3.3 Vout Submit Datasheet Feedback May 29, 2014 IR3892 THERMAL DERATING CURVES Measurements are done on IR3892 Evaluation board. PCB is a 4 layer board with 2 oz copper and FR4 material. Vin=PVin=12V, Vout1 = 1.8V, Vout2 = 1.2V, Iout1 = Iout2, VCC=internal LDO (5.3V), Fs = 600kHz Vin=PVin=12V, Vout1 =3.3V, Vout2=1.8V, Iout1 = Iout2, VCC=internal LDO (5.3V), Fs = 600kHz Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The continuous current load capability might be higher than the rating of the device if input voltage is 12V typical and switching frequency is below 600kHz. However, the maximum current is limited by the internal current limit and designers need to consider enough guard bands between load current and minimum current limit to guarantee that the device does not trip at steady state condition. 12 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 MOSFET RDSON VARIATION OVER TEMPERATURE 13 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C) 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 THEORY OF OPERATION DESCRIPTION The IR3892 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 300KHz to 1.0MHz and provides the capability of optimizing the design in terms of size and performance. IR3892 provides precisely regulated output voltage programmed via two external resistors from 0.5V to 0.86*PVin. The IR3892 operates with an internal low drop out regulator (LDO) which is connected to the VCC pin. This allows operation with a single supply. When using the internal LDO supply, the Vin pin should be connected the PVin pin. If an external bias is used, it should be connected to the VCC pin and the Vin pin should be shorted to the VCC pin. voltage exceeds its precise threshold (EN_UVLO_START), the respective channel turns on. The precise threshold allows the user to implement an Under-Voltage Lockout (UVLO) function. By deriving the EN pin voltage from the bus voltage (PVin) through a suitable resistor divider, the user can set a PVin threshold voltage. The resistor divider scales the PVin voltage for the EN pin. Only after the bus voltage reaches or exceeds this level will the voltage at the Enable pin exceeds its threshold and enable the respective IR3892 channel. By connecting IR3892 in this configuration, the user can enable the part by applying PVin and ensures the IR3892 does not turn on until the bus voltage reaches the desired level (Figure 4). Therefore, in addition to being a logic input pin that enables channels on IR3892, the EN pin also offers UVLO functionality. UVLO functionality is particularly desirable for high output voltage applications, where it is beneficial to disable the IR3892 until PVin exceeds the desired output voltage level. 12V The device utilizes the on-resistance of the low side MOSFET (sync FET) as a current sense element. This method enhances the converter’s efficiency and reduces cost by eliminating the need for an external current sense resistor. 10.2V PVin Vcc IR3892 includes two low Rds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. UNDER-VOLTAGE LOCKOUT AND POR The under-voltage lockout circuits monitor the voltage on the VCC pin and the EN1/2 pins. They ensure that the MOSFET driver outputs remain in the off state whenever either of these signals drops below the set thresholds. Normal operation resumes once VCC and EN rise above their thresholds. > 1.2V EN 1.2V EN_UVLO_START Intl_SS Figure 4: Normal Startup: IR3892 Channel starts when PVin reaches 10.2V by connecting EN to PVin using a resistor divider. The POR (Power On Ready) signal is high when all these signals reach the valid logic level (see system block diagram). ENABLE The EN pin offers another level of flexibility for startup. Each channel of the IR3892 is controlled by a separate EN pin. When the voltage at an EN pin 17 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 [V] PVin=Vin Vo Vcc EN1/2 Pre-Bias Voltage > 1.2V Intl_SS 1/2 [Time] Vo 1/2 Figure 7: Pre-bias Start Up Figure 5: Recommended startup for Normal operation 12.5% Vcc EN2 ... HDRv PVin=Vin ... LDRv > 1.2V 16 ... ... 25% ... ... 16 ... 87.5% ... ... End of PB ... Intl_SS 2 EN1 > 1.2V Intl_SS 1 SOFT-START Vo1 Vo2 Figure 6: Recommended startup for sequencing operation (ratiometric or simultaneous) Figure 5 shows the recommended start-up sequence for the normal (non-sequencing) operation of IR3892, when EN pins are used as a logic input. Figure 6 shows the recommended startup sequence for sequenced operation of IR3892. PRE-BIAS STARTUP IR3892 begins each start up by pre-charging the output to prevent oscillation and disturbances to the output voltage. The buck converter starts in an asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 7 shows a typical pre-bias sequence. The sync FET always starts with a narrow pulse width (12.5% of the switching period). The pulse width increase after 16 pulses by 12.5% until the output reaches steady state value. There are 16 pulses for each step. Figure 8 shows the series of 16 x 8 startup pulses. 18 www.irf.com Figure 8: Pre-bias startup pulses © 2014 International Rectifier IR3892 has an internal digital soft-start to control the output voltage rise and to limit the current surge during start-up. To ensure the correct start-up, the soft-start sequence initiates when the EN and VCC rise above their UVLO thresholds and generates Power On Ready (POR) signal. The internal soft-start rises with the typical rate of 0.2mV/µS from 0V to 1.5V. Figure 9 shows the waveforms during soft-start. The normal Vout start-up time is fixed, and is equal to: Tstart = (0.65V − 0.15V ) = 2.7mS 0.18mV / µS (1) During the soft-start the over-current protection (OCP) and the over-voltage protection (OVP) is enabled to protect the device from short circuit or over voltage events. Submit Datasheet Feedback May 29, 2014 IR3892 from Rt/Sync pin to GND is required to set the free running frequency. POR 3.0V 1.5V 0.65V Intl_SS 0.15V Vout t1 t2 t3 Figure 9: Theoretical operation waveforms during softstart (non-sequencing) OPERATING FREQUENCY When an external clock is applied to Rt/Sync pin after the converter runs in steady state with its free-running frequency, a transition from the free-running frequency to the external clock frequency will happen. The switching frequency gradually synchronizes to the external clock frequency regardless of which one is faster. On the contrary, when the external clock signal is removed from Rt/Sync pin, the switching frequency gradually returns to the free-running frequency. In order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and Rt/Sync pin. Figure 10 shows the timing diagram of these transitions. The switching frequency can be programmed between 300KHz-1.0MHz by connecting an external resistor from Rt/Sync pin to GND. Table 1 tabulates the oscillator frequency versus Rt. Synchronize to the external clock Free Running Frequency ... SW Table 1: Switching Frequency (Fs) vs. External Resistor (Rt) Rt (KΩ) 80.6 60.4 48.7 39.2 34 29.4 26.1 23.2 Freq (KHz) 300 400 500 600 700 800 900 1000 EXTERNAL SYNCHRONIZATION IR3892 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (POL) regulators are used. A multiplefunction pin, Rt/Sync, is used to connect the external clock. If the external clock is present before the converter turns on, Rt/Sync pin can be connected to the external clock solely and no resistor is required. If the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free-running frequency, an external resistor 19 www.irf.com © 2014 International Rectifier Return to freerunning freq Gradually change Gradually change ... Fs1 SYNC Fs1 Fs2 Figure 10: Timing diagram for synchronization to an external clock (Fs1>Fs2 or Fs1<Fs2) An internal compensation circuit is used to change the PWM ramp slope according to the clock frequency applied on Rt/Sync pin. Thus, the effective amplitude of the PWM ramp (Vramp), which is used in compensation loop calculation, has minor impact from the variation of the external synchronization signal. Vin variation also affects the ramp amplitude, which is discussed separately in Feed-Forward section. SHUTDOWN IR3892 shutdown occurs when VCC drops below its threshold or a fault occurs. When VCC falls below VCC_UVLO_STOP, the part detects an UVLO event and the part turns off. Over-Voltage Protection, OverCurrent Protection and Thermal Shutdown also cause the IR3892 shutdown. Faults are discussed in more detail below. Each channel of the IR3892 can be shutdown separately by pulling the channel EN pin below its low threshold. Each EN pin controls only one channel to allow the user to operate each independently. Submit Datasheet Feedback May 29, 2014 IR3892 OVER CURRENT PROTECTION (CURRENT LIMIT AND HICCUP MODE) Figure 11: Timing diagram for pulse-by-pulse current limit and Hiccup mode THERMAL SHUTDOWN The over-current protection is performed by sensing current through the RDS(on) of the Sync FET. This method enhances the converter’s efficiency and reduces cost by eliminating a current sense resistor. The current limit is pre-set internally and compensated to maintain an almost constant limit over temperature. IR3892 determines over-current events when the Synchronous FET is on. OCP circuit samples this current for 40 nsec typically after the rising edge of the PWM set pulse which has a width of 12.5% of the switching period. The PWM pulse starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. An OC condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. PGood will go low and the internal soft start signal will be pulled low. I OCP = I LIMIT + ∆i 2 (2) = DC current limit hiccup point = Current Limit Valley Point = Inductor ripple current IOCP ILIMIT Δi Hiccup mode is when the converter stops and waits before restarting. The channel waits for Tblk_Hiccup, 2.48 ms typical, before the OC signal resets and restarts. In normal application, the converter restarts with a pre-bias sequence and soft-start. Figure 11 shows the timing diagram of the above OC protection. If another OC event is detected, the part repeats hiccup mode. IR3892 provides thermal protection. A thermal fault is detected, when the temperature of the part reaches the Thermal Shutdown Threshold, 145°C typical. A thermal fault results in both channels turning off. The power MOSFETs are disabled during thermal shutdown. IR3892 automatically restarts when the temperature of the part drops back below the lower thermal limit, typically 20°C below the Thermal Shutdown Threshold. FEED-FORWARD Feed-Forward is an important feature which helps with stability and preserves load transient performance during PVin changes. In IR3892, Feed-Forward (F.F.) function is enabled when Vin pin is connected to PVin pin and Vin>5.0V. The PWM ramp amplitude (Vramp) is proportionally changed with respect to Vin to maintain PVin/Vramp ratio. The ratio is almost constant throughout the Vin range (as shown in Figure 12). By maintaining a constant PVin/Vramp, the control loop bandwidth and phase margin are more constant. F.F. function also helps minimize the effect of PVin changes on the output voltage. Feed-Forward is based on the Vin voltage and needs to be accounted for when calculating IR3892 compensation. The PVin/Vramp ratio is not maintained when Vin and PVin are not equal. This is the case when an external bias voltage for VCC. When using an external VCC voltage, Vin pin should be connected to the VCC pin instead of the PVin pin. Compensation for the configuration should reflect the separation. 16V 12V 0 Current Limit Hiccup PWM Ramp PWM Ramp Amplitude = 2.4V PWM Ramp Amplitude = 1.8V Tblk_Hiccup 20.48 mS* IL 12V 6.8V Vin PWM Ramp Amplitude = 1.02V 0 0 HDrv ... Figure 12: Timing diagram for Feed Forward (F.F.) Function 0 LDrv Ramp Offset ... 0 PGood *typical filter delay 0 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 LOW DROPOUT REGULATOR (LDO) Ext VCC IR3892 has an integrated low dropout (LDO) regulator which can provide gate drive voltage for both drivers. When using an internally biased configuration, the LDO draws from the Vin pin and provides a 5.3V (typ.), as shown in Figure 13. Vin and PVin can be connected together as shown in the internally biased single rail configuration, Figure 14. PVin Vin PVin IR3892 VCC PGND An external bias configuration can provide gate drive voltage for the drivers instead of the internal LDO. To use an external bias, connected to Vin and VCC to the external bias, as shown in Figure 15. PVin can also be connected or a different rail can be used. When using multiple rail configurations, calculate the compensation Vramp associated with Vin. Vramp is derived from Vin which can be different from PVin, refer to Feed-Forward section. Vin PVin Vin PVin IR3892 VCC PGND Figure 13: Internally Biased Configuration Vin Vin PVin IR3892 VCC PGND Figure 14: Internally Biased Single Rail Configuration 21 www.irf.com © 2014 International Rectifier Figure 15: Externally Biased Configuration OUTPUT VOLTAGE SEQUENCING IR3892 can accommodate user sequencing options using Seq, EN1/2, and PGood1/2 pins. In the block diagram presented on page 3, the error-amplifier (E/A) has been depicted with three positive inputs. Ideally, the input with the lowest voltage is used for regulating the output voltage and the other two inputs are ignored. In practice the voltages of the other two inputs should be at least 200mV greater than the referenced voltage input so that their effects can completely be ignored. In normal operating condition, the IR3892 channels initially follow their internal soft-starts (Intl_SS) and then references VREF. After Enable goes high, Intl_SS begins to ramp up from 0V. The FB pin follows the Intl_SS until it approaches VREF where the E/A starts to reference the VREF instead of the Intl_SS (refer to Figure 16). VREF and Seq are not referenced initially because they are higher than Intl_SS. VREF is 0.5V, typical. Seq is internally pulled up to approximately 3.3V when left floating in normal operation and only used by channel 2. In sequencing mode of operation, Vout2 is initially regulated with the Seq pin. Vout2 ramps up similar to the normal operation, but Intl_SS is replaced with Seq. Seq is kept to ground level until Intl_SS signal reaches its final value. FB2 follows Seq, until Seq approaches VREF where the E/A switches reference to the VREF. Vout2 is then regulated with respect to internal VREF (refer to Figure 17). The final Seq voltage should between 0.7V and 3.3V. Submit Datasheet Feedback May 29, 2014 IR3892 resistor values are set up in the following way, RA/RB > RE/RF > RC/RD. 0.65V OVP Is Activated Intl_SS OVP(Threshold) OVP(Hys) VPG(Upper) LDrv turned off VPG(Lower) FB/Vsns PGood Table 2 summarizes the required conditions to achieve simultaneous or ratiometric sequencing operations. Table 2: Required Conditions for Simultaneous / Ratiometric Tracking and Sequencing Seq Required Condition Floating ― Ramp up from 0V Ramp up from 0V RA/RB>RE/RF=RC/RD Operating Mode 1.3 mS* 1.3 mS* * typical filter delay Figure 16: Timing Diagram for Output Sequence Intl_SS (>0.7V) Normal (Non-sequencing, Non-tracking) Simultaneous Sequencing Ratiometric Sequencing VREF RA/RB>RE/RF>RC/RD Vin Seq OVP(Threshold) Vo1 VPG(Lower) Threshold SW2 En2 PVin Vin Vcc/LDO_out En1 SW1 VPG(Upper) Threshold Vo2 Boot2 RA FB1 RB FB/Vsns PGood 1.3 mS* 2uS* RD Vo1 PGND2 Comp2 Vsns2 PGood2 Rt/Sync GND Figure 17: Timing Diagram for Sequence Startup (Seq ramping up/down) RF Comp1 Vsns1 PGood1 Seq PGND1 RE *typical filter delay RC FB2 Figure 18: Application Circuit for Simultaneous and Ratiometric Sequencing IR3892 can perform simultaneous or ratiometric sequencing operations. Simultaneous sequencing is when the both outputs rise at the same rate. During Ratiometric sequencing, the ratio of the two outputs is held constant during power-up. Figure 19 shows examples of the two sequencing modes. IR3892 uses a single configuration to implement both mode of sequencing operations. Figure 18 shows the typical circuit configuration for both modes of sequencing operation. The sequencing mode is determined by the RA/RB, RE/RF, and RC/RD ratios. If RE/RF = RC/RD, simultaneous startup is achieved. Vout2 follows Vout1 until the voltage at the Seq pin reaches VREF. After the voltage at the Seq pin exceeds VREF, VREF dictates Vout2. In ratiometric startup, Vout2 rises at a slower rate than Vout1. The 22 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Vcc EN2 Intl_SS2 EN1 Vo1 (master) Vo2 (slave) (a) Open Feedback Loop protection (OFLP) is devised to shutdown the channel in case the feedback is broken. OFLP is activated when the Vsns is above the VPG(upper) threshold, 0.85*VREF typical, and remains active while Vsns is above the VPG(lower) threshold, 0.80*VREF. When FB drop below OFLP(threshold) threshold, 0.70*VREF, OFLP disables switching and pulls down on PGood. The part remains disabled until FB rises above OFLP(threshold) plus OFLP(Hys), 0.75*VREF. This function does not latch the part off nor does it require an EN or a VCC toggle to re-enable the part. Vo1 (master) Vo2 (slave) (b) Vsns Figure 19: Typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric Over-Voltage protection (OVP) disables the channel when the output voltage exceeds the over-voltage threshold. IR3892 achieves OVP by comparing Vsns pin to the internal over-voltage threshold set at OVP(threshold), 1.2*VREF typical. Vsns voltage is determined by an external voltage divider resistor network connected to the output in typical application. When Vsns exceeds the over-voltage threshold, an over-voltage is detected and OV signal asserts after OVP(delay). The high side drive signal HDrv is turned off immediately and PGood flags low. The low side drive signal is kept on until the Vsns voltage drops below the lower threshold. After that, HDrv is latched off until a reset is performed by cycling either VCC or the respective EN. OVP(Hys) Vsns 2uS * PGood HDrv LDrv *typical filter delay Figure 20: Timing diagram for OVP OPEN FEEDBACK-LOOP PROTECTION 23 www.irf.com VREF OFLP Trip Threshold PGood OVER-VOLTAGE PROTECTION (OVP) OVP(Threshold) FB VPG(Lower) Threshold © 2014 International Rectifier Figure 21: Timing Diagram for Open Feedback Line Protection (OFLP) POWER GOOD OUTPUT PGood is an open drain pin that monitors the UV, FAULT and the POR signals. PGood signal asserts approximately 1.3mS, after Vsns rises above VGP(Upper) threshold, 0.85*VREF typical, while FAULT is low and POR is high. It remains asserted while FAULT is low and POR is high and Vsns stays above VGP(Lower) threshold, 0.80*VREF typical. When Vsns falls below VGP(Lower) threshold there is a typical 2µS delay before PGood goes low. The two PGood signals are independent of each other and are set according to their respective channel. SWITCH NODE PHASE SHIFT The two converters on the IR3892 run interleaving phases by 180° to reduce input filter requirements. The two converters are synchronized to the user programmable oscillator. Channel 1 runs in phase with the oscillator while channel 2 runs out of phase. Staggering the switching cycles reduces the time the converters draw current from the supply simultaneously. The pulses of current drawn from the input induce voltage ripples across the input capacitor. The voltage ripple shapes are dependent on the different loading and output voltages of the two converters. By switching the converters at different times, the magnitude of voltage ripples reduces and input filter requirements become less stringent. Submit Datasheet Feedback May 29, 2014 IR3892 MINIMUM ON-TIME CONSIDERATIONS MAXIMUM DUTY RATIO The minimum on-time is the shortest amount of time which the Control FET may be reliably turned on. Internal delays and gate drive make up a large portion of the minimum on-time. IR3892 has a minimum ontime of 60nS. Maximum duty ratio is lower at higher frequencies and higher Vin voltages. A maximum off-time of 250nS is specified for IR3892. This provides an upper limit on the operating duty ratio at any given switching frequency. The off-time becomes a larger percentage of the switching period when high switching frequencies are used. Thus, a lower the maximum duty ratio can be achieved when frequencies increase. Any design or application using IR3892 should operation with a pulse width greater than minimum ontime. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. ton = Vout D = Fs PVin × Fs (3) In any application that uses IR3892, the following condition must be satisfied: t on (min) ≤ t on (4) Vout PVin × Fs V ∴ PVin × Fs ≤ out ton (min) ton (min) ≤ (5) (6) Feed-Forward from the Vin voltage placed a limitation on the maximum duty cycle by saturating the compensation ramp. By maintaining a constant Vin/Vramp, the effective Vramp voltage is increased while the maximum range is remains the same. The ramp reaches the maximum limit before reaching the expected level. Reaching the maximum limit ends the switching cycle prematurely and results in a lower maximum duty cycle. Maximum duty cycle is dependent on the Vin and switching frequency. Figure 22 is a theoretical plot of the maximum duty cycle vs. the switching frequency using typical parameter values. It shows how the maximum duty cycle is influenced by the Vin and the switching frequency. The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5V. For Vout(min) = 0.5V, ∴ PVin × Fs ≤ ∴ PVin × Fs ≤ Vout ton (min) (7) 0.5V = 8.33V / µS 60nS Therefore, with an input voltage 16V and minimum output voltage, the converter should be designed for switching frequency not to exceed 520kHz. Conversely, the input voltage (PVin) should not exceed 5.55V for operation at the maximum recommended operating frequency (1.0MHz) and minimum output voltage (0.5V). Increasing the PVin greater than 5.55V will cause pulse skipping. 24 www.irf.com © 2014 International Rectifier Figure 22: Maximum Duty Cycle vs. Switching Frequency Submit Datasheet Feedback May 29, 2014 IR3892 DESIGN EXAMPLE The following example is a typical application for IR3892. The application circuit is shown in Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The FB pin is the inverting input of the error amplifier, which is internally referenced to VREF. The divider ratio is set to equal VREF at the FB pin when the output is at its desired value. When an external resistor divider is connected to the output as shown in Figure 24, the output voltage is defined by using the following equation: Vin = PVin = 12V (21V Max) Fs = 600kHz Channel 1: Vo = 1.8V Io = 6A Ripple Voltage = ± 1% * Vo ΔVo = ± 4% * Vo (for 30% load transient) R Vo = Vref × 1 + 5 R6 Channel 2: Vo = 1.2V Io = 6A Ripple Voltage = ± 1% * Vo ΔVo = ± 4% * Vo (for 30% load transient) Vref R6 = R5 × V −V ref o Enabling the IR3892 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage as shown in Figure 23. (10) (11) For the calculated values of R5 and R6, see feedback compensation section. Vout PVin IR3892 IR3892 R1 R5 FB R6 Enable R2 Figure 23: Using Enable pin for UVLO implementation For a typical Enable threshold of VEN = 1.2 V R2 PVin (min) × = V EN = 1.2 R1 + R2 R2 = R1 V EN PVin (min) − V EN Bootstrap Capacitor Selection (8) (9) For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1. 25 www.irf.com Figure 24: Typical application of the IR3892 for programming the output voltage © 2014 International Rectifier To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode (Figure 25), which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C1 is approximately given as: Vc ≅ Vcc − VD Submit Datasheet Feedback (12) May 29, 2014 IR3892 When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: VBoot ≅ Vin + Vcc − VD Cvin + VD - (13) Inductor Selection Inductors are selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but may reduce efficiency and cause higher output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (Δi). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: VIN Boot Vcc C1 SW IR3892 Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 4x10uF, 25V ceramic capacitors, C3216X5R1E106K from TDK. In addition to these, although not mandatory, a 1x330uF, 25V SMD capacitor EEVFK1E331P from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. + Vc L PGnd Figure 25: Bootstrap circuit to generate Vc voltage ∆i 1 ; ∆t = D × ∆t Fs Vo L = (Vin − Vo ) × Vin × ∆i × Fs Vin − Vo = L × A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple currents generated during the on time of the control FETs should be provided by the input capacitor. The RMS value of this ripple for each channel is expressed by: I RMS = I o × D × (1 − D ) D= Vo Vin (14) (15) Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For channel 1, Io=6A and D=0.15, the IRMS = 2.14A. For channel 2, Io=6A and D=0.1, the IRMS = 1.8A. Where: Vin V0 Δi Fs Δt D (16) = Maximum input voltage = Output Voltage = Inductor Peak-to-Peak Ripple Current = Switching Frequency = On time for Control FET = Duty Cycle If Δi ≈ 30%*Io, then the channel 1 output inductor is calculated to be 1.42μH. Select L=1.0μH, SPM6550T1R0M100A, from TDK which provides a compact, low profile inductor suitable for this application. For channel 2, the output inductor is calculated to be 1.0μH. Select L=1.0μH, SPM6550T-1R0M100A, from TDK. Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criterion is normally based on the value of the 26 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o. The resonant frequency of the LC filter is expressed as follows: ∆Vo = ∆Vo ( ESR ) + ∆Vo ( ESL ) + ∆Vo (C ) FLC = ∆V0 ( ESR ) = ∆I L × ESR V −V ∆V0 ( ESL ) = in o × ESL L ∆I L ∆V0 (C ) = 8 × Co × Fs 1 (18) 2 × π × Lo × Co Figure 26 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. Phase Gain (17) 0dB 00 -40dB/Decade Where: ΔV0 = Output Voltage Ripple ΔIL = Inductor Ripple Current -900 -1800 Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3892 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Four of TDK C2012X5R0J226M (22uF/0805/X5R/6.3V) capacitors is a good choice for channel 1 and channel 2. It is also recommended to use a 0.1µF ceramic capacitor at the output for high frequency filtering. Feedback Compensation The IR3892 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to have a stable closed-loop transfer function with a high crossover frequency and o phase margin greater than 45 . 27 www.irf.com © 2014 International Rectifier FLC Frequency FLC Frequency Figure 26: Gain and Phase of LC filter The IR3892 uses a voltage-type error amplifier with high-gain and high-bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Local feedback with Type II compensation is shown in Figure 27. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. If the output capacitor’s ESR generates a zero at 5kHz to 50kHz, the zero generates acceptable phase margin and the Type II compensator can be used. The ESR zero of the output capacitor is expressed as follows: FESR = 1 2 × π × ESR × Co Submit Datasheet Feedback (19) May 29, 2014 IR3892 VOUT Z IN FLC = Resonant Frequency of the Output Filter R5 = Feedback Resistor C POLE R3 C3 R5 Zf Fb E/A R6 Comp Ve FZ = 75% × FLC FZ = 0.75 × VREF Gain(dB) To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: 1 2 × π Lo × Co (25) H(s) dB Use equation (22), (23) and (24) to calculate C3. F FZ Frequency POLE Figure 27: Type II compensation network and its asymptotic gain plot The additional pole is given by: The transfer function (Ve/Vout) is given by: Z 1 + sR3C3 Ve = H (s) = − f = − Z IN sR5C3 Vout Fp = (20) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: H (s) = Fz = R3 R5 (21) 1 2 × π × R3 × C3 (22) First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1 / 5 ~ 1 / 10) × Fs One more capacitor is sometimes added in parallel with C3 and R3. This introduces one more pole which is mainly used to suppress the switching noise. 1 C × C POLE 2×π × 3 C3 + C POLE (26) The pole sets to one half of the switching frequency which results in the capacitor CPOLE: CPOLE = 1 1 π × R3 × FS − C3 ≅ 1 π × R3 × FS (27) For an unconditional stability general solution using any type of output capacitors with a wide range of ESR values, use local feedback with type III compensation network. Type III compensation network is typically used for voltage-mode controller as shown in Figure 28. (23) Use the following equation to calculate R3: R3 = Vramp × Fo × FESR × R5 2 Vin × FLC (24) Where: Vin = Maximum Input Voltage Vramp = Amplitude of the oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 VOUT ZIN C2 C4 R4 R3 Zf Fb R6 Ve Comp E/ A FZ 2 (33) Cross over frequency is expressed as: Fo = R3 × C 4 × VREF Gain (dB) Vin 1 × Vramp 2π × Lo × C o (34) Based on the frequency of the zero generated by the output capacitor and its ESR, relative to the crossover frequency, the compensation type can be different. Table 3 shows the compensation types for relative locations of the crossover frequency. |H(s)| dB FZ1 FZ 2 FP2 FP3 Frequency Figure 28: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: Zf Ve = H (s) = − Z IN Vout By replacing Zin and Zf, according to Figure 28, the transfer function can be expressed as: H ( s) = − (32) C3 R5 1 2π × R3 × C3 1 1 = ≅ 2π × C 4 × (R4 × R5 ) 2π × C 4 × R5 FZ 1 = (1 + sR3C3 )[1 + sC4 (R4 + R5 )] C × C3 (1 + sR4C4 ) sR5 (C2 + C3 )1 + sR3 2 + C C 2 3 (28) The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 (29) 1 2π × R4 × C4 1 1 FP 3 = ≅ C × C3 2π × R3 × C2 2π × R3 2 C2 + C3 FP 2 = (30) (31) Table 3: Different types of compensators Compensator Type FESR vs FO Typical Output Capacitor Type II FLC < FESR < FO < FS/2 Electrolytic Type III FLC < FO < FESR SP Cap, Ceramic The higher the crossover frequency is, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency (Fo) is selected such that: Fo ≤ (1/5 ~ 1/10 )* Fs The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. The specifications for designing channel 1: Vin = 12V Vo = 1.8V Vramp= 1.8V (This is a function of Vin, pls. see Feed-Forward section) Vref = 0.5V Lo = 1.0uH Co = 4x22uF, ESR≈3mΩ each It must be noted here that the value of the capacitance used in the compensator design must be 29 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 15uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (18) to compute the small signal Co. These result to: FLC = 20.6 kHz FESR = 3.54 MHz Fs/2 = 300 kHz Select crossover frequency F0=100 kHz Since FLC<F0<Fs/2<FESR, Type III is selected to place the pole and zeros. Select: C3 = 4.7 nF C2 = Select: C2 = 100 pF Calculate R4, R5 and R6: R4 = FZ 2 = Fo R5 = 1 ; R5 = 1 kΩ, 2 × π × C4 × FZ 2 Select R5 = 11.8 kΩ R6 = 1 − sin Θ = 13.2 kHz 1 + sin Θ 1 ; R4 = 209.5 Ω, 2 × π × C4 × FP 2 Select R4 = 210 Ω Detailed calculation of compensation Type III: Desired Phase Margin Θ = 75° 1 ; C2 = 94 pF, 2 × π × FP 3 × R3 Vref Vo − Vref × R5 ; R6 = 4.54 kΩ, Select R6 = 4.53 kΩ Setting the Power Good Threshold FP 2 = Fo 1 + sin Θ = 759.6 kHz 1 − sin Θ Select: FZ 1 = 0.5 × FZ 2 = 6.6 kHz and FP 3 = 0.5 × Fs = 300 kHz Select C4 = 1nF. 2 × π × Fo × Lo × C o × Vramp C 4 × Vin ; R3 = 5.65 kΩ, 30 1 ; C3 = 4.29 nF, 2 × π × FZ 1 × R3 www.irf.com The following formula can be used to set the PGood threshold. Vout (PGood_TH) can be taken as 85% of Vout. V Rsns12 = out ( PGood _ TH ) − 1 × Rsns11 0.85 × VREF (35) Rsns12 = 11.78 kΩ, Select 11.8 kΩ, Select: R3 = 5.62 kΩ C3 = As long as the Vsns voltage is between the threshold range, Enable is high, and no fault happens, the PGood remains high. Choose Rsns11=4.53 KΩ. Calculate R3, C3 and C2: R3 = In this design IR3892, the PGood outer limits are set at 85% and 120% of VREF. PGood signal is asserted 1.3ms after Vsns voltage reaches 0.85*0.5V=0.425V. © 2014 International Rectifier OVP comparator also uses Vsns signal for OverVoltage detection. With above values for Rsns22 and Rsns21, OVP trip point (Vout_OVP) is Submit Datasheet Feedback May 29, 2014 IR3892 Vout _ OVP = VREF × 1.2 × (Rsns11 + Rsns12) Rsns11 FP 3 = 0.5 × Fs = 300 kHz (36) Select C4 = 1nF. Vout_OVP = 2.16 V Calculate R3, C3 and C2: Selecting Power Good Pull-Up Resistor The PGood1 and PGood2 are open drain outputs and require pull up resistors to VCC. The value of the pullup resistors should limit the current flowing into the each PGood pin to be less than 5mA. A typical value used is 49.9kΩ. The specifications for the channel 2 design: Vin=12V Vo=1.2V Vramp=1.8V (This is a function of Vin, pls. see feed forward section) Vref=0.5V Lo=1.0uH Co=4x22uF, ESR≈3mΩ each In the calculations, 18uF is used for the 22uF Co capacitors due to the 1.2V bias and 600 kHz frequency. These result to: FLC = 18.8 kHz FESR = 2.95 MHz Fs/2 = 300 kHz Select crossover frequency F0=100 kHz Since FLC<F0<Fs/2<FESR, Type III is selected to place the pole and zeros. R3 = 2 × π × Fo × Lo × C o × Vramp C 4 × Vin ; R3 = 6.79 kΩ, Select: R3 = 6.65 kΩ C3 = 1 ; C3 = 3.63 nF, 2 × π × FZ 1 × R3 Select: C3 = 3.6 nF C2 = 1 ; C2 = 78.8 pF, 2 × π × FP 3 × R3 Select: C2 = 82 pF Calculate R4, R5 and R6: R4 = 1 ; R4 = 209.5 Ω, 2 × π × C4 × FP 2 Select R4 = 210 Ω R5 = 1 ; R5 = 12.1 kΩ, 2 × π × C4 × FZ 2 Select R5 = 11.8 kΩ Detailed calculation of compensation Type III: Desired Phase Margin Θ = 75° FZ 2 = Fo 1 − sin Θ = 13.2 kHz 1 + sin Θ 1 + sin Θ FP 2 = Fo = 759.6 kHz 1 − sin Θ Select: FZ 1 = 0.5 × FZ 2 = 6.6 kHz and 31 www.irf.com © 2014 International Rectifier R6 = Vref Vo − Vref × R5 ; R6 = 8.43 kΩ, Select R6 = 8.45 kΩ Setting the Power Good Threshold Equation (35) shows how to set values for Rsns12 and Rsns11. Use the same equation to determine Rsns21 and Rsns22 values, but substitute Rsns22 for Rsns12 and Rsns21 for Rsns11. Choose Rsns21=8.45 KΩ. Submit Datasheet Feedback May 29, 2014 IR3892 Vout ( PGood _ TH ) − 1 × Rsns 21 Rsns 22 = 0.85 × VREF (37) Rsns22 = 11.83 kΩ; Select 11.8 kΩ, The typical over-voltage threshold is calculated below for channel 2. With above values for Rsns22 and Rsns21, OVP trip point (Vout_OVP) is Vout _ OVP = VREF × 1.2 × (Rsns 21 + Rsns 22) (38) Rsns 22 Vout_OVP = 1.44 V 32 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 APPLICATION DIAGRAM INTERNALLY BIASED SINGLE RAIL Vin Ren12 49.9 K Rpg1 49.9 K PG1 PGood1 EN1 Ren11 7.5 K Cvin 1 uF Cboot1 0.1 uF Vin Cvcc 2.2 uF Vcc Cpvin2 4 x 10 uF PVin1/2 Cpvin1 330 uF Cpvin3 2 x 0.1 uF Rpg2 49.9 K PGood2 PG2 EN2 Boot1 Boot2 SW1 SW2 Cc11 1000 pF Rc11 210 Rc12 5.62 K Rfb12 11.8 K Rfb11 4.53 K 1.0 uH Comp2 IR3892 Cc13 100 pF Cc23 82 pF Comp2 FB1 Vsns1 Rsns11 4.53 K Rt/Sync Cc12 4.7 nF PGND1/2 Rsns12 11.8 K Comp1 GND Rbd1 20 Cout1 4 x 22 uF L1 1.0 uH Seq Co1 0.1 uF Ren21 7.5 K Cboot2 0.1 uF L0 Vo1 Ren22 49.9 K Vo2 Rbd2 20 Cc22 3.6 nF Cc21 1000 pF Rc22 6.65 K Rt 39.2 K Co2 0.1 uF Rsns22 11.8 K Rc21 210 Rfb22 11.8 K Vsns2 Cout2 4 x 22 uF Rfb21 8.45 K Rsns21 8.45 K Figure 29: Application circuit for 12V to 1.8V and 1.2V, 6A Point of Load Converter Using the Internal LDO 33 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Suggested Bill of Material for application circuit 12V to 1.8V and 1.2V Part Reference Cpvin1 Cpvin2 Cvin Cvcc Co1 Co2 Cboot1 Cboot2 Cpvin3 Cc11 Cc21 Cc12 Cc13 Cc22 Cc23 Cout1 Cout2 Qty 1 4 1 1 Value 330uF 10uF 1.0uF 2.2uF Description SMD, electrolytic, 25V, 20% 1206, 25V, X5R, 10% 0603, 25V, X5R, 10% 0603, 16V, X5R, 20% Manufacturer Panasonic TDK Murata TDK Part Number EEV-FK1E331P C3216X5R1E106M GRM188R61E105KA12D C1608X5R1C225M 6 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D 2 1 1 1 1 8 1000pF 4.7nF 100pF 3.6nF 82pF 22uF Murata Murata Murata Murata Murata TDK GRM188R71H102KA01D GRM188R71H472KA01D GRM1885C1H101JA01D GRM1885C1H362JA01D GRM1885C1H820JA01D C2012X5R0J226M L0 L1 2 1.0uH TDK SPM6550T-1R0M100A Rbd1 Rbd2 Ren12 Ren22 Rpg1 Rpg2 Ren11 Ren21 Rc11 Rc21 Rc12 Rc22 Rfb11 Rsns11 Rfb12 Rsns12 Rfb22 Rsns22 Rfb21 Rsns21 Rt 2 20 0603, 50V, X7R, 10% 0603, 50V, X7R, 10% 0603, 50V, NPO, 5% 0603, 50V, NPO, 5% 0603, 50V, NPO, 5% 0805, 6.3V X5R, 20% SMT 6.5x7x5mm, DCR=4.7mΩ Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF20R0V 4 49.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4992V 2 2 1 1 2 7.5K 210 5.62K 6.65K 4.53K Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Panasonic Panasonic Panasonic Panasonic Panasonic ERJ-3EKF7501V ERJ-3EKF2100V ERJ-3EKF5621V ERJ-3EKF6651V ERJ-3EKF4531V 4 11.8K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1182V 2 1 8.45K 39.2K Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% ERJ-3EKF8451V ERJ-3EKF3922V U1 1 IR3892 PQFN 5x6mm Panasonic Panasonic International Rectifier 34 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback IR3892MPBF May 29, 2014 IR3892 EXTERNALLY BIASED DUAL RAIL PVin Vin Ren12 49.9 K Rpg1 49.9 K PG1 PGood1 EN1 Ren11 7.5 K Cvin 1 uF Cboot1 0.1 uF Vin Cvcc 2.2 uF Vcc Cpvin2 4 x 10 uF PVin1/2 Cpvin1 330 uF Cpvin3 2 x 0.1 uF Rpg2 49.9 K PGood2 PG2 EN2 Boot1 Boot2 SW1 SW2 Rc11 210 Rc12 2.43 K Rfb12 11.8 K Rfb11 4.53 K Cc13 220 pF Cc23 180 pF Comp2 FB1 Vsns1 Rsns11 4.53 K Rt/Sync Cc11 1000 pF 1.0 uH Comp2 IR3892 PGND1/2 Rsns12 11.8 K Cc12 10 nF GND Cout1 4 x 22 uF Comp1 Seq Co1 0.1 uF L1 1.0 uH Rbd1 20 Ren21 7.5 K Cboot2 0.1 uF L0 Vo1 Ren22 49.9 K Vo2 Rbd2 20 Cc22 8.2 nF Cc21 1000 pF Rc22 2.94 K Rt 39.2 K Co2 0.1 uF Rsns22 11.8 K Rc21 210 Rfb22 11.8 K Vsns2 Cout2 4 x 22 uF Rfb21 8.45 K Rsns21 8.45 K Figure 30: Application circuit for a 12V to 1.8V and 1.2V, 4A Point of Load Converter using external 5V VCC 35 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Suggested Bill of Material for application circuit 12V to 1.8V and 1.2V using external 5V VCC Part Reference Cpvin1 Cpvin2 Cvin Cvcc Cpvin3 Cboot1 Cboot2 Co1 Co2 Cc11 Cc21 Cc12 Cc13 Cc22 Cc23 Cout1 Cout2 Qty 1 4 1 1 Value 330uF 10uF 1.0uF 2.2uF Description SMD, electrolytic, 25V, 20% 1206, 25V, X5R, 10% 0603, 25V, X5R, 10% 0603, 16V, X5R, 20% Manufacturer Panasonic TDK Murata TDK Part Number EEV-FK1E331P C3216X5R1E106M GRM188R61E105KA12D C1608X5R1C225M 6 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D 2 1 1 1 1 8 1000pF 10nF 220pF 8.2nF 180pF 22uF Murata Murata Murata Murata Murata TDK GRM188R71H102KA01D GRM188R71H103KA01D GRM1885C1H221JA01D GRM188R71H822KA01D GRM1885C1H181JA01D C2012X5R0J226M L0 L1 2 1.0uH TDK SPM6550T-1R0M100A Rbd1 Rbd2 Rc11 Rc21 Rc12 Rc22 Ren11 Ren21 Ren12 Ren22 Rpg1 Rpg2 Rfb11 Rsns11 Rfb12 Rsns12 Rfb22 Rsns22 Rfb21 Rsns21 Rt 2 2 1 1 2 20 210 2.43K 2.94K 7.5K 0603, 50V, X7R, 10% 0603, 50V, X7R, 10% 0603, 50V, NPO, 5% 0603, 50V, X7R, 10% 0603, 50V, NPO, 5% 0805, 6.3V X5R, 20% SMT 6.5x7x5mm, DCR=4.7mΩ Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Panasonic Panasonic Panasonic Panasonic Panasonic ERJ-3EKF20R0V ERJ-3EKF2100V ERJ-3EKF2431V ERJ-3EKF2941V ERJ-3EKF7501V 4 49.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4992V 2 4.53K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4531V 4 11.8K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1182V 2 1 8.45K 39.2K Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% ERJ-3EKF8451V ERJ-3EKF3922V U1 1 IR3892 PQFN 5x6mm Panasonic Panasonic International Rectifier 36 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback IR3892MPBF May 29, 2014 IR3892 EXTERNALLY BIASED SINGLE RAIL Vin Ren12 41.2 K Rpg1 49.9 K PG1 PGood1 EN1 Ren11 21 K Cvin 1 uF Cboot1 0.1 uF Vin Cvcc 2.2 uF Vcc Cpvin2 8 x 10 uF PVin1/2 Cpvin1 330 uF Cpvin3 2 x 0.1 uF Rpg2 49.9 K PGood2 PG2 EN2 Boot1 Boot2 SW1 SW2 Rc11 210 Rc12 5.62 K Rfb12 11.8 K Rfb11 4.53 K Cc13 91 pF Cc23 91 pF Comp2 FB1 Vsns1 Rsns11 4.53 K Rt/Sync Cc11 1000 pF 1.0 uH Comp2 IR3892 PGND1/2 Rsns12 11.8 K Comp1 Cc12 3.9 nF GND Cout1 4 x 22 uF Seq Co1 0.1 uF L1 1.0 uH Rbd1 20 Ren21 21 K Cboot2 0.1 uF L0 Vo1 Ren22 41.2 K Vo2 Rbd2 20 Cc22 3.9 nF Cc21 1000 pF Rc22 5.62 K Rt 39.2 K Co2 0.1 uF Rsns22 11.8 K Rc21 210 Rfb22 11.8 K Vsns2 Cout2 4 x 22 uF Rfb21 8.45 K Rsns21 8.45 K Figure 31: Application circuit for a 5V to 1.8V and 1.2V, 4A Point of Load Converter 37 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Suggested bill of material for application circuit 5V to 1.8V and 1.2V Part Reference Cpvin1 Cpvin2 Cvin Cvcc Cpvin3 Cboot1 Cboot2 Co1 Co2 Cc11 Cc21 Cc12 Cc22 Cc13 Cc23 Cout1 Cout2 Qty 1 8 1 1 Value 330uF 10uF 1.0uF 2.2uF Description SMD, electrolytic, 25V, 20% 1206, 25V, X5R, 10% 0603, 25V, X5R, 10% 0603, 16V, X5R, 20% Manufacturer Panasonic TDK Murata TDK Part Number EEV-FK1E331P C3216X5R1E106M GRM188R61E105KA12D C1608X5R1C225M 6 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D 2 2 2 8 1000pF 3.9nF 91pF 22uF Murata Murata Murata TDK GRM188R71H102KA01D GRM188R71H392KA01D GRM1885C1H910JA01D C2012X5R0J226M L0 L1 2 1.0uH TDK SPM6550T-1R0M100A Rbd1 Rbd2 Rc11 Rc21 Rc12 Rc22 Ren11 Ren21 Ren12 Ren22 Rfb11 Rsns11 Rfb12 Rsns12 Rfb22 Rsns22 Rfb21 Rsns21 Rpg1 Rpg2 Rt 2 2 2 2 2 2 20 210 5.62K 21K 41.2K 4.53K 0603, 50V, X7R, 10% 0603, 50V, X7R, 10% 0603, 50V, NPO, 5% 0805, 6.3V X5R, 20% SMT 6.5x7x5mm, DCR=4.7mΩ Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ERJ-3EKF20R0V ERJ-3EKF2100V ERJ-3EKF5621V ERJ-3EKF2102V ERJ-3EKF4122V ERJ-3EKF4531V 4 11.8K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF1182V 2 2 1 8.45K 49.9K 39.2K Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% Thick Film, 0603, 1/10W, 1% ERJ-3EKF8451V ERJ-3EKF4992V ERJ-3EKF3922V U1 1 IR3892 PQFN 5x6mm Panasonic Panasonic Panasonic International Rectifier 38 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback IR3892MPBF May 29, 2014 IR3892 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow Figure 32: Startup with full load CH1:Vout1, Ch2:Vout2, Ch3:Vin, CH4:Vcc Figure 33: PGood signals at Startup with full load CH1:Vout1, Ch2:Vout2, Ch3:PGood1, CH4:PGood2 Figure 34: Channel 1 Startup with Pre-Bias, 1.52V CH1:Vout1, Ch3:PGood1, Ch4:Enable1 Figure 35: Channel 2 Startup with Pre-Bias, 1.05V CH2: Vout2, Ch2: PGood2 , Ch4:Enable2 Figure 36: Inductor Switch Nodes at full load CH1:SW1, Ch2:SW2 Figure 37: Output Voltage Ripples at full load CH1:Vout1, Ch2:Vout2 39 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow Figure 38: Vout1 Transient Response, 4.2A to 6A step at 2.5A/µSec CH1:Vout1, CH2=Vout2, CH4:Iout1 40 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow Figure 39: Vout2 Transient Response, 4.2A to 6A step at 2.5A/µSec CH1:Vout1, CH2=Vout2, CH4:Iout2 41 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 TYPICAL OPERATING WAVEFORMS Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow Figure 40: CH1 Bode Plot with 6A load, CH2 disabled. Fo = 96.3 kHz, Phase Margin = 56.2 Degrees Figure 41: CH2 Bode Plot with 6A load, CH1 disabled. Fo = 97 kHz, Phase Margin = 54 Degrees 42 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components on the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, input capacitors, output capacitors and the IR3892 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3892. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for PVin and VCC should be close to their respective - Ground path length between VIN- and VOUT1should be minimized with maximum copper pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane on top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 42a-d illustrates the implementation of the layout guidelines outlined above, on the IRDC3892 4-layer demo board. Vout1 - Compensation parts should be placed as close as possible to the Comp pins - Bypass caps should be placed as close as possible to their PVin - Single point connection between AGND & PGND, should be placed near the part and kept away from noise sources AGND - SW node copper is kept only at the top layer to minimize the switching noise PGND - Ground path length between VIN- and VOUT2- should be minimized with maximum copper Vout2 Figure 42a: IRDC3892 Demo board Layout Considerations – Top Layer 43 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 PGND Figure 42b: IRDC3892 Demo board Layout Considerations – Bottom Layer PGND AGND Feedback and Vsns trace routing should be kept away from noise sources Figure 42c: IRDC3892 Demo board Layout Considerations – Mid Layer 1 Vin PGND Figure 42d: IRDC3892 Demo board Layout Considerations – Mid Layer 2 44 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and Figure 43: PCB Pad Sizes Detail 1 (Dimensions in mm) experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck® Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 44: PCB Pad Sizes Detail 2 (Dimensions in mm) Figure 45: PCB Metal Pad Spacing (Dimensions in mm) 45 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 SOLDER RESIST • • IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD). This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y). • However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. • When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X & Y), in order to accommodate any layer to layer misalignment. • Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 46: SMD Pad Sizes Detail 1 (Dimensions in mm) 46 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Figure 47: SMD Pad Sizes Detail 2 (Dimensions in mm) Figure 48: SMD Pad Spacing (Dimensions in mm) 47 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 STENCIL DESIGN • Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. • Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 49: Stencil Pad Sizes (Dimensions in mm) 48 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Figure 50: Stencil Pad Spacing Detail 1 (Dimensions in mm) Figure 51: Stencil Pad Spacing Detail 2 (Dimensions in mm) 49 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 MARKING INFORMATION Figure 52: Marking Information 50 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 PACKAGING INFORMATION 51 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 ENVIRONMENTAL QUALIFICATIONS Industrial Qualification Level Moisture Sensitivity Level 5mm x 6mm PQFN Machine Model (JESD22-A115A) ESD Human Body Model (JESD22-A114F) Charged Device Model (JESD22-C101D) MSL2 Class A <200V Class 1C ≥1000V to <2000V Class III ≥500V to ≤1000V Yes RoHS Compliant Data and specifications subject to change without notice. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com 52 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014