IRMCF188 High Performance Sensorless Motor Control IC Description IRMCF188 is a high performance Flash based motion control IC designed and optimized for complete air conditioner control which contains two computation engines integrated into one monolithic chip. One is the Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors; the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCF188 performs a PFC (Power Factor Correction) function in addition to the motor control. IRMCF188 comes in a 64 pin QFP package. Features • • • • • • • • • • • • • • • Product Summary MCETM (Flexible Motion Control Engine) Dedicated computation engine for high efficiency sinusoidal sensorless motor control Built-in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits Supports induction machine and both interior and surface permanent magnet motor sensorless control Dedicated PFC PWM for digital PFC control Loss minimization Space Vector PWM Three-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) I2C/SPI serial interface Three general purpose timers/counters Two special timers: periodic timer, capture timer Watchdog timer with independent internal clock Internal 64 Kbyte flash memory 3.3V single supply Base Part Number Package Type IRMCF188 IRMCF188 1 www.irf.com Maximum clock input (fcrystal) Maximum Internal clock (SYSCLK) Maximum 8051 clock (8051CLK) MCETM computation data range 8051 Program Flash 8051/MCE Data RAM MCE Program RAM GateKill latency (digital filtered) PWM carrier frequency A/D input channels A/D converter resolution A/D converter conversion speed Analog output (PWM) resolution UART baud rate (typ) Number of digital I/O (max) Package (lead free) Typical 3.3V operating current Standard Pack 60 MHz 120MHz 30MHz 16 bit signed 52KB 4KB 12KB 2 μsec 20 bits/ SYSCLK 10 12 bits 2 μsec 8 bits 57.6 Kbps 24 QFP64 30mA Orderable Part Number Form Quantity LQFP64 Tape and Reel 1500 IRMCF188TR LQFP64 Tray 1600 IRMCF188TY © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 Table of Contents 1 Overview ................................................................................................................................ 5 2 Pinout ..................................................................................................................................... 6 3 IRMCF188 Block Diagram and Main Functions ..................................................................... 7 4 Application connection and Pin function................................................................................. 9 4.1 8051 Peripheral Interface Group .......................................................................................... 10 4.2 Motion Peripheral Interface Group ....................................................................................... 11 4.3 Analog Interface Group ........................................................................................................ 12 4.4 Power Interface Group ......................................................................................................... 12 4.5 Test Interface Group ............................................................................................................ 12 5 DC Characteristics ............................................................................................................... 14 5.1 Absolute Maximum Ratings.................................................................................................. 14 5.2 System Clock Frequency and Power Consumption ............................................................. 14 5.3 Digital I/O DC Characteristics............................................................................................... 15 5.4 Analog I/O DC Characteristics ............................................................................................. 16 5.5 Under Voltage Lockout DC characteristics........................................................................... 17 5.6 Itrip comparator DC characteristics ...................................................................................... 17 5.7 CMEXT and AREF Characteristics ...................................................................................... 17 6 AC Characteristics................................................................................................................ 18 6.1 Digital PLL AC Characteristics ............................................................................................. 18 6.2 Analog to Digital Converter AC Characteristics.................................................................... 19 6.3 Op amp AC Characteristics .................................................................................................. 20 6.4 SYNC to SVPWM and A/D Conversion AC Timing .............................................................. 21 6.5 GATEKILL to SVPWM AC Timing ........................................................................................ 22 6.6 Itrip AC Timing...................................................................................................................... 22 6.7 Interrupt AC Timing .............................................................................................................. 23 6.8 I2C AC Timing ...................................................................................................................... 24 6.9 SPI AC Timing ...................................................................................................................... 25 6.10 UART AC Timing ................................................................................................................ 27 6.11 CAPTURE Input AC Timing ................................................................................................ 28 6.12 JTAG AC Timing ................................................................................................................. 29 7 I/O Structure ......................................................................................................................... 30 8 Pin List.................................................................................................................................. 34 9 Package Dimensions............................................................................................................ 36 10 Part Marking Information ...................................................................................................... 37 11 Qualification Information....................................................................................................... 37 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 List of Tables Table 1. Analog channel sensing functions in Leg and Single Shunt Modes ........................... 12 Table 2. Absolute Maximum Ratings ....................................................................................... 14 Table 3. System Clock Frequency ........................................................................................... 14 Table 4. Digital I/O DC Characteristics .................................................................................... 15 Table 6. Analog I/O DC Characteristics ................................................................................... 16 Table 7. UVcc DC Characteristics ........................................................................................... 17 Table 8. Itrip DC Characteristics .............................................................................................. 17 Table 9. CMEXT and AREF DC Characteristics ...................................................................... 17 Table 10. PLL AC Characteristics ............................................................................................ 18 Table 11 . A/D Converter AC Characteristics .......................................................................... 19 Table 12 Current Sensing OP Amp AC Characteristics ........................................................... 20 Table 13. SYNC AC Characteristics ........................................................................................ 21 Table 14. GATEKILL to SVPWM AC Timing ........................................................................... 22 Table 15. Itrip AC Timing ......................................................................................................... 22 Table 16. Interrupt AC Timing.................................................................................................. 23 Table 17. I2C AC Timing ......................................................................................................... 24 Table 18. SPI Write AC Timing ................................................................................................ 25 Table 19. SPI Read AC Timing................................................................................................ 26 Table 20. UART AC Timing ..................................................................................................... 27 Table 21. CAPTURE AC Timing .............................................................................................. 28 Table 22. JTAG AC Timing ...................................................................................................... 29 Table 23. Pin List ..................................................................................................................... 35 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 List of Figures Figure 1. Typical Application Block Diagram Using IRMCF188 ................................................................................ 5 Figure 2. Pinout of IRMCF188 ................................................................................................................................... 6 Figure 3. IRMCF188 Block Diagram.......................................................................................................................... 7 Figure 4. IRMCF188 Leg Shunt Connection Diagram............................................................................................... 9 Figure 5. IRMCF188 Single Shunt Connection Diagram......................................................................................... 10 Figure 6. Crystal circuit example ............................................................................................................................. 18 Figure 7. Voltage droop and S/H hold time ............................................................................................................. 19 Figure 8 Op amp output capacitor ........................................................................................................................... 20 Figure 9. SYNC timing ............................................................................................................................................. 21 Figure 10. Gatekill timing ......................................................................................................................................... 22 Figure 11. ITRIP timing ............................................................................................................................................ 22 Figure 12. Interrupt timing ....................................................................................................................................... 23 2 Figure 13. I C Timing ............................................................................................................................................... 24 Figure 14. SPI write timing ...................................................................................................................................... 25 Figure 15. SPI read timing ....................................................................................................................................... 26 Figure 16. UART timing ........................................................................................................................................... 27 Figure 17. CAPTURE timing .................................................................................................................................... 28 Figure 18. JTAG timing ............................................................................................................................................ 29 Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output............................................................ 30 Figure 20. All digital I/O except motor PWM output ................................................................................................ 30 Figure 21. RESET, GATEKILL I/O .......................................................................................................................... 31 Figure 22. Analog input ........................................................................................................................................... 31 Figure 23. ADCL pin input structure ........................................................................................................................ 31 Figure 24 Analog operational amplifier output and AREF I/O structure ................................................................. 32 Figure 25. VSS,AVSS pin I/O structure ................................................................................................................... 32 Figure 26. VDD1,VDDCAP pin I/O structure ........................................................................................................... 32 Figure 27. XTAL0/XTAL1 pins structure .................................................................................................................. 33 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 1 Overview IRMCF188 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverterized appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCF188 provides a built-in closed loop sensorless control algorithm using the unique Flexible Motion Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF188 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC, while still supporting leg shunt current sensing. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging. Figure 1 shows a typical application schematic using the IRMCF188 in leg shunt mode. IRMCF188 contains 64K bytes of Flash program memory and comes in a 64-pin QFP package. Host communication Appliance Inverter With PFC Galvanic isolation PFC gate drive Passive EMI Filter IRS2630D Motor (PMSM or IM) IRMCF188 Power Supply 3.3V UART interface to Front Panel Digial I/O Analog Input 2 22 6 Figure 1. Typical Application Block Diagram Using IRMCF188 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 PWMUH P1.5 PFCPWM PFCGKILL GATEKILL P3.0/CS1 TMS/P5.2 TDO/P5.3 TDI/P5.1 TCK RESET P1.1/RXD P1.2/TXD T3.4/T0 T3.5/T1 P3.3/INT1 2 Pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 XTAL0 1 48 PWMVH XTAL1 2 47 P2.1 P1.0/T2 3 46 P3.7 SCL/SDI-SDO 4 45 PWMWH SDA/CS0 5 44 PWMUL P1.3/SYNC/SCK 6 43 PWMVL P1.4/CAP 7 42 PWMWL P1.6 8 41 P3.1/AOPWM2 P1.7 9 40 VSS VDD1 10 39 VDD1 VSS 11 38 VDDCAP VDDCAP 12 37 AVSS P2.0/NMI 13 36 OP3O P3.2/INT0 14 35 OP3+ P2.2 15 34 OP3- P2.3 16 33 ADCL IRMCF188 (Top View) AREF CMEXT OP2O OP2+ OP2- ADCH AIN4 AIN3 AIN2 AIN1 VDCBUS OP1+ OP1- OP1O P2.7/AOPWM1 P2.6/AOPWM0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 2. Pinout of IRMCF188 6 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 3 IRMCF188 Block Diagram and Main Functions IRMCF188 block diagram for leg shunt mode is shown in Figure 3. Speed command Mini- Motion Control Engine ( MiniMCE) D/A ( PWM) Capture Timer Counnter0,1,2 I2C 8bit CPU Core PORT1 PORT2 Digital I/Os Local RAM 2 kbyte PORT3 Ceramic Resonator (4MHz) 4 Motion Control Modules Interrupt Control 8 bit ( 8051) microcontroller Emulator Debugger GATEKILL To IGBT gate drive GATEKILL RCV SCL SDA To IGBT gate drive PFC PWM Program Flash 64kB 8bit uP Address/data bus SND Host Interface Watchdog Timer UART 6 Low Loss SVPWM Dual Port RAM 2 kbyte MCE Program RAM 12kbyte Motor Current Reconstruct OP2 3 OP3 3 PFC Current Sense Motion Control Bus 2 Monitoring OP1 3 VDCBUS Analog Input AIN1 AIN2 S/H A/D MUX AIN3 AIN4 ADCH ADCL JTAG Motion Control Sequencer 2 Freq Synthesizer 30MHz 120MHz Figure 3. IRMCF188 Block Diagram IRMCF188 contains the following functions for sensorless AC motor control applications: Motion Control Engine (MCETM) • Sensorless FOC (complete sensorless field oriented control) • Proportional plus Integral block • Low pass filter • Differentiator and lag (high pass filter) • Ramp • Limit • Angle estimate (sensorless control) • Inverse Clark transformation • Vector rotator • Bit latch • Peak detect • Transition • Multiply-divide (signed and unsigned) • Adder 7 www.irf.com 8051 microcontroller • Two 16 bit timer/counters • One 16 bit periodic timer • One 16 bit watchdog timer • One 16 bit capture timer • Up to 24 discrete digital I/Os • Ten-channel 12 bit A/D o Buffered (current sensing) three channels (0 – 1.2V input) o Unbuffered seven channels (0 – 1.2V input) • JTAG port (4 pins) • Up to three channels of analog output (8 bit PWM) • UART • I2C/SPI port © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 • • • • • • • • • Divide (signed and unsigned) Subtractor Comparator Counter Accumulator Switch Shift ATAN (arc tangent) Function block (any curve fitting, nonlinear function) 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) MCETM program memory and dual port RAM (6K byte) MCETM control sequencer • • • 8 www.irf.com • • 64K byte Flash memory 2K byte data RAM © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 4 Application connection and Pin function Figure 4 shows the application connections in leg shunt mode. Figure 5 shows the application connections in single shunt mode. AC 230V System Clock XTAL0 4 MHz Crystal XTAL1 Host Microcontroller (RS232C) P1.2/ TXD P1.1/ RXD Frequency Synthesizer PWMUH System clock PWMUL Low Loss Space Vector PWM Motion Control Modules RS232C PWMVH PWMVL PWMWH PWMWL GATEKILL PFCPWM SDA SCL Other Communication (I2 C) PFC GATEKILL I2 C/SPI Dual Port Memory (2kB) & MCE Memory (12kB) P1.0/T2 P1.3/SYNC P1.4/CAP P1.5 P1.6 PORT1 P1.7 P2.0/ NMI P2.1 P2.2 P2.3 Digital I/O Control Motor Current Reconstruct Motion Control Sequencer PFC shunt resistor VDCBUS 0.2V VAC+ AIN1 PORT2 From AC Voltage VACVACO 0.6V P3.0/INT2 P3.3 P3.4 PORT3 S/H Timers OP2- P3.5 Watchdog Timer PWM0 Local RAM (2 kByte) P2.7/ AOPWM1 PWM1 Analog Output P3.1/ AOPWM2 12-bit A/D & MUX TDO RESET OP3O 0.2V OP1+ OP1- - From PFC shunt OP1O Program Flash (64 kByte) JTAG Interface 3 AIN2 – AIN4 Other analog input (0 – 1,2V) 2 ADCH, ADCL A/D Calibration Reference Voltages AREF Optional External Voltage Reference (0.6V) CMEXT RESET Motor AVDD System Reset AVSS 8051 CPU VDD1 VSS Motor shunt resistors OP3- - T CLK TDI TSM 0.6V OP3+ S/H PWM2 3.3V - OP2O P2.6/ AOPWM0 JTAG Control ( OTP programming & Emulation) HVIC Gate Drive IRS2336D OP2+ P3.2/ INT0 IRMCF188 3.3V 1.8V Voltage Regulator VDDCAP 1.8V Figure 4. IRMCF188 Leg Shunt Connection Diagram 9 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 AC 230V System Clock XTAL0 4 MHz Crystal XTAL1 Host Microcontroller (RS232C) Frequency Synthesizer P1.2/ TXD PWMUH System clock PWMUL Motion Control Modules RS232C P1.1/ RXD Low Loss Space Vector PWM PWMVH PWMVL PWMWH PWMWL GATEKILL PFCPWM PFC GATEKILL SDA SCL Other Communication (I2 C) I2 C/SPI Dual Port Memory (2kB) & MCE Memory (12kB) 3.3V P1.0/T2 P1.3/SYNC P1.4/CAP PORT1 P1.5 P1.6 P1.7 P2.0/ NMI P2.1 P2.2 P2.3 Digital I/O Control Motor Current Reconstruct Motion Control Sequencer VDCBUS PORT2 OP2+ P3.3 P3.4 PORT3 S/H Timers HVIC Gate Drive IRS2336D OP2- P3.5 OP2O Watchdog Timer P2.6/ AOPWM0 PWM0 Local RAM (2 kByte) P2.7/ AOPWM1 PWM1 Analog Output P3.1/ AOPWM2 0.2V OP3+ 12-bit A/D & MUX S/H OP3O OP1+ TDO RESET From AC Voltage OP1O Program Flash (64 kByte) JTAG Interface 4 AIN1 – AIN4 Other analog input (0 – 1,2V) 2 ADCH, ADCL A/D Calibration Reference Voltages AREF Optional External Voltage Reference (0.6V) CMEXT RESET Motor AVDD System Reset AVSS 8051 CPU VDD1 VSS 0.6V OP1- T CLK TDI TSM From PFC shunt OP3- PWM2 3.3V Motor shunt resistor 0.6V P3.0/INT2 P3.2/ INT0 JTAG Control ( OTP programming & Emulation) PFC shunt resistor IRMCF188 3.3V 1.8V Voltage Regulator VDDCAP 1.8V Figure 5. IRMCF188 Single Shunt Connection Diagram 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD P1.1/RXD Output, Transmit data from IRMCF188 Input, Receive data to IRMCF188 Discrete I/O Interface P1.0/T2 P1.1/RXD P1.2/TXD P1.3/SYNC/SCK P1.4/CAP P1.5 P1.6 P1.7 P2.0/NMI P2.2 P2.3 P2.6/AOPWM0 Input/output port 1.0, can be configured as Timer/Counter 2 input Input/output port 1.1, can be configured as RXD input Input/output port 1.2, can be configured as TXD output Input/output port 1.3, can be configured as SYNC output or SPI clock output Input/output port 1.4, can be configured as Capture Timer input Input/output port 1.5 Input/output port 1.6 Input/output port 1.6 Input/output port 2.0, can be configured as non-maskable interrupt input Input/output port 2.2 Input/output port 2.3 Input/output port 2.6, can be configured as AOPWM0 output 10 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 P2.7/AOPWM1 P3.0/INT2/CS1 P3.1/AOPWM2 P3.2/NINT0 P3.3/NINT1 P3.4/T0 P3.5/T1 P3.7 P5.1/TDI P5.2/TMS Input/output port 2.7, can be configured as AOPWM1 output Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 Input/output port 3.1, can be configured as AOPWM2 output Input/output port 3.2, can be configured as INT0 input Input/output port 3.3, can be configured as INT1 input Input/output port 3.4, can be configured as T0 input for counter mode Input/output port 3.5, can be configured as T1 input for counter mode Input/output port 3.7 Input port 5.1, configured as JTAG port by default Input port 5.2, configured as JTAG port by default Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency Crystal Interface XTAL0 XTAL1 Input, connected to crystal Output, connected to crystal Reset Interface RESET Input and Output, system reset, doesn’t require external RC time constant 2 I C Interface SCL/SO-SI SDA/CS0 Output, I2C clock output, or SPI data Input/output, I2C Data line or SPI chip select 0 I2C/SPI Interface SCL/SO-SI SDA/CS0 P1.3/SYNC/SCK P3.0/INT2/CS1 Output, I2C clock output, or SPI data Input/output, I2C data line or SPI chip select 0 Input/output port 1.3, can be configured as SYNC output or SPI clock output Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 4.2 Motion Peripheral Interface Group PWM PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL PFCPWM 11 www.irf.com Output, PWM phase U high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase U low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase V high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase V low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase W high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase W low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PFCPWM output signal, internally pulled up by 70kΩ, configured low true at a power up © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 Fault GATEKILL Input, upon assertion this negates all six PWM signals, active low, internally pulled up by 70kΩ Input, upon assertion, this negates PFCPWM signal, active low, internally pulled up by 70kΩ PFCGKILL 4.3 Analog Interface Group AVSS AREF CMEXT Analog power return, (analog internal 1.8V power is shared with VDDCAP) 0.6V buffered output Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected. OP1+ OP1OP1O Input, Operational amplifier positive input for application sensing Input, Operational amplifier negative input for application sensing Output, Operational amplifier output for application sensing OP2+ OP2OP2O Input, Operational amplifier positive input for application sensing Input, Operational amplifier negative input for application sensing Output, Operational amplifier output for application sensing OP3+ OP3OP3O Input, Operational amplifier positive input for application sensing Input, Operational amplifier negative input for application sensing Output, Operational amplifier output for application sensing VDCBUS AIN1 AIN2 AIN3 AIN4 ADCH Input, Analog input channel (0 – 1.2V), allocated for DC bus voltage input Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), internally biased to 0.6V, see Figure 23 for internal structure ADCL Analog Channel OP1 OP2 OP3 AIN1 4.4 Leg Shunt Mode Single Shunt Mode Pin number(s) PFC Current AC Voltage 19, 20, 21 Motor U Phase Current Motor Shunt Current 28, 29, 30 Motor V Phase Current PFC Current 34, 35, 36 AC Voltage 23 Unallocated Table 1. Analog channel sensing functions in Leg and Single Shunt Modes Power Interface Group VDD1 VDDCAP VSS 4.5 Digital power (3.3V) Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Note: The internal 1.8V supply is not designed to power any external circuits or devices. Only capacitors should be connected to this pin. Digital common Test Interface Group P5.2/TMS 12 www.irf.com JTAG test mode input or input digital port © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 TDO P5.1/TDI TCK 13 www.irf.com JTAG data output JTAG data input, or input digital port JTAG test clock © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol VDD1 VIA VID TA TS Parameter Supply Voltage Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Min Typ Max -0.3 V 3.6 V -0.3 V 1.98 V -0.3 V 6.0 V -40 ˚C 85 ˚C -65 ˚C 150 ˚C Table 2. Absolute Maximum Ratings Condition Respect to VSS Respect to AVSS Respect to VSS Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max SYSCLK System Clock 32 120 PD Power consumption 1001) Table 3. System Clock Frequency Unit MHz mW Note 1) The value is based on the condition of MCE clock=100MHz, 8051 clock 20MHz with a actual motor and PFC running by a typical MCE application program and 8051 code. 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 5.3 Digital I/O DC Characteristics Symbol VDD1 VIL VIH CIN IL IOL1(2) Parameter Supply Voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current IOH1(2) IOL2(3) IOH2(3) Min 3.0 V -0.3 V 2.0 V - Typ 3.3 V - Condition Recommended Recommended Recommended 8.9 mA 3.6 pF ±10 nA 13.2 mA Max 3.6 V 0.8 V 3.6 V ±1 μA 15.2 mA High level output current Low level output current 12.4 mA 24.8 mA 38 mA VOH = 2.4 V 17.9 mA 26.3 mA 33.4 mA VOL = 0.4 V High level output current 24.6 mA 49.5 mA 81 mA VOH = 2.4 V (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) (1) (1) (1) Table 4. Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins. 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 5.4 Analog I/O DC Characteristics - OP amps for application sensing (OP1+, OP1-, OP1O, OP2+, OP2-, OP2O, OP3+, OP3-, OP3O) CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ VOFFSET Input Offset Voltage VI Input Voltage Range 0V VOUTSW OP amp output 50 mV (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 kΩ resistor OP GAINCL CMRR ISRC ISNK Max 26 mV 1.2 V 1.2 V Condition VAVDD = 1.8 V Recommended VAVDD = 1.8 V 20 kΩ (1) Operating Close loop 80 db Gain Common Mode 80 db Rejection Ratio Op amp output source 1 mA current Op amp output sink 100 μA current Table 5. Analog I/O DC Characteristics Requested between IFBO and IFB(1) (1) VOUT = 0.6 V (1) VOUT = 0.6 V (1) Note: (1) Data guaranteed by design. 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 5.5 Under Voltage Lockout DC characteristics Unless specified, Ta = 25˚C. Symbol Parameter UVCC+ UVcc positive going Threshold UVCCUVcc negative going Threshold UVCCH UVcc Hysteresys Min 2.78 V Typ 3.04 V Max 3.23 V 2.78 V 2.97 V 3.23 V 73 mV Table 6. UVcc DC Characteristics Condition (1) (1) Note: (1) Data guaranteed by design. 5.6 Itrip comparator DC characteristics Unless specified, VDD1=3.3V, Ta = 25˚C. Symbol Parameter Min Typ Max Itrip+ Itrip positive going 1.22V Threshold ItripItrip negative going 1.10V Threshold ItripH Itrip Hysteresys 120mV Table 7. Itrip DC Characteristics 5.7 Condition VDD1 = 3.3 V VDD1 = 3.3 V CMEXT and AREF Characteristics CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VCM CMEXT voltage 495 mV 600 mV 700 mV VAREF Buffer Output Voltage 495 mV 600 mV 700 mV Load regulation (VDC-0.6) 1 mV ∆Vo PSRR Power Supply Rejection Ratio 75 db Table 8. CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design. 17 www.irf.com © 2014 International Rectifier Condition VVDD1 = 3.3 V VVDD1 = 3.3 V (1) (1) Submit Datasheet Feedback May 28, 2014 IRMCF188 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Crystal input frequency Internal clock frequency Sleep mode output frequency Short time jitter Duty cycle PLL lock time Min 3.2 MHz Typ 4 MHz Max 60 MHz Condition 32 MHz 50 MHz 128 MHz (1) FCLKIN ÷ 256 - - (1) (1) (see figure below) 200 psec 50 % 500 μsec Table 9. PLL AC Characteristics (1) (1) (1) Note: (1) Data guaranteed by design. XTAL0 XTAL1 R1=1MΩ R2=1KΩ Xtal C1=15PF C2=15PF Figure 6. Crystal circuit example 18 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Min - Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) Table 10 . A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 7. Voltage droop and S/H hold time 19 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 6.3 Op amp AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Min - Typ 10 V/μsec Max - - 108 Ω 400 ns - Condition VDD1 = 3.3 V, CL = 33 pF (1) (1) (2) VDD1 = 3.3 V, CL = 33 pF (1) Table 11 Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. (2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pF, see Figure 8. Here only Op-amp 1 is shown but all op amp outputs should be loaded with this capacitor value. IRMCF188 IC AVREF External components OP1+ OP1OP1O 47pF Figure 8 Op amp output capacitor 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 6.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 PWMUx,PWMVx,PWMWx Figure 9. SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twSYNC SYNC pulse width 32 tdSYNC1 SYNC to current feedback 100 conversion time tdSYNC2 SYNC to AIN0-4, ADCH, 200 ADCL analog input conversion time tdSYNC3 SYNC to PWM output delay 2 time Table 12. SYNC AC Characteristics Unit SYSCLK SYSCLK SYSCLK (1) SYSCLK Note: (1) AIN2 – AIN4, ADCH, ADCL channels are converted once every 5 SYNC events 21 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 6.5 GATEKILL to SVPWM AC Timing twGK GATEKILL tdGK PWMUx,PWMVx,PWMWx Figure 10. Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twGK GATEKILL pulse width 32 tdGK GATEKILL to PWM 100 output delay Table 13. GATEKILL to SVPWM AC Timing 6.6 Unit SYSCLK SYSCLK Itrip AC Timing Itrip tItrip PWMUH,PWMUL, PWMVH,PWMVH, PWMWH,PWMWL Figure 11. ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter tITRIP Itrip propagation delay 22 www.irf.com Min Typ Max 100(sysclk)+1.0usec Table 14. Itrip AC Timing © 2014 International Rectifier Unit SYSCLK+usec Submit Datasheet Feedback May 28, 2014 IRMCF188 6.7 Interrupt AC Timing twINT P3.2/INT0 P3.3/INT1 tdINT Internal Program Counter Internal Vector Fetch Figure 12. Interrupt timing Unless specified, Ta = 25˚C. Symbol Parameter twINT INT0, INT1 Interrupt Assertion Time tdINT INT0, INT1 latency 23 www.irf.com Min 4 Typ - Max - 4 Table 15. Interrupt AC Timing © 2014 International Rectifier Unit SYSCLK SYSCLK Submit Datasheet Feedback May 28, 2014 IRMCF188 6.8 I2C AC Timing TI2CLK TI2CLK SCL tI2ST1 tI2WSETUP tI2WHOLD tI2RSETUP tI2EN1 tI2RHOLD tI2ST2 tI2EN2 SDA Figure 13. I2C Timing Unless specified, Ta = 25˚C. Symbol Parameter TI2CLK I2C clock period tI2ST1 I2C SDA start time tI2ST2 I2C SCL start time tI2WSETUP I2C write setup time tI2WHOLD I2C write hold time tI2RSETUP I2C read setup time tI2RHOLD I2C read hold time Min Typ 10 0.25 0.25 0.25 0.25 I2C filter time(1) 1 2 Table 16. I C AC Timing Max 8192 - Unit SYSCLK TI2CLK TI2CLK TI2CLK TI2CLK SYSCLK SYSCLK Note: (1) I2C read setup time is determined by the programmable filter time applied to I2C communication. 24 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 6.9 SPI AC Timing 6.9.1.1 SPI Write AC timing TSPICLK P1.3/SYNC/SCK tWRDELAY SCL/SO-SI Bit7(MSB) tSPICLKHT tSPICLKLT Bit0(LSB) tCSDELAY tCSHOLD tCSHIGH SDA/CS0 P3.0/INT2/CS1 Figure 14. SPI write timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max TSPICLK SPI clock period 4 tSPICLKHT SPI clock high time 1/2 tSPICLKLT SPI clock low time 1/2 tCSDELAY CS to data delay time 10 tWRDELAY CLK falling edge to data 10 delay time tCSHIGH CS high time between two 1 consecutive byte transfer tCSHOLD CS hold time 1 Table 17. SPI Write AC Timing 25 www.irf.com © 2014 International Rectifier Unit SYSCLK TSPICLK TSPICLK nsec nsec TSPICLK TSPICLK Submit Datasheet Feedback May 28, 2014 IRMCF188 6.9.1.2 SPI Read AC Timing TSPICLK P1.3/SYNC/SCK tRDHOLD tSPICLKHT tSPICLKLT tRDSU SCL/SO-SI Bit7(MSB) Bit0(LSB) tCSRD tCSHIGH tCSHOLD SDA/CS0 P3.0/INT2/CS1 Figure 15. SPI read timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max TSPICLK SPI clock period 4 tSPICLKHT SPI clock high time 1/2 tSPICLKLT SPI clock low time 1/2 tCSRD CS to data delay time 10 tRDSU SPI read data setup time 10 tRDHOLD SPI read data hold time 10 tCSHIGH CS high time between two 1 consecutive byte transfer tCSHOLD CS hold time 1 Table 18. SPI Read AC Timing 26 www.irf.com © 2014 International Rectifier Unit SYSCLK TSPICLK TSPICLK nsec nsec nsec TSPICLK TSPICLK Submit Datasheet Feedback May 28, 2014 IRMCF188 6.10 UART AC Timing TBAUD TXD Data and Parity Bit Start Bit Stop Bit RXD TUARTFIL Figure 16. UART timing Unless specified, Ta = 25˚C. Symbol Parameter TBAUD Baud Rate Period TUARTFIL UART sampling filter period (1) Min - Typ 57600 1/16 Max - Unit bit/sec TBAUD Table 19. UART AC Timing Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. 27 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 6.11 CAPTURE Input AC Timing TCAPCLK tCAPHIGH P1.4/CAP tCAPLOW tCRDELAY CREV(H,L) Internal register tCLDELAY CLAST(H,L) Internal register tINTDELAY Interrupt Vector Fetch Interrupt Figure 17. CAPTURE timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ TCAPCLK CAPTURE input period 8 tCAPHIGH CAPTURE input high time 4 tCAPLOW CAPTURE input low time 4 tCRDELAY CAPTURE falling edge to capture register latch time tCLDELAY CAPTURE rising edge to capture register latch time tINTDELAY CAPTURE input interrupt latency time Table 20. CAPTURE AC Timing 28 www.irf.com © 2014 International Rectifier Max 4 Unit SYSCLK SYSCLK SYSCLK SYSCLK 4 SYSCLK 4 SYSCLK Submit Datasheet Feedback May 28, 2014 IRMCF188 6.12 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Figure 18. JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ TJCLK TCK Period tJHIGH TCK High Period 10 tJLOW TCK Low Period 10 tCO TCK to TDO propagation delay 0 time tJSETUP TDI/TMS setup time 4 tJHOLD TDI/TMS hold time 0 Table 21. JTAG AC Timing 29 www.irf.com © 2014 International Rectifier Max 50 5 Unit MHz nsec nsec nsec - nsec nsec Submit Datasheet Feedback May 28, 2014 IRMCF188 7 I/O Structure The following figure shows the PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL/PFCPWM) VDD1 (3.3V) Internal digital circuit High true logic 6.0V PIN 270 Ω 6.0V 58k Ω VSS Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH/PFCPWM output The following figure shows the digital I/O structure except the PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 20. All digital I/O except PWM output The following figure shows RESET and GATEKILL I/O structure. 30 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 VDD1 (3.3V) RESET GATEKILL circuit 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 21. RESET, GATEKILL I/O The following figure shows the analog input structure, except for ADCL. VDDCAP(1.8V) Analog input 6.0V PIN 1 Ω Analog Circuit 6.0V AVSS Figure 22. Analog input The following figure shows the ADCL input structure. VDDCAP(1.8V) VDD1 (3.3V) Analog input 6.0V PIN 37.8 kΩ 1 Ω Analog Circuit 6.0V 8.4 kΩ AVSS Figure 23. ADCL pin input structure The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. 31 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 VDDCAP(1.8V) Analog output 6.0V PIN Analog Circuit 6.0V AVSS Figure 24 Analog operational amplifier output and AREF I/O structure The following figure shows the VSS,AVSS pin I/O structure VDD1 AVDD PIN 6.0V Figure 25. VSS,AVSS pin I/O structure The following figure shows the VDD1,VDDCAP pin I/O structure PIN 6.0V VSS Figure 26. VDD1,VDDCAP pin I/O structure 32 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 The following figure shows the XTAL0 and XTAL1 pins structure VDDCAP(1.8V) 6.0V PIN 1 Ω 6.0V VSS Figure 27. XTAL0/XTAL1 pins structure 33 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 8 Pin List Pin Number 1 2 3 4 5 Pin Name XTAL0 XTAL1 P1.0/T2 SCL/SO-SI SDA/CS0 Internal Pullup /Pull-down Pin Type I O I/O I/O I/O 6 P1.3/SYNC/SCK I/O 7 8 9 10 11 12 13 P1.4/CAP P1.6 P1.7 VDD1 VSS VDDCAP P2.0/NMI I/O I/O 14 15 16 17 18 19 20 P3.2/INT0 P2.2 P2.3 P2.6/AOPWM0 P2.7/AOPWM1 OP1O OP1- I/O I/O I/O I/O I/O O I 21 OP1+ I 22 VDCBUS I 23 AIN1 I 24 AIN2 I 25 AIN3 I 26 AIN4 I 27 ADCH I 28 OP2- I 29 OP2+ I 30 31 OP2O CMEXT O O 32 AREF O 34 www.irf.com P P P I/O Description Crystal input Crystal output Discrete programmable I/O or Timer/Counter 2 input I2C clock output (open drain, need pull up) or SPI data I2C data (open drain, need pull up) or SPI Chip Select 0 Discrete programmable I/O or SYNC output or SPI clock output Discrete programmable I/O or Capture timer input Discrete programmable I/O Discrete programmable I/O 3.3V digital power Digital common Internal 1.8V output, Capacitor(s) to be connected Discrete programmable I/O or Non-maskable Interrupt input Discrete programmable I/O or Interrupt 0 input Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O or PWM 0 digital output Discrete programmable I/O or PWM 1 digital output Op amp output for application sensing, 0-1.2V range Op amp negative input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Op amp positive input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel (0 – 1.2V), allocated for DC bus voltage input, needs to be pulled down to AVSS if unused Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), needs to be pulled down to AVSS if unused Op amp negative input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Op amp positive input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Op amp output for application sensing, 0-1.2V range Unbuffered 0.6V output. Capacitor needs to be connected. Analog reference voltage output (0.6V) © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 Pin Number 33 Pin Name ADCL Internal Pullup /Pull-down Pin Type I 34 OP3- I 35 OP3+ I 36 37 38 39 40 41 42 OP3O AVSS VDDCAP VDD1 VSS P3.1/AOPWM2 PWMWL 43 PWMVL 44 PWMUL 45 PWMWH 46 47 48 P3.7 P2.1 PWMVH 49 PWMUH 50 51 52 53 P1.5 PFCPWM PFCGKILL GATEKILL 70 kΩ Pull up 70 kΩ Pull up I/O I/O I I 54 P3.0/INT2/CS1 70 kΩ Pull up I/O 55 56 57 58 59 60 61 62 63 64 P5.2/TMS TDO P5.1/TDI TCK RESET P1.1/RXD P1.2/TXD P3.4/T0 P3.5/T1 P3.3/INT1 O P P P P I/O O 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down O O O I/O I/O O 58 kΩ Pull down 58 kΩ Pull down O I O I I I I/O I/O I/O I/O I/O Description Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), internally biased to 0.6V, see Figure 23 for internal structure Op amp negative input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Op amp positive input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Op amp output for application sensing, 0-1.2V range Analog common Internal 1.8V output, Capacitor(s) to be connected 3.3V digital power Digital common Discrete programmable I/O or PWM 2 digital output PWM gate drive for phase W low side, configurable either high or low true. PWM gate drive for phase V low side, configurable either high or low true PWM gate drive for phase U low side, configurable either high or low true PWM gate drive for phase W high side, configurable either high or low true Discrete programmable I/O Discrete programmable I/O PWM gate drive for phase V high side, configurable either high or low true PWM gate drive for phase U high side, configurable either high or low true Discrete programmable I/O. PFC PWM gate drive , configurable either high or low PFCPWM shutdown input, active low input. PWM shutdown input, configurable digital filter, active low input. Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 JTAG test mode select or digital input port JTAG test data output JTAG test data input or digital input port JTAG test clock Reset, low true, Schmitt trigger input UART receiver input or Discrete programmable I/O UART transmitter output or Discrete programmable I/O Discrete programmable I/O or Timer/Counter 2 input Discrete programmable I/O or Timer/Counter 2 input Interrupt 1 input or Discrete I/O Table 22. Pin List 35 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 9 Package Dimensions 36 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 10 Part Marking Information IRMCF188 Part Number Date Code IR Logo YWWP XXXXXX Production Lot Pin 1 Indentifier 11 Qualification Information †† Qualification Level Moisture Sensitivity Level Industrial (per JEDEC JESD 47E) MSL3††† (per IPC/JEDEC J-STD-020C) Machine Model Class B (per JEDEC standard JESD22-A114D) Human Body Model Class 2 (per EIA/JEDEC standard EIA/JESD22-A115-A) ESD RoHS Compliant Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. Note: Test condition for Temperature Cycling test is -40C to 125C. 37 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCF188 Data and Specifications are subject to change without notice IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 38 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014