Datasheet - International Rectifier

Release Datasheet Rev. A
IRMCF171
High Performance Sensorless Motor Control IC
Description
IRMCF171 is a high performance flash memory based motion control IC designed primarily for appliance
applications. IRMCF171 is designed to achieve low cost yet high performance control solutions for advanced
inverterized appliance motor control. IRMCF171 contains two computation engines integrated into one monolithic
chip. One is the Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet or induction
motors; the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm
by connecting control elements using a graphic compiler. Key components of the complex sensorless control
algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique
analog/digital circuit and algorithm fully supports single or leg shunt current reconstruction. The MCE and 8051
microcontroller communicate via dual port RAM for signal monitoring and command input. An advanced graphic
compiler for the MCETM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAGbased emulator tools are supported for 8051 software development including a flash programmer. IRMCF171
comes in a 48 pin QFP package.
Features
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Product Summary
MCETM (Flexible Motion Control Engine) Dedicated computation engine for high efficiency
sinusoidal sensorless motor control
Built-in hardware peripheral for single or two shunt
current feedback reconstruction and analog
circuits
Supports induction machine and both interior and
surface permanent magnet motor sensorless
control
Loss minimization Space Vector PWM
Two-channel analog output (PWM)
Embedded 8-bit high speed microcontroller (8051)
for flexible I/O and man-machine control
JTAG programming port for emulation/debugger
Serial communication interface (UART)
I2C/SPI serial interface
Three general purpose timers/counters
Two special timers: periodic timer, capture timer
Watchdog timer with independent internal clock
Internal 64 Kbyte flash memory
5V tolerant I/O
3.3V single supply
Base Part Number
Package Type
Maximum clock input (fcrystal)
Maximum Internal clock (SYSCLK)
Maximum 8051 clock (8051CLK)
Sensorless control computation time
MCETM computation data range
8051 Program Flash
805/MCE Data RAM
MCE Program RAM
GateKill latency (digital filtered)
PWM carrier frequency
A/D input channels
A/D converter resolution
A/D converter conversion speed
Analog output (PWM) resolution
UART baud rate (typ)
Number of digital I/O (max)
Package (lead free)
Typical 3.3V operating current
Standard Pack
Form
Quantity
60 MHz
120MHz
30MHz
35 [email protected]
16 bit signed
52KB
4KB
12KB
2 μsec
20 bits/ SYSCLK
7
12 bits
2 μsec
8 bits
57.6K bps
14
QFP48
30mA
Orderable Part Number
IRMCF171
LQFP48
Tape and Reel
2000
IRMCF171TR
IRMCF171
LQFP48
Tray
2500
IRMCF171TY
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© 2013 International Rectifier
April 20, 2013
IRMCF171
Table of Contents
1 Overview ....................................................................................................................... 5
2 Pinout ........................................................................................................................... 6
3 IRMCF171 Block Diagram and Main Functions ............................................................ 7
4 Application connection and Pin function ....................................................................... 9
4.1 8051 Peripheral Interface Group.................................................................................. 10
4.2 Motion Peripheral Interface Group ............................................................................... 11
4.3 Analog Interface Group................................................................................................ 11
4.4 Power Interface Group................................................................................................. 12
4.5 Test Interface Group .................................................................................................... 12
5 DC Characteristics ...................................................................................................... 13
5.1 Absolute Maximum Ratings ......................................................................................... 13
5.2 System Clock Frequency and Power Consumption ..................................................... 13
5.3 Digital I/O DC Characteristics ...................................................................................... 14
5.4 PLL and Oscillator DC characteristics ......................................................................... 15
5.5 Analog I/O DC Characteristics ..................................................................................... 15
5.6 Under Voltage Lockout DC characteristics .................................................................. 16
5.7 Itrip comparator DC characteristics.............................................................................. 16
5.8 CMEXT and AREF Characteristics .............................................................................. 16
6 AC Characteristics ...................................................................................................... 17
6.1 Digital PLL AC Characteristics ..................................................................................... 17
6.2 Analog to Digital Converter AC Characteristics ........................................................... 18
6.3 Op amp AC Characteristics ......................................................................................... 19
6.4 SYNC to SVPWM and A/D Conversion AC Timing...................................................... 20
6.5 GATEKILL to SVPWM AC Timing ............................................................................... 21
6.6 Itrip AC Timing ............................................................................................................. 21
6.7 Interrupt AC Timing...................................................................................................... 22
6.8 I2C AC Timing .............................................................................................................. 23
6.9 SPI AC Timing ............................................................................................................. 24
SPI Write AC timing ........................................................................................................... 24
SPI Read AC Timing.......................................................................................................... 25
6.10 UART AC Timing ...................................................................................................... 26
6.11 CAPTURE Input AC Timing ...................................................................................... 27
6.12 JTAG AC Timing ....................................................................................................... 28
7 I/O Structure ............................................................................................................... 29
8 Pin List ........................................................................................................................ 32
9 Package Dimensions .................................................................................................. 34
10 Part Marking Information ............................................................................................ 35
11 Qualification Information† ........................................................................................... 35 2
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IRMCF171
List of Tables
Table 2. Absolute Maximum Ratings ....................................................................................... 13
Table 3. System Clock Frequency ........................................................................................... 13
Table 4. Digital I/O DC Characteristics .................................................................................... 14
Table 5 PLL DC Characteristics .............................................................................................. 15
Table 6. Analog I/O DC Characteristics ................................................................................... 15
Table 7. UVcc DC Characteristics ........................................................................................... 16
Table 8. Itrip DC Characteristics .............................................................................................. 16
Table 9. CMEXT and AREF DC Characteristics ...................................................................... 16
Table 10. PLL AC Characteristics ............................................................................................ 17
Table 11 . A/D Converter AC Characteristics .......................................................................... 18
Table 12 Current Sensing OP Amp AC Characteristics ........................................................... 19
Table 13. SYNC AC Characteristics ........................................................................................ 20
Table 14. GATEKILL to SVPWM AC Timing ........................................................................... 21
Table 15. Itrip AC Timing ......................................................................................................... 21
Table 16. Interrupt AC Timing.................................................................................................. 22
Table 17. I2C AC Timing .......................................................................................................... 23
Table 18. SPI Write AC Timing ................................................................................................ 24
Table 19. SPI Read AC Timing................................................................................................ 25
Table 20. UART AC Timing ..................................................................................................... 26
Table 21. CAPTURE AC Timing .............................................................................................. 27
Table 22. JTAG AC Timing ...................................................................................................... 28
Table 23. Pin List ..................................................................................................................... 33
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IRMCF171
List of Figures
Figure 1. Typical Application Block Diagram Using IRMCF171 ................................................. 5
Figure 2. Pinout of IRMCF171 ................................................................................................... 6
Figure 3. IRMCF171 Block Diagram .......................................................................................... 7
Figure 4. IRMCF171 Leg Shunt Connection Diagram ............................................................... 9
Figure 5. IRMCF171 Single Shunt Connection Diagram ......................................................... 10
Figure 6. Crystal circuit example ............................................................................................. 17
Figure 7. Voltage droop and S/H hold time .............................................................................. 18
Figure 8 Op amp output capacitor ........................................................................................... 19
Figure 9. SYNC timing ............................................................................................................. 20
Figure 10. Gatekill timing ......................................................................................................... 21
Figure 11. ITRIP timing ............................................................................................................ 21
Figure 12. Interrupt timing........................................................................................................ 22
Figure 13. I2C Timing ............................................................................................................... 23
Figure 14. SPI write timing....................................................................................................... 24
Figure 15. SPI read timing ....................................................................................................... 25
Figure 16. UART timing ........................................................................................................... 26
Figure 17. CAPTURE timing .................................................................................................... 27
Figure 18. JTAG timing ............................................................................................................ 28
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output ............................. 29
Figure 20. All digital I/O except motor PWM output ................................................................. 29
Figure 21. RESET, GATEKILL I/O ........................................................................................... 29
Figure 22. Analog input............................................................................................................ 30
Figure 24 Analog operational amplifier output and AREF I/O structure .................................. 30
Figure 25. VSS,AVSS pin I/O structure ................................................................................... 30
Figure 26. VDD1,VDDCAP pin I/O structure............................................................................ 31
Figure 27. XTAL0/XTAL1 pins structure .................................................................................. 31
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IRMCF171
1 Overview
IRMCF171 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip
solution for complete inverterized appliance motor control applications. Unlike a traditional microcontroller or
DSP, the IRMCF171 provides a built-in closed loop sensorless control algorithm using the unique flexible Motion
Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a
collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to
map internal signal nodes. IRMCF171 also employs a unique single shunt current reconstruction circuit in
addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct
shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler
integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host
communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller.
The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1
shows a typical application schematic using the IRMCF171.
IRMCF171 contains 64 Kbytes of Flash program memory. The IRMCK171 contains 32 Kbytes OTP memory and
is intended for high volume production purposes while the IRMCF171 is intended for flexible volume production.
Both the Flash and ROM versions come in a 48-pin QFP package with identical pin configuration to facilitate PC
board layout and transition to mass production.
Host
Communication
(RS232C)
Appliance PM
motor Drive
Galvanic
isolation
15V
Passive
EMI
Fillter
PM motor
IPM or SPM
Or
IM motor
Gate signal
IRMCF171
Power
Supply
IRS2336 D
3.3V
Optional
EEPROM
2
8
Digital I/O
6
Analog Input
Figure 1. Typical Application Block Diagram Using IRMCF171
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IRMCF171
PWMUH
P1.5
GATEKILL
P3.0/CS1
TMS/P5.2
TDO
TDI/P5.1
TCK
RESET
P1.1/RXD
P1.2/TXD
P3.3/INT1
2 Pinout
48 47 46 45 44 43 42 41 40 39 38 37
XTAL0
1
36
PWMVH
XTAL1
2
35
PWMWH
P1.0/T2
3
34
PWMUL
SCL/SO-SI
4
33
PWMVL
SDA/CS0
5
32
PWMWL
P1.3/SYNC/SCK
6
31
P3.1/AOPWM2
P1.4/CAP
7
30
VSS
VDD1
8
29
VDD1
9
28
VDDCAP
VDDCAP
10
27
AVSS
P2.0/NMI
11
26
AIN5O
P3.2/INT0
12
25
AIN5+
VSS
IRMCF171
(Top View)
AIN5-
AREF
CMEXT
IFBO
IFB+
IFB-
AIN4
AIN3
AIN2
AIN1
AIN0
P2.7/AOPWM1
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. Pinout of IRMCF171
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IRMCF171
3 IRMCF171 Block Diagram and Main Functions
IRMCF171 block diagram for leg shunt mode is shown in Figure 3.
Flexible Motion
Control Engine
(MCE)
D/A
(PWM)
Speed
command
Capture
Timer
Counnter 0,1,2
Watchdog
Timer
Program
FLASH
64 KB
UART
RCV
Host
Interface SCL
I2C
SDA
8bit
CPU
Core
PORT 1
PORT 2
Digital
I/Os
Local
RAM
2 KB
PORT 3
8bit (8051)
microcontroller
Emulator
Debugger
Ceramic
Resonator
(4MHz)
To IGBT
gate drive
GATEKILL
Single Shunt
Motor Current
Reconstruction
8bit uP Address/data bus
SND
6
Low Loss
SVPWM
Dual Port
RAM
2 KB
MCE
Program
RAM
12 KB
IFB
Motion
Control
Modules
3
AIN0
From
shunt
resistor
AIN1
A/D
MUX
S/H
Motion Control Bus
2
Monitoring
AIN2
analog
input
AIN3
AIN4
AIN5
3
Interrupt
Control
Motion Control
Sequencer
4
JTAG
2
Freq
Synthesizer
20MHz
120MHz
Figure 3. IRMCF171 Block Diagram
IRMCF171 contains the following functions for sensorless AC motor control applications:
Motion Control Engine (MCETM)
 Sensorless FOC (complete sensorless field
oriented control)
 Proportional plus Integral block
 Low pass filter
 Differentiator and lag (high pass filter)
 Ramp
 Limit
 Angle estimate (sensorless control)
 Inverse Clark transformation
 Vector rotator
 Bit latch
 Peak detect
 Transition
 Multiply-divide (signed and unsigned)
 Adder
 Divide (signed and unsigned)
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8051 microcontroller
 Two 16 bit timer/counters
 One 16 bit periodic timer
 One 16 bit watchdog timer
 One 16 bit capture timer
 Up to 14 discrete digital I/Os
 Seven-channel 12 bit A/D
o Buffered (current sensing) two
channels (0 – 1.2V input)
o Unbuffered five channels (0 – 1.2V
input)
 JTAG port (4 pins)
 Up to two channels of analog output (8 bit
PWM)
 UART
 I2C/SPI port
 2K byte data RAM
© 2013 International Rectifier
April 20, 2013
IRMCF171
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Subtractor
Comparator
Counter
Accumulator
Switch
Shift
ATAN (arc tangent)
Function block (any curve fitting, nonlinear
function)
16 bit wide Logic operations (AND, OR,
XOR, NOT, NEGATE)
MCETM program memory and dual port RAM
(6K byte)
MCETM control sequencer
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64K byte Flash memory
© 2013 International Rectifier
April 20, 2013
IRMCF171
4 Application connection and Pin function
Figure 4 shows the application connections in leg shunt mode. Figure 5 shows the application connections in
single shunt mode.
XTAL0
XTAL1
4MHz
Crystal
Host
Microcontroller
(RS232C)
P1.2/TXD
P1.1/ RXD
SDA/ CS0
SCL/SO-SI
Other Communication
(I2C)
3.3V
P1.0/T2
P1.3/ SYNC/SCK
P1.4/CAP
P1.5
Digital I/O
Control
P2.0/NMI
Frequency
Synthesizer
System
clock
Low Loss
Space
Vector
PWM
Motion
Control
Modules
RS232 C
I2C/SPI
Dual
Port
Memory
(2 KB)
&
MCE
Memory
(12 KB)
PORT1
Motion
Control
Sequencer
IFBC+
IFBC-
AV REF
IFBCO
PORT3
Timers
PWM1
AIN5+
AIN 5-
S/H
AIN5O
12bit
A/D
&
MUX
Local
RAM
(2 KB)
PWM1
Analog Output
P3.1/ AOPWM2
HVIC
Gate Drive
IRS2336 D
PORT2
Watchdog
Timer
P2.7/ AOPWM1
PWMVL
PWMWH
PWMWL
GATEKILL
Single
Shunt
Current
Sensing
S/H
P3.0/CS1
P3.2/INT0
P3.3/INT1
PWMUH
PWMUL
PWMVH
AV REF
System
Clock
Motor
5
AIN0 – AIN4
Analog inputs (0-1.2V)
AREF
CMEXT
TCK
JTAG Control
(Flash programming
& Emulation)
P5.1/ TDI
P5.2/TMS
TDO
RESET
Program
FLASH
(64 KB)
JTAG
Interface
VDD1
VSS
AVSS
AVDD
RESET
System
Reset
3. 3V
Optional External Voltage
Reference (0.6V)
8051
CPU
IRMCF171
3.3V
1.8V
Voltage
Regulator
VDDCAP
1. 8V
Figure 4. IRMCF171 Leg Shunt Connection Diagram
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IRMCF171
XTAL0
XTAL1
4MHz
Crystal
Host
Microcontroller
(RS232C)
Frequency
Synthesizer
P1.2/TXD
P1.1/ RXD
3.3V
I2C/SPI
P1.0/T2
P1.3/ SYNC/SCK
P1.4/ CAP
P1.5
Digital I/O
Control
Low Loss
Space
Vector
PWM
Motion
Control
Modules
RS232 C
SDA/ CS0
SCL/SO-SI
Other Communication
(I2C)
System
clock
Dual
Port
Memory
(2 KB)
&
MCE
Memory
(12 KB)
PORT1
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
Single
Shunt
Current
Sensing
Motion
Control
Sequencer
HVIC
Gate Drive
IRS2336 D
AV REF
System
Clock
PORT2
P2.0/NMI
IFBC+
S/H
P3.0/CS1
P3.2/INT0
P3.3/INT1
IFBC-
AV REF
IFBCO
PORT3
Timers
Analog Output
P3.1/ AOPWM2
12bit
A/D
&
MUX
Local
RAM
(2 KB)
PWM1
PWM2
Motor
5
AIN0 – AIN4
Analog inputs (0-1.2V)
AREF
CMEXT
TCK
JTAG Control
(Flash programming
& Emulation)
P5.1/ TDI
P5.2/TMS
TDO
RESET
Program
FLASH
(64 KB)
JTAG
Interface
VDD1
VSS
Optional External Voltage
Reference (0.6V)
AVSS
AVDD
RESET
System
Reset
3. 3V
Buffered Analog Input
AIN5O
Watchdog
Timer
P2.7/ AOPWM1
AIN5+
AIN 5-
S/H
8051
CPU
IRMCF171
3.3V
1.8V
Voltage
Regulator
VDDCAP
1. 8V
Figure 5. IRMCF171 Single Shunt Connection Diagram
4.1
8051 Peripheral Interface Group
UART Interface
P1.2/TXD
P1.1/RXD
Output, Transmit data from IRMCF171
Input, Receive data to IRMCF171
Discrete I/O Interface
P1.0/T2
P1.1/RXD
P1.2/TXD
P1.3/SYNC/SCK
P1.4/CAP
P1.5
P2.0/NMI
P2.7/AOPWM1
P3.0/INT2/CS1
P3.1/AOPWM2
P3.2/NINT0
P3.3/NINT1
P5.1/TDI
Input/output port 1.0, can be configured as Timer/Counter 2 input
Input/output port 1.1, can be configured as RXD input
Input/output port 1.2, can be configured as TXD output
Input/output port 1.3, can be configured as SYNC output or SPI clock output
Input/output port 1.4, can be configured as Capture Timer input
Input/output port 1.5
Input/output port 2.0, can be configured as non-maskable interrupt input
Input/output port 2.7, can be configured as AOPWM1 output
Input/output port 3.0, can be configured as INT2 input or SPI chip select 1
Input/output port 3.1, can be configured as AOPWM2 output
Input/output port 3.2, can be configured as INT0 input
Input/output port 3.3, can be configured as INT1 input
Input port 5.1, configured as JTAG port by default
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IRMCF171
P5.2/TMS
Input port 5.2, configured as JTAG port by default
Analog Output Interface
P2.7/AOPWM1
Input/output, can be configured as 8-bit PWM output 1 with programmable carrier
frequency
P3.1/AOPWM2
Input/output, can be configured as 8-bit PWM output 2 with programmable carrier
frequency
Crystal Interface
XTAL0
XTAL1
Input, connected to crystal
Output, connected to crystal
Reset Interface
RESET
Input and Output, system reset, doesn’t require external RC time constant
2
I C Interface
SCL/SO-SI
SDA/CS0
Output, I2C clock output, or SPI data
Input/output, I2C Data line or SPI chip select 0
I2C/SPI Interface
SCL/SO-SI
SDA/CS0
P1.3/SYNC/SCK
P3.0/INT2/CS1
Output, I2C clock output, or SPI data
Input/output, I2C data line or SPI chip select 0
Input/output port 1.3, can be configured as SYNC output or SPI clock output
Input/output port 3.0, can be configured as INT2 input or SPI chip select 1
4.2
Motion Peripheral Interface Group
PWM
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
PFCPWM
Fault
GATEKILL
4.3
Output, PWM phase U high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase U low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase V high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase V low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase W high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase W low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PFCPWM output signal, internally pulled up by 70kΩ, configured low true at a
power up
Input, upon assertion this negates all six PWM signals, active low, internally pulled up
by 70kΩ
Analog Interface Group
AVSS
AREF
CMEXT
Analog power return, (analog internal 1.8V power is shared with VDDCAP)
0.6V buffered output
Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected.
IFB+
Input, Operational amplifier positive input for shunt resistor current sensing
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IRMCF171
4.4
IFBIFBO
Input, Operational amplifier negative input for shunt resistor current sensing
Output, Operational amplifier output for shunt resistor current sensing
AIN0
AIN1
AIN2
AIN3
AIN4
Input, Analog input channel 0 (0 – 1.2 V), typically configured for DC bus voltage input
Input, Analog input channel 1 (0 – 1.2 V), needs to be pulled down to AVSS if unused
Input, Analog input channel 2 (0 – 1.2 V), needs to be pulled down to AVSS if unused
Input, Analog input channel 3 (0 – 1.2 V), needs to be pulled down to AVSS if unused
Input, Analog input channel 4 (0 – 1.2 V), needs to be pulled down to AVSS if unused
AIN5+
AIN5AIN5O
Input, Operational amplifier positive input for shunt resistor current sensing
Input, Operational amplifier negative input for shunt resistor current sensing
Output, Operational amplifier output for AIN5 output, there is a single sample/hold
circuit on the output
Power Interface Group
VDD1
VDDCAP
VSS
4.5
Digital power (3.3V)
Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad
internally
Note: The internal 1.8V supply is not designed to power any external circuits or
devices. Only capacitors should be connected to this pin.
Digital common
Test Interface Group
P5.2/TMS
TDO
P5.1/TDI
TCK
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JTAG test mode input or input digital port
JTAG data output
JTAG data input, or input digital port
JTAG test clock
© 2013 International Rectifier
April 20, 2013
IRMCF171
5 DC Characteristics
5.1
Absolute Maximum Ratings
Symbol
VDD1
VIA
VID
TA
TS
Parameter
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Min
Typ
Max
-0.3 V
3.6 V
-0.3 V
1.98 V
-0.3 V
6.0 V
-40 ˚C
85 ˚C
-65 ˚C
150 ˚C
Table 1. Absolute Maximum Ratings
Condition
Respect to VSS
Respect to AVSS
Respect to VSS
Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and function of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
5.2
System Clock Frequency and Power Consumption
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
SYSCLK
System Clock
32
120
PD
Power consumption
1001)
Table 2. System Clock Frequency
Unit
MHz
mW
Note 1) The value is based on the condition of MCE clock=120MHz, 8051 clock 30MHz with a actual motor
running by a typical MCE application program and 8051 code.
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IRMCF171
5.3
Digital I/O DC Characteristics
Symbol
VDD1
VIL
VIH
CIN
IL
IOL1(2)
IOH1
(2)
High level output
current
Low level output current
IOL2(3)
IOH2
Parameter
Supply Voltage
Input Low Voltage
Input High Voltage
Input capacitance
Input leakage current
Low level output current
(3)
High level output
current
Min
3.0 V
-0.3 V
2.0 V
-
Typ
3.3 V
-
8.9 mA
3.6 pF
±10 nA
13.2 mA
Max
3.6 V
0.8 V
3.6 V
±1 μA
15.2 mA
12.4 mA
24.8 mA
38 mA
17.9 mA
26.3 mA
33.4 mA
24.6 mA
49.5 mA
81 mA
Condition
Recommended
Recommended
Recommended
(1)
VO = 3.3 V or 0 V
VOL = 0.4 V
(1)
VOH
(1)
= 2.4 V
VOL = 0.4 V
(1)
VOH
(1)
= 2.4 V
Table 3. Digital I/O DC Characteristics
Note:
(1) Data guaranteed by design.
(2) Applied to SCL/SO-SI, SDA/CS0 pins.
(3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins.
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© 2013 International Rectifier
April 20, 2013
IRMCF171
5.4
PLL and Oscillator DC characteristics
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
VIL OSC
Oscillator (XTAL0,1)
0
0.2* VDDCAP
Input Low Voltage
VIH OSC
Oscillator (XTAL0,1)
0.8* VDDCAP
VDDCAP
Input High Voltage
Table 4 PLL DC Characteristics
5.5
Condition
VDDCAP = voltage at
VDDCAP pin
VDDCAP = voltage at
VDDCAP pin
Analog I/O DC Characteristics
- OP amps for current sensing (IFB+,IFB-,IFBO, AIN5+,AIN5-,AIN5O)
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
VOFFSET
Input Offset Voltage
VI
Input Voltage Range
0V
VOUTSW
OP amp output
50 mV
(1)
operating range
CIN
Input capacitance
3.6 pF
RFDBK
OP amp feedback
5 k
resistor
OP GAINCL
CMRR
ISRC
ISNK
Max
26 mV
1.2 V
1.2 V
Condition
VAVDD = 1.8 V
Recommended
VAVDD = 1.8 V
20 k
(1)
Operating Close loop
80 db
Gain
Common Mode
80 db
Rejection Ratio
Op amp output source
1 mA
current
Op amp output sink
100 μA
current
Table 5. Analog I/O DC Characteristics
Requested
between IFBO and
IFB-
(1)
(1)
VOUT = 0.6 V
(1)
VOUT = 0.6 V
(1)
Note:
(1) Data guaranteed by design.
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© 2013 International Rectifier
April 20, 2013
IRMCF171
5.6
Under Voltage Lockout DC characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
UVCC+
UVcc positive going
Threshold
UVCCUVcc negative going
Threshold
UVCCH
UVcc Hysteresys
Note:
(1) Data guaranteed by design.
5.7
Min
2.78 V
Typ
3.04 V
Max
3.23 V
2.78 V
2.97 V
3.23 V
73 mV
Table 6. UVcc DC Characteristics
(1)
Itrip comparator DC characteristics
Unless specified, VDD1=3.3V, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Itrip+
Itrip positive going
1.22V
Threshold
ItripItrip negative going
1.10V
Threshold
ItripH
Itrip Hysteresys
120mV
Table 7. Itrip DC Characteristics
5.8
Condition
(1)
Condition
VDD1 = 3.3 V
VDD1 = 3.3 V
CMEXT and AREF Characteristics
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
VCM
CMEXT voltage
495 mV
600 mV
700 mV
VAREF
Buffer Output Voltage
495 mV
600 mV
700 mV
Load regulation (VDC-0.6)
1 mV
Vo
PSRR
Power Supply Rejection Ratio
75 db
Table 8. CMEXT and AREF DC Characteristics
Note:
(1) Data guaranteed by design.
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© 2013 International Rectifier
Condition
VVDD1 = 3.3 V
VVDD1 = 3.3 V
(1)
(1)
April 20, 2013
IRMCF171
6 AC Characteristics
6.1
Digital PLL AC Characteristics
Symbol
FCLKIN
FPLL
FLWPW
JS
D
TLOCK
Parameter
Crystal input
frequency
Internal clock
frequency
Sleep mode output
frequency
Short time jitter
Duty cycle
PLL lock time
Min
3.2 MHz
Typ
4 MHz
Max
60 MHz
32 MHz
50 MHz
128 MHz
(1)
FCLKIN ÷ 256
-
-
(1)
(1)
Condition
(see figure below)
200 psec
50 %
500 μsec
Table 9. PLL AC Characteristics
(1)
(1)
(1)
Note:
(1) Data guaranteed by design.
R1 =1M
R2 =10
Xtal
C1 =15PF
C2=15PF
Figure 6. Crystal circuit example
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April 20, 2013
IRMCF171
6.2
Analog to Digital Converter AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
TCONV
Conversion time
THOLD
Sample/Hold maximum
hold time
Min
-
Typ
-
Max
2.05 μsec
10 μsec
(1)
Condition
Voltage droop ≤ 15
LSB
(see figure below)
Table 10 . A/D Converter AC Characteristics
Note:
(1) Data guaranteed by design.
Input Voltage
Voltage droop
S/H Voltage
tSAMPLE
THOLD
Figure 7. Voltage droop and S/H hold time
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April 20, 2013
IRMCF171
6.3
Op amp AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
OPSR
OP amp slew rate
OPIMP
TSET
OP input impedance
Settling time
Min
-
Typ
10 V/μsec
Max
-
-
108 Ω
400 ns
-
Condition
VDD1 = 3.3 V, CL
= 33 pF (1)
(1) (2)
VDD1 = 3.3 V, CL
= 33 pF (1)
Table 11 Current Sensing OP Amp AC Characteristics
Note:
(1) Data guaranteed by design.
(2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a
capacitor of 47pF, see Figure 8. Here only the single shunt current amplifier is shown but all op amp
outputs should be loaded with this capacitor value.
IRMCF171 IC
AVREF
External
components
IFB+
IFBIFBO
47pF
Figure 8 Op amp output capacitor
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© 2013 International Rectifier
April 20, 2013
IRMCF171
6.4
SYNC to SVPWM and A/D Conversion AC Timing
twSYNC
SYNC
tdSYNC1
IU,IV,IW
tdSYNC2
AINx
tdSYNC3
PWMUx,PWMVx,PWMWx
Figure 9. SYNC timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twSYNC
SYNC pulse width
32
tdSYNC1
SYNC to current feedback
100
conversion time
tdSYNC2
SYNC to AIN0-4, ADCH,
200
ADCL analog input
conversion time
tdSYNC3
SYNC to PWM output delay
2
time
Table 12. SYNC AC Characteristics
Unit
SYSCLK
SYSCLK
SYSCLK
(1)
SYSCLK
Note:
(1) AIN1 – AIN5 channels are converted once every 5 SYNC events
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© 2013 International Rectifier
April 20, 2013
IRMCF171
6.5
GATEKILL to SVPWM AC Timing
twGK
GATEKILL
tdGK
PWMUx,PWMVx,PWMWx
Figure 10. Gatekill timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twGK
GATEKILL pulse width
32
tdGK
GATEKILL to PWM
100
output delay
Table 13. GATEKILL to SVPWM AC Timing
6.6
Unit
SYSCLK
SYSCLK
Itrip AC Timing
Itrip
tItrip
PWMUH,PWMUL,
PWMVH,PWMVH,
PWMWH,PWMWL
Figure 11. ITRIP timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
tITRIP
Itrip propagation delay
21
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Min
Typ
Max
100(sysclk)+1.0usec
Table 14. Itrip AC Timing
© 2013 International Rectifier
Unit
SYSCLK+usec
April 20, 2013
IRMCF171
6.7
Interrupt AC Timing
twINT
P3.2/ INT0
P3.3/ INT1
tdI NT
Internal
Program
Counter
Internal Vector Fetch
Figure 12. Interrupt timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
twINT
INT0, INT1 Interrupt
Assertion Time
tdINT
INT0, INT1 latency
22
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Min
4
Typ
-
Max
-
4
Table 15. Interrupt AC Timing
Unit
SYSCLK
SYSCLK
© 2013 International Rectifier
April 20, 2013
IRMCF171
6.8
I2C AC Timing
TI2CLK
TI2CLK
SCL
tI 2ST1
t I2WSETUP
tI 2WHOLD
tI 2RSETUP
tI 2EN1
t I2RHOLD
t I2ST 2
tI 2EN2
SDA
Figure 13. I2C Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
TI2CLK
I2C clock period
tI2ST1
I2C SDA start time
tI2ST2
I2C SCL start time
tI2WSETUP
I2C write setup time
tI2WHOLD
I2C write hold time
tI2RSETUP
I2C read setup time
tI2RHOLD
I2C read hold time
Min
Typ
10
0.25
0.25
0.25
0.25
I2C filter time(1)
1
Table 16. I2C AC Timing
Max
8192
-
Unit
SYSCLK
TI2CLK
TI2CLK
TI2CLK
TI2CLK
SYSCLK
SYSCLK
Note:
(1) I2C read setup time is determined by the programmable filter time applied to I2C communication.
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© 2013 International Rectifier
April 20, 2013
IRMCF171
6.9
SPI AC Timing
SPI Write AC timing
TSPICLK
P1.3/SYNC /SCK
tWRDELAY
Bit7(MSB)
SCL/SO-SI
t SPICLKHT
tSPICLKLT
Bit0(LSB)
tCSDELAY
tCSHOLD
tCSHIGH
SDA/CS0
P3. 0/INT2/CS1
Figure 14. SPI write timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
TSPICLK
SPI clock period
4
tSPICLKHT
SPI clock high time
1/2
tSPICLKLT
SPI clock low time
1/2
tCSDELAY
CS to data delay time
10
tWRDELAY
CLK falling edge to data
10
delay time
tCSHIGH
CS high time between two
1
consecutive byte transfer
tCSHOLD
CS hold time
1
Table 17. SPI Write AC Timing
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Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
TSPICLK
TSPICLK
© 2013 International Rectifier
April 20, 2013
IRMCF171
SPI Read AC Timing
TSPICLK
P1.3/SYNC /SCK
tRDHOLD
t SPICLKHT
tSPICLKLT
t RDSU
Bit7(MSB)
SCL/SO-SI
Bit0(LSB)
t CSRD
tCSHOLD
tCSHIGH
SDA/CS0
P3.0/INT2/CS1
Figure 15. SPI read timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
TSPICLK
SPI clock period
4
tSPICLKHT
SPI clock high time
1/2
tSPICLKLT
SPI clock low time
1/2
tCSRD
CS to data delay time
10
tRDSU
SPI read data setup time
10
tRDHOLD
SPI read data hold time
10
tCSHIGH
CS high time between two
1
consecutive byte transfer
tCSHOLD
CS hold time
1
Table 18. SPI Read AC Timing
25
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Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
nsec
TSPICLK
TSPICLK
© 2013 International Rectifier
April 20, 2013
IRMCF171
6.10 UART AC Timing
TBAUD
TXD
Start Bit
Data and Parity Bit
Stop Bit
RXD
TUARTFIL
Figure 16. UART timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
TBAUD
Baud Rate Period
TUARTFIL
UART sampling filter
period (1)
Min
-
Typ
57600
1/16
Max
-
Unit
bit/sec
TBAUD
Table 19. UART AC Timing
Note:
(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If
three sampled values do not agree, then UART noise error is generated.
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© 2013 International Rectifier
April 20, 2013
IRMCF171
6.11 CAPTURE Input AC Timing
TCAPCLK
t CAPHIGH
P1. 4/CAP
tCAPLOW
t CRDELAY
CREV(H,L)
Internal
register
tCLDELAY
CLAST (H,L)
Internal
register
tINTDELAY
Interrupt
Vector Fetch
Interrupt
Figure 17. CAPTURE timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
TCAPCLK
CAPTURE input period
8
tCAPHIGH
CAPTURE input high time
4
tCAPLOW
CAPTURE input low time
4
tCRDELAY
CAPTURE falling edge to
capture register latch time
tCLDELAY
CAPTURE rising edge to
capture register latch time
tINTDELAY
CAPTURE input interrupt
latency time
Table 20. CAPTURE AC Timing
27
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Max
4
Unit
SYSCLK
SYSCLK
SYSCLK
SYSCLK
4
SYSCLK
4
SYSCLK
© 2013 International Rectifier
April 20, 2013
IRMCF171
6.12 JTAG AC Timing
TJCLK
TCK
tJ HIGH
tJ LOW
tCO
TDO
tJ SETUP
t J HOLD
TDI/TMS
Figure 18. JTAG timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
TJCLK
TCK Period
tJHIGH
TCK High Period
10
tJLOW
TCK Low Period
10
tCO
TCK to TDO propagation delay
0
time
tJSETUP
TDI/TMS setup time
4
tJHOLD
TDI/TMS hold time
0
Table 21. JTAG AC Timing
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Max
50
5
Unit
MHz
nsec
nsec
nsec
-
nsec
nsec
© 2013 International Rectifier
April 20, 2013
IRMCF171
7 I/O Structure
The following figure shows the motor PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL)
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output
The following figure shows the digital I/O structure except the motor PWM output
Figure 20. All digital I/O except motor PWM output
The following figure shows RESET and GATEKILL I/O structure.
VDD1
(3.3V)
RESET
GATEKILL
circuit
70k 
6.0V
PIN
270 
6.0V
VSS
Figure 21. RESET, GATEKILL I/O
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© 2013 International Rectifier
April 20, 2013
IRMCF171
The following figure shows the analog input structure.
VDDCAP(1.8V)
Analog input
6.0V
PIN
1 
Analog Circuit
6.0V
AVSS
Figure 22. Analog input
The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.
VDDCAP(1. 8V)
Analog output
6.0V
PIN
Analog Circuit
6.0V
AVSS
Figure 23 Analog operational amplifier output and AREF I/O structure
The following figure shows the VSS,AVSS pin I/O structure
VDD1
AVDD
PIN
6.0V
Figure 24. VSS,AVSS pin I/O structure
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April 20, 2013
IRMCF171
The following figure shows the VDD1,VDDCAP pin I/O structure
PIN
6.0V
VSS
Figure 25. VDD1,VDDCAP pin I/O structure
The following figure shows the XTAL0 and XTAL1 pins structure
VDDCAP(1.8V)
6.0V
PIN
1 
6.0V
VSS
Figure 26. XTAL0/XTAL1 pins structure
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© 2013 International Rectifier
April 20, 2013
IRMCF171
8 Pin List
Pin
Number
Pin Name
Internal
Pull-up
/Pull-down
Pin
Type
1
2
3
4
5
XTAL0
XTAL1
P1.0/T2
SCL/SO-SI
SDA/CS0
6
P1.3/SYNC/SCK
I/O
7
8
9
10
11
P1.4/CAP
VDD1
VSS
VDDCAP
P2.0/NMI
I/O
P
P
P
I/O
12
13
14
P3.2/INT0
P2.7/AOPWM1
AIN0
I/O
I/O
I
15
AIN1
I
16
AIN2
I
17
AIN3
I
18
AIN4
I
19
20
21
22
IFBIFB+
IFBO
CMEXT
I
I
O
O
23
24
AREF
AIN5-
O
I
25
AIN5+
I
26
27
28
29
30
31
32
AIN5O
AVSS
VDDCAP
VDD1
VSS
P3.1/AOPWM2
PWMWL
33
PWMVL
32
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58 kΩ Pull
down
58 kΩ Pull
down
I
O
I/O
I/O
I/O
O
P
P
P
P
I/O
O
O
Description
Crystal input
Crystal output
Discrete programmable I/O or Timer/Counter 2 input
I2C clock output (open drain, need pull up) or SPI data
I2C data (open drain, need pull up) or SPI Chip Select
0
Discrete programmable I/O or SYNC output or SPI
clock output
Discrete programmable I/O or Capture timer input
3.3V digital power
Digital common
Internal 1.8V output, Capacitor(s) to be connected
Discrete programmable I/O or Non-maskable Interrupt
input
Discrete programmable I/O or Interrupt 0 input
Discrete programmable I/O or PWM 1 digital output
Analog input channel 0, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 1, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 2, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 3, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 4, 0-1.2V range, needs to be
pulled down to AVSS if unused
Single shunt current sensing OP amp input (-)
Single shunt current sensing OP amp input (+)
Single shunt current sensing OP amp output
Unbuffered 0.6V output. Capacitor needs to be
connected.
Analog reference voltage output (0.6V)
Analog input channel 5, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 5, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog output 5, 0-1.2V range,
Analog common
Internal 1.8V output, Capacitor(s) to be connected
3.3V digital power
Digital common
Discrete programmable I/O or PWM 2 digital output
PWM gate drive for phase W low side, configurable
either high or low true.
PWM gate drive for phase V low side, configurable
either high or low true
© 2013 International Rectifier
April 20, 2013
IRMCF171
Pin
Number
Pin Name
Internal
Pull-up
/Pull-down
58 kΩ Pull
down
58 kΩ Pull
down
58 kΩ Pull
down
58 kΩ Pull
down
Pin
Type
34
PWMUL
O
35
PWMWH
36
PWMVH
37
PWMUH
38
39
P1.5
GATEKILL
70 kΩ Pull up
I/O
I
40
P3.0/INT2/CS1
70 kΩ Pull up
I/O
41
42
43
44
45
46
47
48
P5.2/TMS
TDO
P5.1/TDI
TCK
RESET
P1.1/RXD
P1.2/RXD
P3.3/INT1
O
O
O
I
O
I
I
I
I/O
I/O
I/O
Description
PWM gate drive for phase U low side, configurable
either high or low true
PWM gate drive for phase W high side, configurable
either high or low true
PWM gate drive for phase V high side, configurable
either high or low true
PWM gate drive for phase U high side, configurable
either high or low true
Discrete programmable I/O.
PWM shutdown input, configurable digital filter, active
low input.
Discrete programmable I/O or external interrupt 2 input
or SPI Chip Select 1
JTAG test mode input or input digital port
JTAG test data output
JTAG test data input or input digital port
JTAG test clock
Reset, low true, Schmitt trigger input
UART receiver input or Discrete programmable I/O
UART transmitter output or Discrete programmable I/O
Interrupt 1 input or Discrete I/O
Table 22. Pin List
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© 2013 International Rectifier
April 20, 2013
IRMCF171
9 Package Dimensions
34
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© 2013 International Rectifier
April 20, 2013
IRMCF171
10 Part Marking Information
IRMCF171
Part Number
IR Logo
Date Code
YWWP
XXXXXX
Production Lot
Pin 1
Indentifier
11 Qualification Information†
††
Qualification Level
Moisture Sensitivity Level
ESD
Industrial
(per JEDEC JESD 47E)
MSL3†††
(per IPC/JEDEC J-STD-020C)
Machine Model
Class B
(per JEDEC standard JESD22-A114D)
Human Body Model
Class 2
(per EIA/JEDEC standard EIA/JESD22-A115-A)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
Revision History
Rev A
(March 10, 2013)
35
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First Revision
© 2013 International Rectifier
April 20, 2013
IRMCF171
Data and Specifications are subject to change without notice
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
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April 20, 2013