60A Dual Integrated PowIRstage IR3548 FEATURES DESCRIPTION • Integrated Dual, Doubler or Quad mode Driver • 2 pairs of high and low side MOSFETs • Peak efficiency up to 94% at 1.2V • Variable gate drive, VDRV, from 4.25V to 12V to optimize system efficiency • 5V VCC and VDRV capability for sleep states where only 5V is available • Input voltage (VIN) range of 4.25V to 17V • Output current capability of 30A/phase • Switching frequency up to 1.5MHz • Ultra-low Rg MOSFET technology minimizes switching losses for optimized high frequency performance • Synchronous MOSFET with monolithic integrated Schottky diode reduces dead-time and diode reverse recovery losses • Low quiescent current (1uA typical) VR12.6/VR12.6+ notebook applications. for • Independent enable control for each phase • Support both industry standard 3.3V tri-state PWM and IR Active Tri-Level (ATL) PWM logic • Small 6mm x 8 mm x 0.9mm PQFN package • Lead-free RoHS compliant package APPLICATIONS • High frequency, low profile DC-DC converters • Voltage Regulators for CPUs, GPUs, and DDR memory arrays of servers, notebook. The IR3548 is a dual integrated PowIRstage® is a with 2 pairs of co-packed control and synchronous MOSFETs and an optimized dual phase driver. The package is optimized internally for PCB layout, heat transfer and package inductance. The integrated driver is capable of operating as a Dual driver (2 PWM controlling 2 phases), a Doubler driver (1 PWM controlling 2 phases) or a Quad driver (1 PWM controlling 4 phases in two IR3548s). Up to 1.5MHz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. Integrating two phases in one package while still providing superior efficiency and thermal performance, the IR3548 enables smallest size and lower solution cost. The lower quiescent current makes it suitable for next generation VR12.6/VR12.6+ notebook applications. The IR3548 uses IR’s latest generation of low voltage MOSFET technology characterized by ultra-low gate resistance (Rg) and charge (Qg) that result in minimized switching losses. The synchronous MOSFET optimizes conduction losses and features a monolithic integrated Schottky to significantly reduce dead-time and diode conduction and reverse recovery losses. The IR3548 is optimized specifically for CPU core power delivery in 12Vin applications like servers, certain notebooks, GPU and DR memory designs. ORDERING INFORMATION Base Part Number Package Type IR3548MTRPBF PQFN 6 mm x 8 mm 1 www.irf.com Standard Pack Form Quantity Tape and Reel 3000 © 2014 International Rectifier Orderable Part Number Submit Datasheet Feedback January 08, 2014 IR3548 PINOUT DIAGRAM VIN1 VIN1 PGND PGND GATEL1 SW1 VIN1 SW1 VIN1 SW1 VINDIV SW1 EN1 SW1 PWM1 SW1 VCC SW1 BOOT1 SW1 GATEL1 SW1 LGND SW1 PGND PGND VDRV SW2 GATEL2 SW2 BOOT2 SW2 PWM2 / PWMIO1 SW2 EN2 / PWMIO2 SW2 FUNCTION SW2 MODE SW2 VIN2 SW2 VIN2 SW2 VIN2 VIN2 GATEL2 PGND PGND SW2 Figure 1: IR3548 Top View 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 FUNCTIONAL BLOCK DIAGRAM BOOT1 GATEL1 GATEL1 VIN1 VIN1 VIN1 VIN1 8 7 1 45 2 48 49 35 SW1 VDRV 11 36 SW1 VDRV EN1 Q1 4 VCC or VDRV UVLO LGND VCC 37 SW1 Driver 38 SW1 39 SW1 or T > 150°C 6 40 SW1 41 SW1 VDRV EN1 4 PWM1 Q2 Power-on Reset (POR), 5 42 SW1 Driver 43 SW1 Reference, MODE MODE (PWM or IR ATL), 17 FUNCTION 16 PWM2 / PWMIO1 44 SW1 13 BOOT2 FUNCTION (Dual, Doubler, or Quad), 14 18 VIN2 19 VIN2 20 VIN2 and Q3 Driver Dead-time EN2 / 15 PWMIO2 21 VIN2 Driver 25 SW2 Control 26 SW2 27 SW2 VIN1 VINDIV 3 LGND 9 Q4 VDRV VIN1 14 28 SW2 29 SW2 Driver 30 SW2 31 SW2 32 SW2 IR3548 33 SW2 34 SW2 10 50 12 PGND PGND 23 22 46 47 PGND PGND PGND PGND GATEL2 GATEL2 24 Figure 2: Block Diagram TABLE 1: FUNCTION AND MODE PIN CONFIGURATION TABLE PIN 16 PIN 17 “FUNCTION” “MODE” 0 1 3 PWM Pin 4 Mode “EN1” Function DUAL IR ATL Loop 1 Functionality Pin 14 Function Pin 15 Function PWM2 EN2 1 1 DOUBLER IR ATL Loops 1 & 2 NA NA Float 1 QUAD Master IR ATL Loops 1 & 2 PWMIO1 (output) PWMIO2 (output) 0 0 DUAL Tri-State Loop 1 PWM2 EN2 1 0 DOUBLER Tri-State Loops 1 & 2 NA NA Float 0 QUAD Slave NA Loops 1 & 2 PWMIO1 (input) PWMIO2 (input) www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 TYPICAL APPLICATION IR3588 DTSEN CFLT CRCS 100pF RT 10kΩ VIN1 VIN2 VCC VCC TSEN 5V 3.3V CFLT 1uF C3V3 1uF CVCC 0.1uF IR3548 CIN2 47uF x4 VDRV RCSP CVDRV 1uF SVADDR_1 RCSM SW1 SV_CLK SV_DIO VRHOT_ICRIT# SM_DIO PWM1 PWM1 PSI#1 EN1 PWM2 PWM2 PSI#2 EN2 ISEN1 SM_CLK IRTN1 EN ISEN2 VSEN VRTN IRTN2 + CS1 CBOOT2 0.22uF BOOT2 SW2 RCS2 2.49kΩ GATEL2 GATEL2 LGND L2 150nH CCS2 0.22uF + CS2 - FUNCTION + CS2 - VOUT CCS1 0.22uF GATEL1 MODE + CS1 - RCS1 2.49kΩ GATEL1 VINDIV VINSEN SV_ALERT# L1 150nH COUT 470uF x3 ADDR_PROT VRDY CBOOT1 0.22uF BOOT1 VDRV LGND From / To System VIN CIN1 0.1uF x2 PGND Figure 3: High Density Two-Phase Voltage Regulator, Standard Tri-state PWM, Dual Driver Mode VCC VIN1 VIN2 VCC CVCC 0.1uF VDRV IR3548 VDRV VIN CIN1 0.1uF x2 BOOT1 CVDRV 1uF CBOOT1 0.22uF CIN2 47uF x4 L1 150nH VOUT1 SW1 Two singlephase PWM controllers GATEL1 PWM1 GATEL1 EN1 BOOT2 RCS1 2.49kΩ CBOOT2 0.22uF PWM2 EN2 + CS1 + CS2 - + VOUT1 SENSE VINDIV MODE FUNCTION LGND CCS1 0.22uF COUT1 470uF x3 + CS1 L2 150nH VOUT2 SW2 GATEL2 RCS2 2.49kΩ CCS2 0.22uF COUT2 470uF x3 GATEL2 PGND + CS2 - + VOUT2 SENSE Figure 4: IR3548 Two Single-Phase Voltage Regulators, Standard Tri-state PWM, Dual Driver Mode 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 VCC VDRV VIN VIN1 VCC CVCC 0.1uF CIN1 0.1uF x2 IR3548 VDRV BOOT1 CVDRV 1uF CBOOT1 0.22uF CIN2 47uF x4 L1 150nH VOUT SW1 Single- VINDIV GATEL1 PWM1 GATEL1 CCS1 0.22uF COUT1 470uF x3 + CS1 - EN1 phase PWM RCS1 2.49kΩ BOOT2 PWM2 + CS1 - controller EN2 SW2 MODE + VOUT SENSE - FUNCTION LGND GATEL2 GATEL2 PGND Figure 5: IR3548 Single-phase Voltage Regulator, Standard Tri-state PWM, Dual Driver Mode VCC VIN1 VIN2 VCC CVCC 0.1uF VDRV IR3548 VDRV VIN CIN1 0.1uF x2 BOOT1 CVDRV 1uF CBOOT1 0.22uF CIN2 47uF x4 L1 150nH VOUT SW1 Singlephase VINDIV GATEL1 PWM1 GATEL1 EN1 PWM controller BOOT2 RCS1 4.99kΩ CBOOT2 0.22uF PWM2 + CS12 + VOUT SENSE - EN2 VCC MODE FUNCTION LGND COUT1 470uF x3 L2 150nH SW2 GATEL2 RCS2 4.99kΩ CCS 0.22uF GATEL2 PGND + CS12 - Figure 6: IR3548 Two-Phase Voltage Regulator, Standard Tri-state PWM, Doubler Driver Mode 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1, 2, 48, 49 VIN1 High current input supply pins for Phase 1. Recommended operating range is 4.25V to 17V. Connect at least a 10uF 1206 ceramic capacitor and a 0.1uF 0402 ceramic capacitor. Place the capacitors as close as possible to VIN1 pins and PGND pins (46 and 47). The 0.1uF 0402 capacitor should be on the same side of the PCB as the IR3548. 3 VINDIV Output containing divided VIN1 analog information, (VIN1-LGND) / 14 with respect to LGND. The internal resistor divider is disconnected from VIN1 when EN1 is low. EN1 Phase 1 ENABLE input in Dual mode and Phases 1 & 2 ENABLE input in Doubler or Quad mode. Grounding this pin places Phase 1 in low quiescent mode as a Dual driver and sets both phases in low quiescent mode as a Doubler or Quad driver. The pin is also used to communicate VDRV UVLO, VCC UVLO or over temperature condition; EN1 is pulsed low under the fault. The pin must be driven high with a pullup resistor or grounded and should not be floated. 5 PWM1 The PWM1 is the control input for the first driver with either an IR ATL compatible signal or an industry standard Tri-State signal. Connect this pin to the PWM output of the controller. As a Dual driver, PWM1 controls gate drivers for Phase 1 (Q1 and Q2), and as a Doubler or Quad driver, PWM1 controls both phases (Q1 and Q2 as well as Q3 and Q4). 6 VCC Bias voltage for control logic. Connect this pin to a +5V bias supply. Place a high quality low ESR 0.1uF ceramic capacitor from this pin to the LGND pin. 7 BOOT1 Floating bootstrap supply pin for the gate drive of control MOSFET Q1. Connect the bootstrap capacitor between this pin and the SW1 pin. The bootstrap capacitor provides the charge to turn on the control MOSFET Q1. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. 8, 45 GATEL1 Gate connection of the Phase 1 synchronous MOSFET Q2. Use a short, wide and direct PCB trace to connect the two pins. 9 LGND Bias and reference ground. All control signals are referenced to this node. 10, 23, 24, 46, 47, 50 PGND High current power ground. Note all pins are internally connected in the package. Provide low resistance connections to the ground plane and respective output capacitors. 11 VDRV Connect this pin to a separate supply voltage between 4.25V and 12V to vary the drive voltage on both the control and synchronous MOSFETs. Place a high quality low ESR ceramic capacitor from this pin to PGND pin (10). 12, 22 GATEL2 Gate connection of the Phase 2 synchronous MOSFET Q4. Use a short, wide and direct PCB trace to connect the two pins. BOOT2 Floating bootstrap supply pin for the gate drive of control MOSFET Q3. Connect the bootstrap capacitor between this pin and the SW2 pin. The bootstrap capacitor provides the charge to turn on the control MOSFET Q3. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. PWM2 / PWMIO1 Dual function pin. It is PWM2 in Dual mode. The PWM2 is the control input for the second driver with either an IR ATL compatible signal or an industry standard Tri-State signal. Connect this pin to the PWM output of the controller. As a DUAL driver, PWM2 controls gate drivers for Phase 2. As a DOUBLER driver, the pin is un-used and is internally disconnected. As a QUAD driver, the pin becomes PWMIO1, a CMOS input or output depending on the configuration of the IR3548 as a slave or master repectively. Refer to Table 1 on page 3 for more details. 4 13 14 15 16 6 EN2 / PWMIO2 Dual function pin. It is Phase 2 ENABLE input as a Dual driver. The pin must be driven high or low in this mode and should not be floated. Grounding this pin places Phase 2 in low quiescent mode. As a DOUBLER driver, the pin is un-used and is internally disconnected. As a QUAD driver, the pin becomes PWMIO2, a CMOS input or output depending on the configuration of the IR3548 as a slave or master respectively. Refer to Table 1 on page 3 for more details. FUNCTION FUNCTION pin used to select between Dual, Doubler and Quad driver modes. Voltage lower than 0.8V sets Dual mode; voltage higher than 2.0V sets Doubler mode; Floating the pin (or between 1.2V and 1.6V) sets Quad mode. This pin in combination with the MODE pin also determines Master or Slave behavior in Quad mode. The pin status is sensed when EN1 is enabled or VCC UVLO is cleared. Refer to Table 1 on page 3 for more details. www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 PIN # PIN NAME PIN DESCRIPTION MODE PWM mode pin used to select either IR ATL input or industry tri-state PWM input. This pin in combination with the FUNCTION pin also determines Master or Slave behavior in Quad mode. Pin should be tied to LGND or VCC, and the pin status is sensed at EN1 enable or when VCC UVLO is cleared. Refer to Table 1 on page 3 for more details. 18-21 VIN2 High current input supply pins for Phase 2. Recommended operating range is 4.25V to 17V. Connect at least a 10uF 1206 ceramic capacitor and a 0.1uF 0402 ceramic capacitor. Place the capacitors as close as possible to VIN2 pins and PGND pins (23 and 24). The 0.1uF 0402 capacitor should be on the same side of the PCB as the IR3548. 25-34 SW2 High Current Switch Node for Phase 2 (Q3 and Q4). 35-44 SW1 High Current Switch Node for Phase 1 (Q1 and Q2). 17 7 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PIN Number PIN NAME VMAX VMIN ISOURCE ISINK 1, 2, 48, 49 VIN1 25V -0.3V 5A RMS 20A RMS 3 VINDIV VCC +0.3V -0.3V 1mA 1mA 4 EN1 VCC +0.3V -0.3V 1mA 50mA 5 PWM1 VCC +0.3V -0.3V 5mA 1mA 6 VCC 6.5V -0.3V NA 100mA 7 BOOT1 15V with respect to SW1, 35V with respect to PGND -0.3V with respect to SW1 1A for <100ns, 100mA DC 2A for <100ns, 100mA DC 8, 45 GATEL1 15V with respect to PGND -5V for <200ns, -0.3V DC with respect to PGND 2A for <100ns, 200mA DC 4A for <100ns, 200mA DC 9 LGND 0V 0V 50mA 1mA 10, 23, 24, 46, 47, 50 PGND 300mV -300mV 40A RMS 80A RMS 11 VDRV 13.2V -0.3V NA 200mA 2A for 100ns, 200mA DC 4A for <100ns, 200mA DC 12, 22 GATEL2 15V with respect to PGND -5V for <200ns, -0.3V DC with respect to PGND 13 BOOT2 15V with respect to SW2, 35V with respect to PGND -0.3V with respect to SW2 1A for <100ns, 100mA DC 2A for <100ns, 100mA DC 14 PWM2 / PWMIO1 VCC +0.3V -0.3V 10mA 10mA 15 EN2 / PWMIO2 VCC +0.3V -0.3V 10mA 10mA 16 FUNCTION VCC +0.3V -0.3V 5mA 1mA 17 MODE VCC +0.3V -0.3V 5mA 1mA 18-21 VIN2 25V -0.3V 5A RMS 20A RMS 50A RMS 25A RMS 50A RMS 25A RMS 25-34 SW2 25V 35-44 SW1 25V -8V for <200ns, -0.3V DC -8V for <200ns, -0.3V DC THERMAL INFORMATION Thermal Resistance, Junction to Top (θJC_TOP) 11.0 °C/W Thermal Resistance, Junction to PCB (Pin 47) (θJB) 1.7 °C/W Thermal Resistance (θJA) 18.4 °C/W 1 Maximum Operating Junction Temperature -40°C to 150°C Maximum Storage Temperature Range -65°C to 150°C ESD Rating HBM Class 1A JEDEC Standard MSL Rating 3 Reflow Temperature 260°C Note: 1. Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air. Refer to International Rectifier Application Note AN-994 for details. 8 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN PARAMETER MIN SYMBOL MAX UNIT Recommended VIN Range 4.25 VIN 17 V Recommended VCC 4.25 VCC 5.5 V Recommended VDRV 4.25 VDRV 12 V Recommended Switching Frequency 200 ƒSW 1500 kHz Recommended Operating Junction Temperature -40 TJ 125 °C ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Efficiency PowIRstage® Peak Efficiency η Note 2 93.8 % Bootstrap PFET Forward Voltage VFWD_PFET I(BOOST) = 35mA 450 595 950 mV Thermal Flag Rising Threshold TRISE Note 1 150 °C Falling Threshold TFALL Note 1 130 °C PWM Input, IR ATL Mode, Figure 8 PWM Input High Threshold VIH_ATL 0.95 1.04 1.12 V PWM Input Low Threshold VIL_ATL 0.75 0.84 0.93 V PWM Tri-level High Threshold VTH_ATL 2.41 2.65 2.79 V PWM Tri-level Low Threshold VTL_ATL 2.21 2.45 2.56 V PWM Input Current Low IL_ATL VPWM = 0V -130 -100 -65 uA PWM Input Current Mid IM_ATL VPWM = 1.8V -840 -600 -360 uA PWM Input Current High IH_ATL VPWM = 2.7V -1.4 -1.0 -0.6 mA Minimum Recognized PWM Pulse Width MinPWM Note 1 50 ns PWM Input, Tri-State Mode (+3.3V or +5V signal level), Figure 7 PWM Input Rising Threshold VIH_PWM 2.41 2.65 2.79 V PWM Input Falling Threshold VIL_PWM 0.75 0.84 0.93 V Tri-State LO_GATE Threshold VTL_PWM 0.95 1.04 1.12 Tri-State LO_GATE Hysteresis VTLH_PWM Tri-State HI_GATE Threshold VTH_PWM Tri-State HI_GATE Hysteresis VTHH_PWM Tri-State Hold Off Time TTHold_PWM PWM Input Pull-Up Voltage PWM Input Resistance Minimum Recognized PWM Pulse Width 9 www.irf.com 200 2.21 Note 1 2.45 V mV 2.56 V 200 mV 80 ns VIT_PWM PWM Input Floating 1.40 1.60 1.80 V RPWM PWM Input Floating 3.00 3.75 4.50 kΩ TPWM_MIN © 2014 International Rectifier Note 1 30 Submit Datasheet Feedback ns January 08, 2014 IR3548 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT 13 14 15 V/V 1 µA VINDIV Divider Ratio VINDIV Disable VIN Bias IVIN_OFF VINDIV Input Resistance RVINDIV VINDIV / VIN kΩ 540 Enable Inputs (EN1, EN2) Enable1 Delay TD_EN1 Enable2 Delay TD_EN2 Input High Voltage VIH_EN Input Low Voltage VIL_EN Input Resistance REN EN1 Fault Pull Down Resistance REN_Pull_Down Power-on delay 10 µs Power-on delay 1 µs No UVLO or Over Temperature Fault @ 5V 1.15 2.00 2.70 V 0.54 0.80 1.20 V 450 500 550 kΩ 100 ohm Note 1 FUNCTION and MODE Input High Voltage VIH_FUNC_MODE Input Low Voltage VIL_FUNC_MODE Maximum Float Pin Capacitance CFUNC_MODE_MAX 2 V Note 1 0.8 V 20 pF PWMIO Input High Voltage 2 VIH_PWMIO V 0.8 V Input Low Voltage VIL_PWMIO Output High Voltage VOH_PWMIO 2.5 5 V Output Low Voltage VOL_PWMIO 0 0.5 V Supply Supply Bias Current Off IVCC_OFF + IVDRV_OFF VDRV Supply Bias Current IVDRV VCC Supply Bias Current EN1=0V 1 5 uA fPWM = 400kHz, VDRV=5V 30 40 mA IVCC_ATL ATL PWM Mode 0.865 2 mA IVCC_PWM Tri-state PWM Mode 1.13 2 mA 4.20 V VCC Rising Threshold for POR VCC_Rise 3.85 VCC Falling Threshold for POR VCC_Fall 3.35 VDRV Rising Threshold for POR VDRV_Rise 3.7 VDRV Falling Threshold for POR VDRV_Fall 3.28 V 4.20 V V Notes 1. Guaranteed by design but not tested in production 2. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, CIN=47uF x 4, COUT =470uF x3, no airflow, no heat sink, 25°C ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included. 10 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 TIMING DIAGRAMS Normal PWM Normal PWM VIH_PWM VIT_PWMI PWM Tri-state Tri-state VIL_PWM SW GATEL Figure 7: IR3548 Timing Diagram in Standard PWM Mode ATL Tri-state VTH_ATL VTL_ATL Normal PWM ATL Tri-state Normal PWM VIH_ATL VIL_ATL PWM SW GATEL ® Figure 8: IR3548 Timing Diagram in International Rectifier’s Active Tri-Level (ATL) PWM Mode 11 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 VCC VIN1 VIN2 VCC CVCC 0.1uF IR3548 CVDRV 1uF VDRV + CS2 - BOOT1 SW1 VINDIV PWM1 EN1 PWM2 EN2 PWM3 PWM1 EN1 EN2 MODE EN3 EN4 CIN2 47uF x2 GATEL1 GATEL1 BOOT2 CBOOT1 0.22uF SW1 RCS1 2.49kΩ L1 150nH CVCC 0.1uF IR3548 VIN CIN3 0.1uF x2 SW2 GATEL2 GATEL2 FUNCTION LGND VDRV SW1 VINDIV GATEL1 CBOOT2 0.22uF + CS1 L2 150nH SW2 RCS2 2.49kΩ CCS2 0.22uF PWM3 EN3 To PWM controller PWM4 EN4 PWM1 EN1 CIN4 47uF x2 + CS2 - PGND CBOOT3 0.22uF GATEL1 GATEL1 BOOT2 SW3 RCS3 2.49kΩ GATEL3 CBOOT4 0.22uF L3 150nH COUT 470uF x3 VOUT CCS3 0.22uF + CS3 L4 150nH PWM2 EN2 VCC MODE GATEL2 BOOT1 CVDRV 1uF CCS1 0.22uF PWM2 VCC PWM4 VIN1 VIN2 VCC CIN1 0.1uF x2 VDRV VDRV + CS1 - Fourphase PWM controller VCC SW2 GATEL2 GATEL2 FUNCTION LGND SW4 RCS4 2.49kΩ GATEL4 CCS4 0.22uF + CS4 - PGND + CS3 - + VOUT SENSE + CS4 PWM1 PWM2 PWM3 PWM4 SW1 GATEL1 SW2 GATEL2 SW3 GATEL3 SW4 GATEL4 Figure 9: Timing Diagram of the IR3548 Four-phase Voltage Regulator, IR ATL PWM, Dual Driver Mode 12 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 VCC VIN1 VIN2 VCC CVCC 0.1uF IR3548 VCC CIN2 47uF x2 VDRV BOOT1 CBOOT1 0.22uF CVDRV 1uF SW1 VINDIV PWM1 EN1 PWM controller PWM1 EN1 IR3548 GATEL1 GATEL1 BOOT2 VDRV L1 150nH VIN CIN3 0.1uF x2 SW1 SW1 RCS1 4.99kΩ VINDIV PWM2 GATEL1 CBOOT2 0.22uF EN2 EN2 + CS12 - MODE CIN4 47uF x2 L2 150nH CBOOT3 0.22uF To PWM controller EN2 PWM1 EN1 GATEL1 GATEL1 BOOT2 L3 150nH COUT 470uF x3 SW3 VOUT RCS3 4.99kΩ GATEL3 CBOOT4 0.22uF L4 150nH PWM2 SW2 GATEL2 GATEL2 FUNCTION LGND BOOT1 CVDRV 1uF PWM2 PWM2 VCC + VOUT SENSE CVCC 0.1uF VDRV VDRV Twophase VIN1 VIN2 VCC CIN1 0.1uF x2 SW2 RCS2 4.99kΩ CCS12 0.22uF EN2 VCC MODE SW2 GATEL2 GATEL2 GATEL2 FUNCTION PGND + CS12 - LGND SW4 RCS4 4.99kΩ CCS34 0.22uF GATEL4 PGND + CS34 - + CS34 PWM1 PWM2 SW1 GATEL1 SW2 GATEL2 SW3 GATEL3 SW4 GATEL4 Figure 10: Timing Diagram of the IR3548 Four-phase Voltage Regulator, IR ATL PWM, Doubler Driver Mode 13 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 VCC VIN1 VIN2 VCC CVCC 0.1uF IR3548 Master VDRV VDRV VCC CBOOT1 0.22uF CVDRV 1uF SW1 VINDIV PWM1 Singlephase PWM controller EN1 PWM1 EN1 CIN2 47uF x2 GATEL1 GATEL1 BOOT2 PWM2 / PWMIO1 SW2 EN2 / PWMIO2 GATEL2 MODE GATEL2 L1 150nH IR3548 Slave VDRV SW1 RCS1 10kΩ VINDIV GATEL1 CBOOT2 0.22uF SW2 RCS2 10kΩ BOOT1 PWM1 L2 150nH CCS12 0.22uF GATEL2 PGND VIN CIN3 0.1uF x2 CBOOT3 0.22uF CVDRV 1uF SW1 VCC FUNCTION LGND CVCC 0.1uF VDRV BOOT1 VIN1 VIN2 VCC CIN1 0.1uF x2 EN1 PWM2 / PWMIO1 GATEL1 GATEL1 BOOT2 SW2 EN2 / PWMIO2 GATEL2 MODE GATEL2 FUNCTION LGND CIN4 47uF x2 L3 150nH COUT 470uF x3 SW3 VOUT RCS3 10kΩ GATEL3 CBOOT4 0.22uF SW4 RCS4 10kΩ L4 150nH CCS1234 0.22uF GATEL4 PGND + + VOUT CS1234 SENSE + CS1234 - PWM1 SW1 GATEL1 SW2 GATEL2 SW3 GATEL3 SW4 GATEL4 Figure 11: Timing Diagram of the IR3548 Four-phase Vo ltage Regulator, IR ATL PWM, Quad Driver Mode 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 34, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), Two Phases, Dual Driver, PWM Mode, Vcc= 5V, VDRV=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7”(L) x 2.6”(W), no PWM controller loss, no inductor loss, unless specified otherwise. 95 94 93 92 91 Efficiency (%) 90 89 88 87 86 85 84 83 82 81 80 5 10 15 20 25 30 35 40 45 50 55 60 65 Figure 15: Normalized Power Loss vs. Output Voltage Output Current (A) Figure 12: Typical IR3548 Efficiency 9.9 1.40 8.8 10 1.35 7.7 9 1.30 6.6 1.25 5.5 1.20 4.4 1.15 3.3 1.10 2.2 1.05 1.1 1.00 0.0 0.95 -1.1 0.90 -2.2 Normalized Power Loss 1.45 8 Power Loss (W) 7 6 5 4 3 2 0.85 200 1 300 400 500 600 700 800 900 Case Temperature Adjustment (°C) 0 -3.3 1000 Switching Frequency (kHz) 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Figure 16: Normalized Power Loss vs. Switching Frequency Output Current (A) 1.10 2.2 1.05 1.1 1.00 0.0 0.95 -1.1 0.90 -2.2 0.85 -3.3 5 6 7 8 9 10 11 12 13 14 1.25 5.5 1.20 4.4 1.15 3.3 1.10 2.2 1.05 1.1 1.00 0.0 0.95 -1.1 0.90 -2.2 0.85 -3.3 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 Case Temperature Adjustment (°C) 3.3 Normalized Power Loss 1.15 Case Temperature Adjustment (°C) Normalized Power Loss Figure 13: Typical IR3548 Power Loss VDRV Voltage (V) 15 Input Voltage (V) Figure 17: Normalized Power Loss vs. VDRV Voltage 1.40 8.8 1.35 7.7 6.6 1.30 15 ower Loss 1.25 www.irf.com re Adjustment (°C) Figure 14: Normalized Power Loss vs. Input Voltage 5.5 © 2013 International Rectifier 1.20 4.4 1.15 3.3 1.10 2.2 Submit Datasheet Feedback January 08, 2014 IR3548 TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 34, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), Two Phases, Dual Driver, PWM Mode, Vcc= 5V, VDRV=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7”(L) x 2.6”(W), no PWM controller loss, no inductor loss, unless specified otherwise. 1.35 7.7 180 1.30 6.6 160 1.25 5.5 1.20 4.4 1.15 3.3 2.2 1.05 1.1 1.00 0.0 0.95 -1.1 0.90 -2.2 0.85 120 130 140 150 160 170 180 190 200 VDRV=7V, 2 Phases VDRV=5V, 2 Phases 140 VDRV Current (mA) 1.10 Case Temperature Adjustment (°C) Normalized Power Loss VDRV=12V, 2 Phases VDRV=12V, 1 Phase 120 VDRV=7V, 1 Phase 100 VDRV=5V, 1 Phase 80 60 40 20 -3.3 210 0 200 300 400 500 Output Inductor (nH) 600 700 800 900 1000 fsw (kHz) Figure 18 Normalized Power Loss vs. Output Inductor Figure 21 VDRV Current vs. Switching Frequency PWM1 5V/div PWM2 5V/div SW1 10V/div SW2 10V/div 1us/div Figure 22 Standard PWM Mode, Dual Driver, 0A Figure 19 Thermal Derating Curve 3.0 VCC Current (mA) PWM1 5V/div PWM Mode, 2 Phases 2.5 PWM Mode, 1 Phase PWM2 5V/div 2.0 1.5 SW1 10V/div 1.0 0.5 SW2 10V/div 0.0 200 300 400 500 600 700 800 900 1000 fsw (kHz) 1us/div Figure 20 VCC Current vs. Switching Frequency 16 www.irf.com © 2014 International Rectifier Figure 23 Standard PWM Mode, Dual Driver, 60A Submit Datasheet Feedback January 08, 2014 IR3548 TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 34, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), Two Phases, Dual Driver, PWM Mode, Vcc= 5V, VDRV=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7”(L) x 2.6”(W), no PWM controller loss, no inductor loss, unless specified otherwise. PWM1 2V/div PWM 2V/div SW1 10V/div SW2 10V/div 1us/div SW 5V/div 100ns/div Figure 24 Standard PWM Mode, Doubler Driver, 0A (Circuit of Figure 6) Figure 27 Tristate Delays in PWM Mode, 10A PWM 2V/div PWM 2V/div SW 5V/div SW 5V/div 40ns/div 40ns/div Figure 25 PWM to Switching Delay in PWM Mode, 10A PWM 2V/div PWM 2V/div SW 5V/div SW 5V/div 100ns/div Figure 26 Tristate Delays in PWM Mode, 10A 17 www.irf.com Figure 28 PWM to Switching Delays in IR ATL Mode, 10A (Circuit if Figure 9) © 2014 International Rectifier 100ns/div Figure 29 Tristate delays in IR ATL Mode, 10A (Circuit of Figure 9) Submit Datasheet Feedback January 08, 2014 IR3548 TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 34, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), Two Phases, Dual Driver, PWM Mode, Vcc= 5V, VDRV=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7”(L) x 2.6”(W), no PWM controller loss, no inductor loss, unless specified otherwise. EN 5V/div PWM 2V/div SW1 5V/div SW 5V/div 40ns/div Figure 30 Tristate delays in IR ATL Mode, 10A (Circuit of Figure 9) Figure 32 ENABLE Control, 0A 14.5 14.4 EN 5V/div 14.3 VINDIV Ratio 14.2 14.1 14.0 13.9 13.8 SW1 5V/div 13.7 13.6 13.5 4 6 8 10 12 14 16 Input Voltage (V) 2us/div Figure 31 ENABLE Control, 0A 18 www.irf.com © 2014 International Rectifier Figure 33 VINDIV to VIN Ratio Submit Datasheet Feedback January 08, 2014 IR3548 GENERAL DESCRIPTION The IR3548 contains two high-efficiency and highspeed MOSFET drivers optimized to drive two pairs of integrated control and synchronous N-channel MOSFETs up to 1.5MHz. The IR3548 accepts industry standard 3.3V tri-state PWM signal and is 5V compliant. It also works with International Rectifier’s controllers with Active TriLevel (ATL) PWM outputs. The patented IR ATL PWM allows complete enable and disable control of both MOSFET pairs through the PWM input signal from the controller. The IR3548 can be configured in three different operating driver modes, Dual driver, Doubler driver and Quad driver so that one PWM signal can control one-, two- or four-phase buck converter. The IR3548 provides two Enable inputs to control the two independent phases while operating in Dual driver mode, which reduces quiesecent current to 1 uA (typical). The IR3548 provides Vcc and VDRV Under Voltage Lockout (UVLO) and over temperature fault protection, which pulls low EN1 when the fault occurs. The wide range of the VDRV driver voltage from 4.25V to 12V makes it possible to optimize system efficiency for applications with different switching frequencies, input voltages, and output voltages. THEORY OF OPERATION POWER-ON RESET (POR) The IR3548 incorporates power-on reset protection. This ensures that both the high- and low-side output drivers are active only after the IR3548 supply voltage Vcc and VDRV both have exceeded a certain minimum operating threshold. The Vcc and VDRV supplies are monitored and both drivers are set to the low state, holding both external MOSFETs off. Once Vcc and VDRV cross the rising POR threshold and if the IR3548 is in IR ATL mode, the outputs are held in the OFF state until a transition from tri-state to active operation is detected at the PWM input. 19 www.irf.com © 2014 International Rectifier This startup configuration ensures that any undetermined PWM signal levels from a controller in pre-POR state will not result in control MOSFET or synchronous MOSFET turn on until the controller is out of its POR. For Tri-state PWM mode, the POR operation is the same except that the driver does not look for an input tri-state before functioning. During normal operation the drivers continue to remain active until Vcc or VDRV fall below their respective falling POR thresholds. STANDARD 3.3V TRI-STATE PWM MODE If MODE pin is grounded, the IR3548 accepts standard 3-level 3.3V PWM input signals. As shown in Figure 7, when PWM input is above VIH_PWM, the synchronous MOSFET is turned off and the control MOSFET is turned on. When PWM input is below VIL_PWM, the control MOSFET is turned off and synchronous MOSFET is turned on. If PWM pin is floated, the built-in resistors pull the PWM pin into a tri-state region centered around 1.6V. IR ACTIVE TRI-LEVEL (ATL) PWM INPUT SIGNAL When MODE pin is tied to VCC, the IR3548 gate drivers are driven by a patented tri-level PWM control signal provided by the IR digital PWM controllers. During normal operation, the rising and falling edges of the PWM signal transition between 0V and 1.8V to control pulse width modulation of the integrated MOSFETs. To force both MOSFETs off simultaneously, the PWM signal crosses a tri-state voltage level higher than the VTH_ATL tri-state threshold. This threshold based tri-state results in a very fast disable for both the MOSFET pairs with only a small tri-state propagation delay. MOSFET switching resumes when the PWM signal falls below the VTL_ATL tri-state threshold into the normal operating voltage range. Figures 8 shows the PWM input and the corresponding SW and GATEL output of the IR3548. This fast tri-state operation eliminates the need for any tri-state hold-off time of the PWM signal to dwell in the shutdown window. Dedicated disable or enable pins are not required which simplifies the routing and layout in applications with a limited number of board layers. It also provides the Submit Datasheet Feedback January 08, 2014 IR3548 switching free of shoot-through for slow PWM transition times of up to 20ns. The IR3548 is therefore tolerant of stray capacitance on the PWM signal lines. The IR3548 provides a pull-up bias current to drive the PWM input to the tri-state condition of 3.3V when the PWM controller output is in its high impedance state. Multi-level pull-up currents are designed to drive worst case stray capacitances and allows for PWM transitions into the tri-state condition rapidly to avoid a prolonged period of MOSFET conduction during faults. The pull-up currents are disabled once the PWM pin exceeds the tri-state threshold to conserve power. DUAL, DOUBLER OR QUAD DRIVER MODE SELECTION The FUNCTION pin is used to select three different operating driver modes, Dual driver, Doubler driver and Quad driver so that one PWM can control one-, two- or four-phase buck converter. As shown in Table 1, connecting FUNCTION to LGND sets Dual driver mode while tying FUNCTION pin to Vcc selects Doubler mode. Leaving FUNCTION pin float sets Quad driver mode. These phase modes are shown in Figures 3 to 6 and Figures 9 to 11. Detailed timing diagrams for IR ATL mode can be seen in Figures 9 to 11. In Dual driver mode, two independent PWM signals control two respective phases with separate ENABLE control. This mode is primarily used in a two-phase converter with a two-phase PWM controller, as shown in Figure 3 and Figure 9. It can also be used in single-phase operation as shown in Figure 5 or in converters with two independent output rails, as shown in Figure 4. In Doubler driver mode, a single input signal at PWM1 controls two phases, where Phase 1 follows PWM1 signal and Phase 2 is 180°phase behind the PWM1 signal. The current signal of the two phases should be summed and then connected to the PWM controller, as shown in Figure 6 and Figure 10. In Quad driver mode, two IR3548 devices are used with one configured as a Master and one as a Slave, as shown in Figure 11. One PWM signal at PWM1 controls four phases with the sequence of Phase 1 of the Master IR3548 , Phase 1 of the Slave IR3548, 20 www.irf.com © 2014 International Rectifier Phase 2 of Master IR3548, and Phase 2 of Slave IR3548. The phase delay is 90°between the phases. The current signal of the four phases should be summed and then connected to the PWM controller. ENABLE CONTROL There are two enable inputs in the IR3548, EN1 and EN2. In Dual Mode, each phase has its own enable input. Respective control and synchronous MOSFETs are held off while EN1 and EN2 are low. If only one phase operation is desired, the EN2 pin must be grounded. In Doubler and Quad modes, only EN1 is available. EN1 low places both phases in high impedance by turning off all four MOSFETs. Internal blocks are shut down to reduce VCC and VDRV quiescent currents to 1uA (typical) when both phases are turned off. The VIN1 input voltage sense resistor divider (VINDIV) is also disconnected when EN1 is low to further reduce bias currents. The IR3548 is ready to accept PWM activity in less than 10 us after the part is enabled via EN1, as shown in Figure 31. INTEGRATED BOOTSTRAP PFET The IR3548 features an integrated bootstrap PFET per phase to reduce external component count. This enables the IR3548 to be used effectively in cost and space sensitive designs. The bootstrap circuit is used to establish the control MOSFET gate driver bias voltage and consists of a PFET and an external capacitor connected between the SW and BOOT pins of each phase. The external bootstrap capacitor is charged through the PFET when the respective SW node is low. CONTROL MOSFET DRIVER Each control MOSFET driver is able to drive a Nchannel MOSFET at frequency up to 1.5MHz. The external bootstrap BOOT pin capacitor referenced to the SW node is used to bias the internal MOSFET gate. When the SW node is at ground, the bootstrap capacitor is charged to the VDRV supply voltage using the BOOT PFET and this stored charge is used to bias the internal MOSFET when the PWM signal goes high. Once the control MOSFET is Submit Datasheet Feedback January 08, 2014 IR3548 turned on, the SW voltage is driven to the VIN supply voltage and the BOOT pin voltage is equal to VIN plus the VDRV voltage without any bootstrap diode voltage drop. When the PWM signal goes low, the control MOSFET is turned off by pulling the gate to the SW voltage. SYNCHRONOUS MOSFET DRIVER The IR3548 synchronous MOSFET driver is designed to drive the internal N-channel MOSFET to frequencies of 1.5MHz. The driver is biased from the VDRV supply voltage to turn the MOSFET on. When the synchronous MOSFET is turned on the SW node is pulled to ground. This allows recharging of the bootstrap capacitor for the next synchronous MOSFET drive event. the control MOSFET is turned off before turning on the synchronous MOSFET. The PWM rising edge transition to a high voltage threshold initiates the turn off of the synchronous MOSFET after a small propagation delay. The adaptive dead time circuit provides the appropriate dead time by determining if the synchronous MOSFET gate voltage has crossed the lower threshold before allowing the turn on of the control MOSFET. INPUT VOLTAGE DIVIDER The VINDIV can be used to provide input voltage VIN1 information to the PWM controller with a ratio of 1/14 through an internal resistor divider, which is disconnected from VIN1 when EN1 is low to reduce the bias current of the IR3548. FREQUENCY RANGE ADAPTIVE DEAD TIME ADJUSTMENT In a synchronous buck converter care should be taken to prevent both control and synchronous MOSFETs from being on simultaneously. Such an event could result in very large shoot-through currents and lead to long term degradation of the power stage. A fixed dead time does not provide optimal performance due to variations in converter duty cycles, bias voltages and temperature. The IR3548 provides an adaptive dead time adjustment to minimize dead time to an optimum duration which allows for maximum efficiency. The ‘break before make’ adaptive design is achieved by monitoring gate and SW voltages to determine the ON or OFF status of a MOSFET. Adaptive dead time also provides zero-voltage switching (ZVS) of the synchronous MOSFET with minimum current conduction through its body diode. The IR3548 is designed to operate over a wide frequency range. When operating in Dual Mode, the PWM input and respective SW output frequencies are identical. When operating in Doubler mode, the PWM1 input frequency is twice the SW1 or SW2 output frequencies. When operating in Quad mode, the Master PWM1 input frequency is four times the four SW output frequencies. The lower limit of the output frequency range is dictated by the size of the BOOT capacitor which provides bias to the control MOSFET driver during the entire on-time. The upper limit of frequency is determined by thermal limitations as well as pulse width limitations. The IR3548 is designed to operate with switching frequencies of each phase between 200kHz and 1.5MHz. USING A DUAL MODE DRIVER AS A SINGLE During normal operation the PWM transitions between low and high voltage levels to drive the control and synchronous MOSFETs. The high voltage level is 1.8V for IR ATL mode and 3.3V for standard PWM mode. DRIVER The PWM signal falling edge transition to a low voltage threshold initiates the control MOSFET driver turn off after a short propagation delay. The dead time control circuit monitors the internal high gate signals and respective SW voltages to ensure DUAL MODE REACTION TO TRI-STATE 21 www.irf.com © 2014 International Rectifier To use the IR3548 in a single phase converter, simply set Dual mode, ground EN2 pin and leave the unused PWM2 input floating, as shown in Figure 5. PWM INPUT Anytime there is a tri-state on the PWM1 or PWM2, the respective SW output is tri-stated. Submit Datasheet Feedback January 08, 2014 IR3548 DOUBLER/QUAD MODE REACTION TO TRI-STATE PWM INPUT In Dual and Quad mode, anytime there is a tri-state on the master PWM1, all outputs (SW1 and SW2) are tri-stated. When the PWM1 transitions from a tristate to a high and then from a high to a low, only Phase 1 (SW1) operates. This allows the VR to operate properly in PS2 mode and during load releases. In Quad mode, both PWMIO1 and PWMIO2 signals of the master IR3548 go to 5V when PWM1 is tri-state to force the slave IR3548 to keep both control and synchronous MOSFETs off. PLOSS = VIN × I IN + VCC × IVCC + VDRV × IVDRV −(VSW 1 + VSW 2 ) × I OUT / 2 Where both MOSFET loss and the driver loss are included, but the PWM controller and the inductor losses are not included. Once the PWM1 sees a transition from a low to a high (absence of tri-state), the driver leaves single phase operation and returns to the Doubler or Quad functionality, as shown in Figure 10 and Figure 11. APPLICATION INFORMATION CONFIGURING THE PWM AND PHASE MODES The IR3548 can operate in 3 different PWM input modes including Dual, Doubler and Quad Modes (Master and Slave). Dual and Doubler modes can accept either an IR ATL input PWM signal or a TriState PWM signal (3.3V or 5V) while Quad mode can only accept ATL mode since PWM tri-state transition delays can not be tolerated when the PWM needs to operate at 4 times the switching frequency. Table 1 on page 3 shows the configuration of both the PWM modes and the driver modes utilizing the FUNCTION and MODE pins. Note that depending on the MODE selected in Table 1, Pin 14 (PWM2 / PWMIO1) and Pin 15 (EN2 / PWMIO2) change functions as well. The FUNCTION and MODE selection pins are latched into the IR3548 at power up and during EN1 cycling, and cannot be changed after these events. POWER LOSS CALCULATION The two-phase IR3548 efficiency and power loss measurement circuit is shown in Figure 34. The IR3548 power loss is determined by, 22 www.irf.com © 2014 International Rectifier Figure 34: IR3548 Power Loss Measurement Figure 12 shows the measured two-phase IR3548 efficiency under the default test conditions, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), Dual driver mode, VDRV=7V, TAMBIENT = 25°C, no heat sink, and no air flow. The measured two-phase IR3548 power loss under the same conditions is provided in Figure 13. If any of the application conditions, i.e. input voltage, output voltage, switching frequency, VCC MOSFET driver voltage or inductance, is different from those of Figure 13, a set of normalized power loss curves should be used. Obtain the normalizing factors from Figure 14 to Figure 18 for the new application conditions; multiply these factors by the power loss obtained from Figure 13 for the required load current. As an example, the power loss calculation procedures under different conditions, VIN=10V, VOUT=1V, ƒSW = 300kHz, L=210nH, VCC=5V, VDRV=5V, IOUT=50A, TAMBIENT = 25°C, no heat sink, and no air flow, are as follows. Submit Datasheet Feedback January 08, 2014 IR3548 1) Determine the power loss at 50A under the default test conditions of VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH, VCC=5V, VDRV=7V, TAMBIENT = 25°C, no heat sink, and no air flow. It is 5.5W from Figure 13. 2) Determine the input voltage normalizing factor with VIN=10V, which is 0.96 based on the dashed lines in Figure 14. 3) Determine the output voltage normalizing factor with VOUT=1V, which is 0.94 based on the dashed lines in Figure 15. 4) Determine the switching frequency normalizing factor with ƒSW = 300kHz, which is 0.99 based on the dashed lines in Figure 16. 5) Determine the VDRV MOSFET drive voltage normalizing factor with VDRV=5V, which is 1.25 based on the dashed lines in Figure 17. 6) Determine the inductance normalizing factor with L=210nH, which is 0.95 based on the dashed lines in Figure 18. 7) Multiply the power loss under the default conditions by the five normalizing factors to obtain the power loss under the new conditions, which is 5.5W x 0.96 x 0.94 x 0.99 x 1.25 x 0.95 = 5.83W. THERMAL DERATING Figure 19 shows the IR3548 thermal derating curve with the case temperature controlled at or below 125°C. The test conditions are VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH (0.29mΩ), VDRV=7V, TAMBIENT = 0°C to 100°C, no heat sink, and Airflow = 0LFM / 100LFM / 200LFM / 400LFM. If any of the application condition, i.e. input voltage, output voltage, switching frequency, VDRV MOSFET driver voltage, or inductance is different from those of Figure 19, a set of IR3548 case temperature adjustment curves should be used. Obtain the temperature deltas from Figure 14 to Figure 18 for the new application conditions; sum these deltas and then subtract from the IR3548 case temperature obtained from Figure 19 for the required load current. 23 www.irf.com © 2014 International Rectifier The IR3548 safe operating area is obtained with the case temperature controlled at or below 125°C. If a lower case temperature is desired, reduce the highest ambient temperature by the same delta. As an example, the highest ambient temperature calculation procedures for a different operating condition, VIN=10V, VOUT=1V, ƒSW = 300kHz, L=210nH, VDRV = 5V, IOUT=50A, TAMBIENT = 25°C, no heat sink, and no air flow, are as follows. 8) From Figure 19, determine the highest ambient temperature at the required load current under the default conditions, which is 59°C at 50A with 0LFM airflow and the IR3548 case temperature of 125°C. 9) Determine the case temperature with VIN=10V, which is -1.0° based on the dashed lines in Figure 14. 10) Determine the case temperature with VOUT=1V, which is -1.4° based on the dashed lines in Figure 15. 11) Determine the case temperature with ƒSW = 300kHz, which is -0.2° based on the dashed lines in Figure 16. 12) Determine the case temperature with VDRV = 5V, which is +5.5° based on the dashed lines in Figure 17. 13) Determine the case temperature with L=210nH, which is -1.1° based on the dashed lines in Figure 18. 14) Sum the case temperature adjustment from 9) to 13), -1.0° -1.4° -0.2° +5.5° -1.1° = +1.8°. Deduct the delta from the highest ambient temperature in step 8), 59°C - (+1.8°C) = 57.2°C. 15) If the desired IR3548 case temperature is 105°C instead of 125°C, subtract 20°C ( =125°C 105°C) from the highest ambient temperature obtained from 14), i.e. 57.2°C - 20°C = 37.2°C. INPUT CAPACITORS CVIN At least one 10uF 1206 ceramic capacitors and one 0.1uF 0402 ceramic capacitor are recommended for decoupling the VIN1 and VIN2 to PGND connection. The 0.1uF 0402 capacitor should be on the same Submit Datasheet Feedback January 08, 2014 IR3548 side of the PCB as the IR3548 and next to the VIN1/VIN2 and PGND pins. Adding additional capacitance and use of capacitors with lower ESR and mounted with low inductance routing will improve efficiency and reduce overall system noise, especially in single-phase designs or during high current operation. BOOTSTRAP CAPACITORS CBOOT1 AND 10). Low inductance routing for the decoupling capacitors is strongly recommended. PCB LAYOUT CONSIDERATIONS PCB layout and design is important to driver performance in voltage regulator circuits due to the high current slew rate (di/dt) during MOSFET switching. Contact International Rectifier for a layout example suitable for your specific application. CBOOT2 A minimum of 0.22uF 0402 capacitor is required for the bootstrap circuit. It should be mounted on the same side of the PCB as the IR3548 and as close as possible to the BOOT1 / BOOT2 pin. A low inductance routing of the SW1 / SW2 pin connection to the other terminal of the bootstrap capacitor is strongly recommended. VCC AND VDRV DECOUPLING • Locate all power components in each phase as close to each other as practically possible in order to minimize parasitics and losses, allowing for reasonable airflow. • Input supply decoupling and bootstrap capacitors should be physically located close to their respective IC pins. • GATEL1 and GATEL2 interconnect trace inductances should be minimized to prevent Cdv/dt turn-on of the low side MOSFETs. • The ground connection of the IC should be as close as possible to the low-side MOSFET source. • Use of a copper plane under and around the IC and thermal vias to connect to buried copper layers improves the thermal performance substantially. CAPACITORS CVCC AND CVDRV A 0.1uF ceramic decoupling capacitor is required at the VCC pin. A 1uF ceramic decoupling capacitor is required at the VDRV pin. They should be mounted on the same side of the PCB as the IR3548. The VCC capacitor should be as close as possible to the VCC and LGND. The VDRV capacitor should be as close as possible to HVCC/LVCC and PGND (pin 24 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. • Lead land length should be equal to maximum part lead length +0.15 - 0.3 mm outboard extension and 0 to + 0.05mm inboard extension. The outboard extension ensures a large and visible toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. 25 www.irf.com © 2014 International Rectifier • Center pad land length and width should be equal to maximum part pad length and width. • Only 0.30mm diameter via shall be placed in the area of the power pad lands and connected to power planes to minimize the noise effect on the IC and to improve thermal performance. Submit Datasheet Feedback January 08, 2014 IR3548 SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist miss-alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensures NSMD pads. • The minimum solder resist width is 0.13mm typical. • At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. • The power land pads VIN, PGND, and SW should be Solder Mask Defined (SMD). • Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Figure 35: Solder resist 26 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 65% to 75% of the area of the lead lands depending on stencil thickness. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. • The low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. • The power pads VIN, PGND and SW, land pad apertures should be approximately 65% to 75% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. Solder paste on large pads is broken down into small sections with a minimum gap of 0.2mm between allowing for out-gassing during solder reflow. • The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Figure 36: Stencil design * Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. 27 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 MARKING INFORMATION Site/Date/Marking Code Lot Code 3548M ?YWW? xxxxx Figure 37: PQFN 6mm x 8mm 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 PACKAGE INFORMATION Figure 38: PQFN 6mm x 8mm 29 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 Data and specifications subject to change without notice. This product will be designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com 30 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014