IRS26310DJPbF - International Rectifier

Data Sheet No. PD60347A
IRS26310DJPbF
HIGH VOLTAGE 3 PHASE GATE DRIVER IC WITH DC BUS
OVER –VOLTAGE PROTECTION
Features
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Drives up to six IGBT/MOSFET power devices
Gate drive supplies up to 20 V per channel
Integrated bootstrap functionality
DC bus sensing with Over Voltage protection
Over-current protection
Over-temperature shutdown input
Advanced input filter
Integrated deadtime protection
Shoot-through (cross-conduction) protection
Under voltage lockout for VCC & VBS
Enable/disable input and fault reporting
Adjustable fault clear timing
Separate logic and power grounds
3.3 V input logic compatible
Tolerant to negative transient voltage
Designed for use with bootstrap power supplies
Matched propagation delays for all channels
-40 °C to 125 °C operating range
RoHS compliant
Typical Applications
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Permanent magnet motor drives for appliances
Industrial drives
Micro inverter drives
Typical Connection Diagram
Rev.1.0
Product Summary
Topology
3 Phase
VOFFSET
≤ 600 V
VOUT
12 V – 20 V
Io+ & I o- (typical)
200 mA & 350 mA
tON & tOFF (typical)
530 ns & 530 ns
Deadtime (typical)
290 ns
Package Options
44-Lead PLCC (without 12 leads)
IRS26310DJPbF
Table of Contents
Page
Description
3
Simplified Block Diagram
3
Typical Application Diagram
4
Qualification Information
5
Absolute Maximum Ratings
6
Recommended Operating Conditions
7
Static Electrical Characteristics
8
Dynamic Electrical Characteristics
10
Functional Block Diagram
11
Input/Output Pin Equivalent Circuit Diagram
12
Lead Definitions
13
Lead Assignments
14
Application Information and Additional Details
15
Parameter Temperature Trends
36
Package Details
40
Tape and Reel Details
41
Part Marking Information
42
Ordering Information
43
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© 2007 International Rectifier
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IRS26310DJPbF
Description
The IRS26310DJPBF is a high voltage, high speed power MOSFET and IGBT driver with three independent
high and low side referenced output channels for 3-phase applications. This IC is designed to be used with
low-cost bootstrap power supplies; the bootstrap diode functionality has been integrated into this device to
reduce the component count and the PCB size. Proprietary HVIC technology enables ruggedized monolithic
construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. A current trip
function which terminates all six outputs can be derived from an external current sense resistor. An enable
function is available to terminate all six outputs simultaneously. An open-drain FAULT signal is provided to
indicate that an overcurrent or a VCC undervoltage shutdown has occurred. Overcurrent fault conditions are
cleared automatically after a delay programmed externally via an RC network connected to the RCIN input.
The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction.
Propagation delays are matched to simplify use in high frequency applications. The floating channel can be
used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V.
A DCbus sensing is provided using an external divider. Over Voltage DCbus protection is activate when
DCbus exceed an externally adjustable threshold, activating zero-vector braking mode (all Low side output
turn-on, all High side output-turn-off).
Simplified Block Diagram
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IRS26310DJPbF
Typical Application Diagram
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IRS26310DJPbF
†
Qualification Information
††
Industrial
Qualification Level
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
†††
PLCC44
Moisture Sensitivity Level
Class B
(per JEDEC standard JESD22-A114)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A115)
Class IV
(per JEDEC standard JESD22-C101)
Class I, Level A
(per JESD78)
Yes
Machine Model
ESD
MSL3 , 245°C
(per IPC/JEDEC J-STD-020)
Human Body Model
Charged Device Model
IC Latch-Up Test
RoHS Compliant
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††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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IRS26310DJPbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSS unless otherwise stated in the table. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Voltage clamps are
included between VCC & COM (25 V), VCC & VSS (20 V), and VB & VS (20 V).
Symbol
VS
VTST
VB
VHO
VCC
VSS
VLO1,2,3
VIN
VFLT
VDCBusSense
dV/dt
†
Definition
High side offset voltage
TST Voltage
High side floating supply voltage
High side floating output voltage
Low side and logic fixed supply voltage
Logic ground
Low side output voltage
Input voltage LIN, HIN, ITRIP, EN, RCIN
FAULT output voltage
Input sensing for DCBUS voltage
Allowable offset voltage slew rate
Min.
Max.
Units
VB - 20†
VB + 0.3
-0.3
20
-0.3
VS - 0.3
-0.3
VCC - 20
-0.3
VSS -0.3
VSS -0.3
VSS -0.3
—
620
VB + 0.3
20
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
50
V/ns
V
PD
Package power dissipation @ TA ≤ +25°C
—
2
W
RthJA
TJ
TS
TL
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
—
—
-55
—
63
150
150
300
°C/W
°C
All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply.
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IRS26310DJPbF
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are
absolute voltages referenced to VSS unless otherwise stated in the table. The offset rating is tested with supplies
of (VCC-COM) = (VB-VS) = 15 V.
Symbol
VB
VS
VS(t)
VTST
VCC
VHO
VLO
VSS
VFLT
VRCIN
VITRIP
VIN
VDCBusSense
TA
Definition
Min.
High side floating supply voltage
†
High side floating supply voltage
††
Transient high-side floating supply voltage
TST Voltage
Low side supply voltage
High side output voltage
Low side output voltage
Logic ground
FAULT output voltage
RCIN input voltage
ITRIP input voltage
Logic input voltage LIN, HIN, EN
Input sensing for DCbus voltage†††
Ambient temperature
VS +12
COM-8
-50
12
12
VS
0
-5
VSS
VSS
VSS
VSS
VSS
-40
Max.
Units
VS + 20
600
600
20
20
VB
VCC
5
VCC
VCC
VSS + 5
VSS + 5
VCC
125
V
°C
†
Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Please refer to Design Tip
DT97-3 for more details.
†† Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
††† DCBusSense pin is internally clamped with a 10.4 V zener diode.
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IRS26310DJPbF
Static Electrical Characteristics
o
(VCC-COM) = (VB-VS) = 15 V. TA = 25 C unless otherwise specified. The VIN ,VTH and IIN parameters are
referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to respective VS
and COM and are applicable to the respective output leads HO or LO. The VCCUV parameters are referenced to
VSS. The VBSUV parameters are referenced to VS.
Symbol
VIH
VIL
VIN,TH+
VIN,THVEN,TH+
VEN,THVIT,TH+
VIT,HYS
VRCIN, TH+
VRCIN, HYS
VOH
VOL
VCCUV+
VCCUVVCCUVHYS
VBSUV+
VBSUVVBSUVHY
Definition
Logic “1” input
Logic “0” input
Input positive going threshold
Input negative going threshold
Enable positive going threshold
Enable negative going threshold
ITRIP positive going threshold
ITRIP hysteresis
RCIN positive going threshold
RCIN hysteresis
High level output voltage, VBIAS – VO
Low level output voltage, VO
VCC supply undervoltage positive going
threshold
VCC supply undervoltage negative going
threshold
VCC supply undervoltage hysteresis
VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative going
threshold
VBS supply undervoltage hysteresis
Min.
Typ.
Max.
2.5
—
—
—
—
0.8
0.37
0.05
—
—
—
—
—
—
1.9
1
—
—
0.46
0.07
8
3
1.12
0.4
—
0.8
—
—
2.5
—
0.55
—
—
—
1.74
0.6
10.4
11.1
11.6
10.2
10.9
11.4
0.17
0.2
—
10.4
11.1
11.6
10.2
10.9
11.4
0.17
0.2
—
Over voltage DCBusSense positive going
3.86 4.20
threshold
Over voltage DCBusSense negative going
VDCBUSSTH3.70 4.03
threshold
VDCBUSSHYS
Over voltage DCBusSense hysteresis
0.14 0.17
ILK
Offset supply leakage current
—
3
IQBS
Quiescent VBS supply current
—
50
IQCC
Quiescent VCC supply current
—
3
IIN+
Input bias current (Lo or Ho= High)
—
100
IINInput bias current (Lo or Ho = Low)
-1
0
IITRIP+
“High” ITRIP input bias current
—
5
IITRIP“Low” ITRIP input bias current
-1
0
IFLT/EN+
“High” FLT/ENABLE input bias current
—
0
IFLT/EN“Low” FLT/ENABLE input bias current
-1
0
IDCBUSSENSE+
“High” DCBusSense input bias current
—
0
IDCBUSSENSE“Low” DCBusSense input bias current
-1
0
Note 1: Guaranteed by design over a temperature range of 0ºC to 110ºC
VDCBUSSTH+
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Units
Test Conditions
IO = 20 mA
V
4.54
Note 1
4.35
—
50
120
4
150
—
40
—
1
—
1
—
VB =VS = 600 V
mA
uA
All inputs @ logic 0
value
VIN = 3.3 V
VIN = 0 V
VITRIP = 5 V
VITRIP = 0 V
VFLT/EN = 3.3 V
VFLT/EN = 0 V
VDCBSENSE = 5 V
VDCBSENSE = 0 V
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IRS26310DJPbF
Static Electrical Characteristics (continued)
o
(VCC-COM) = (VB-VS) = 15 V. TA = 25 C unless otherwise specified. The VIN ,VTH and IIN parameters are referenced
to VSS and are applicable to all six channels. The VO and IO parameters are referenced to respective VS and COM and
are applicable to the respective output leads HO or LO. The VCCUV parameters are referenced to VSS. The VBSUV
parameters are referenced to VS.
Symbol
IRCIN+
IRCIN-
Definition
“High” RCIN input bias current
“Low” RCIN input bias current
Min.
Typ.
Max.
Units
—
-1
0
0
1
—
uA
Io+
Output high short circuit pulsed current
120
200
—
Io-
Output low short circuit pulsed current
250
350
—
—
—
—
50
50
200
100
100
400
mA
Ron_RCIN
Ron_FAULTEN
RBS
RCIN low on resistance
FAULT low on resistance
Internal bootstrap diode Ron
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Ω
Test
Conditions
VRCIN = 15 V
VRCIN = 0 V
Vo = 0 V,
PW ≤ 10 µs
Vo = 15 V,
PW ≤ 10 µs
I = 1.5 mA
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IRS26310DJPbF
Dynamic Electrical Characteristics
o
VCC= VB = 15 V, VS = VSS = COM, TA = 25 C, and CL = 1000 pF unless otherwise specified.
Symbol
ton
toff
tr
tf
tITRIP
tITRIP_blk
tFLT
tENOUT
tSDOUT
tZV_DCBS_LOon
tZV_DCBS_HOoff
tZV_DCBS_HOon
tZV_DCBS_LOoff
tZV_DCBS_flt_LO
tZV_DCBS_flt_HO
tFILIN
tFILTEREN
DT
MT
MDT
PM
tFLTCLR
†
††
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
ITRIP to output shutdown
propagation delay
ITRIP blanking time
ITRIP to FAULT propagation
delay
ENABLE high to output
propagation delay
ENABLE low to output
shutdown propagation delay
DCBusSense entering Over
voltage to LO turn on
DCBusSense entering Over
voltage to HO turn off
DCBusSense exiting Over
voltage to HO turn on
DCBusSense exiting Over
voltage to LO turn off
DCBusSense input filter time on
LO
DCBUSSENSE input filter time on
HO
†
Input filter time (HIN, LIN)
Enable input filter time
Deadtime
Ton, Toff matching time (on all
six channels)
DT matching (HIN->LO & LO>HIN on all channels)
††
Pulse width distortion
FAULT clear time RCIN: R = 2
meg, C = 1nF
Min.
Typ.
Max.
Units
Test Conditions
400
400
—
—
530
530
125
50
750
750
190
75
VIN = 0V & 5V
500
750
1200
VITRIP = 5V
—
500
750
400
600
950
350
460
650
350
460
650
310
460
730
310
460
730
270
380
590
300
450
720
140
250
420
140
250
420
200
100
190
350
200
290
510
—
420
—
—
50
—
—
60
—
—
75
1.3
1.65
2
VIN = 0V & 5V
VITRIP = 5V
ns
VIN = 0V & 5V
VEN = 0V & 3.3V
VDCBSENSE = 0V & 5V
VIN = 0V & 5V
ns
ms
VIN = 0V & 5V
External dead time 0s
PW input =10µs
VIN = 0V or 5V
VITRIP = 0V
The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the
input filter is exceeded.
PM is defined as PW IN - PW OUT.
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IRS26310DJPbF
Functional Block Diagram: IRS26310DJ
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IRS26310DJPbF
Input/Output Pin Equivalent Circuit Diagrams: IRS26310D
TST
VB
VCC
ESD
Diode
HIN
LIN
ESD
Diode
20 V
Clamp
ESD
Diode
20 V
Clamp
HO
ESD
Diode
R PD
V SS
VS
600 V
VCC
VCC
DCbus
Sense
ESD
Diode
ESD
Diode
ESD
Diode
25 V
Clamp
LO
ESD
Diode
10.4V
Clamp
COM
V SS
V ss
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IRS26310DJPbF
Lead Definitions: IRS26310DJ
Symbol
Description
VCC
VSS
TST
VB1
VB2
VB3
VS1
VS2
VS3
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
HO1
HO2
HO3
LO1
LO2
LO3
COM
Low-side supply voltage
Logic ground
TST to be shorted to VCC
High-side gate drive floating supply (phase 1)
High-side gate drive floating supply (phase 2)
High-side gate drive floating supply (phase 3)
High voltage floating supply return (phase 1)
High voltage floating supply return (phase 2)
High voltage floating supply return (phase 3)
Logic inputs for high-side gate driver outputs (phase 1)
Logic inputs for high-side gate driver outputs (phase 2)
Logic inputs for high-side gate driver outputs (phase 3
Logic inputs for low-side gate driver outputs (phase 1)
Logic inputs for low-side gate driver outputs (phase 2)
Logic inputs for low-side gate driver outputs (phase 3)
High-side driver outputs (phase 1)
High-side driver outputs (phase 2)
High-side driver outputs (phase 3)
Low-side driver outputs (phase 1)
Low-side driver outputs (phase 2)
Low-side driver outputs (phase 3)
Low-side gate drive return
Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred.
This pin has negative logic and an open-drain output. The use of over-current and overtemperature protection requires the use of external components.
Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No
effect on FAULT and not latched.
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates
FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally
set time tFLTCLR, then automatically becomes inactive (open-drain high impedance).
Analog input for DCbus sensing
An external RC network input used to define the FAULT CLEAR delay (tFLTCLR) approximately
equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance
state.
FAULT/N
EN
ITRIP
DCbusSense
RCIN
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Lead Assignments
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IRS26310DJPbF
Application Information and Additional Details
Informations regarding the following topics are included as subsections within this section of the datasheet.
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IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Undervoltage Lockout Protection
Shoot-Through Protection
Enable Input
Fault Reporting and Programmable Fault Clear Timer
Over-Current Protection
Over-Temperature Shutdown Protection
DC bus over-voltage Protection
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Advanced Input Filter
Short-Pulse / Noise Rejection
Integrated Bootstrap Functionality
Bootstrap Power Supply Design
Separate Logic and Power Grounds
Tolerant to Negative VS Transients
PCB Layout Tips
Bootstrap FET limitation
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS26310D HVIC is designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate
several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to
drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is
defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes
generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage.
VB
(or VCC)
VB
(or VCC)
IO+
HO
(or LO)
HO
(or LO)
+
IO-
VHO (or VLO)
VS
(or COM)
-
VS
(or COM)
Figure 1: HVIC sourcing current
Figure 2: HVIC sinking current
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IRS26310DJPbF
Switching and Timing Relationships
The relationship between the input and output signals of the IRS26310D is illustrated below in Figures 3. From this
figure, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with
this device.
Figure 3: Switching time waveforms
The following two figures illustrate the timing relationships of some of the functionality of the IRS26310D; this
functionality is described in further detail later in this document.
During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at
the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the highand low-side output are held in the off state.
Interval B of Figures 4 and 5 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a
result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also
held low), the voltage on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT output
transitioning to the low state. Once the ITRIP input has returned to the low state, the output will remain disabled and
the fault condition reported until the voltage on the RCIN pin charges up to VRCIN,TH (see interval C in Figure 6); the
charging characteristics are dictated by the RC network attached to the RCIN pin.
During intervals D and E of Figure 4, we can see that the enable (EN) pin has been pulled low (as is the case when
the driver IC has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx)
being held in the low state until the enable pin is pulled high.
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IRS26310DJPbF
Figure 4: Input/output timing diagram
Interval B
Interval C
VIT,TH-
VIT,TH+
ITRIP
FAULT
tFLT
50%
50%
RCIN
VRCIN,TH
tFLTCLR
90%
HOx
tITRIP
Figure 5: Detailed view of B & C intervals
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs
within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts
a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to
ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This
minimum deadtime is automatically inserter whenever the external deadtime is shorter than DT; external deadtimes
larger than DT are not modified by the gate driver. Figure 6 illustrates the deadtime period and the relationship
between the output gate signals.
The deadtime circuitry of the IRS26310D is matched with respect to the high- and low-side outputs of a given
channel; additionally, the deadtimes of each of the three channels are matched. Figure 6 defines the two deadtime
parameters (i.e., DT1 and DT2) of a specific channel; the deadtime matching parameter (MDT) associated with the
IRS26310D specifies the maximum difference between DT1 and DT2. The MDT parameter also applies when
comparing the DT of one channel of the IRS26310D to that of another.
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IRS26310DJPbF
Figure 6: Illustration of deadtime
Matched Propagation Delays
The IRS26310D family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both
the low-side channels and the high-side channels; the maximum difference is specified by the delay matching
parameter (MT). Additionally, the propagation delay for each low-side channel is matched when compared to the
other low-side channels and the propagation delays of the high-side channels are matched with each other; the MT
specification applies as well. The propagation turn-on delay (tON) of the IRS26310D is matched to the propagation
turn-on delay (tOFF).
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS26310D has been designed to
be compatible with 3.3 V and 5 V logic-level signals. Figure 7 illustrates an input signal to the IRS26310D, its input
threshold values, and the logic state of the IC as a result of the input signal.
Figure 7: HIN & LIN input thresholds
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IRS26310DJPbF
Undervoltage Lockout Protection
This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply
and the VBS (high-side circuitry) power supply. Figure 8 is used to illustrate this concept; VCC (or VBS) is plotted over
time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or
disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the
VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a
fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low
state to inform the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS
voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault
condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be
driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this
could result in very high conduction losses within the power device and could lead to power device failure.
Figure 8: UVLO protection
Shoot-Through Protection
The IRS26310D is equipped with shoot-through protection circuitry (also known as cross-conduction prevention
circuitry). Figure 9 shows how this protection circuitry prevents both the high- and low-side switches from conducting
at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that
the IRS26310D has non-inverting inputs (the output is in-phase with its respective input).
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IRS26310DJPbF
Figure 9: Illustration of shoot-through protection circuitry
IRS26310DJ
HIN
LIN
HO
LO
0
0
0
0
0
1
0
1
1
0
1
0
1
1
0
0
Table 1: Input/output truth table
Enable Input
The IRS26310D is equipped with an enable input pin that is used to shutdown or enable the HVIC. When the EN pin
is in the high state the HVIC is able to operate normally (assuming no other fault conditions). When a condition
occurs that should shutdown the HVIC, the EN pin should see a low logic state. The enable circuitry of the
IRS26310D features an input filter; the minimum input duration is specified by tFILTER,EN. Please refer to the EN pin
parameters VEN,TH+, VEN,TH-, and IEN for the details of its use. Table 2 gives a summary of this pin’s functionality and
Figure 10 illustrates the outputs’ response to a shutdown command.
Enable Input
*
Enable input high
Outputs enabled
Enable input low
Outputs disabled
Table 2: Enable functionality truth table
(*assumes no other fault condition)
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IRS26310DJPbF
Figure 10: Output enable/disable timing waveform
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Fault Reporting and Programmable Fault Clear Timer
The IRS26310D family provides an integrated fault reporting output and an adjustable fault clear timer. There are two
situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC
and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally
pulled to VSS and the fault clear timer is activated. The fault output stays in the low state until the fault condition has
been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the FAULT pin will
return to VCC.
The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the capacitor
where the time constant is set by RRCIN and CRCIN. In Figure 11 where we see that a fault condition has occurred
(UVLO or ITRIP), RCIN and FAULT are pulled to VSS, and once the fault has been removed, the fault clear timer
begins. Figure 12 shows that RRCIN is connected between the VCC and the RCIN pin, while CRCIN is placed between
the RCIN and VSS pins.
Figure 11: RCIN and FAULT pin waveforms
Figure 12: Programming the fault clear timer
The design guidelines for this network are shown in Table 3.
≤1 nF
CRCIN
Ceramic
0.5 MΩ to 2 MΩ
RRCIN
>> RON,RCIN
Table 3: Design guidelines
The length of the fault clear time period can be determined by using the formula below.
-t/RC
vC(t) = Vf(1-e
)
tFLTCLR = -(RRCINCRCIN)ln(1-VRCIN,TH/VCC)
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Over-Current Protection
The IRS26310D HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current
events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are
shutdown, a fault is reported through the FAULT pin, and RCIN is pulled to VSS.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1,
and R2) connected to ITRIP as shown in Figure 14, and the ITRIP threshold (VIT,TH+). The circuit designer will need to
determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at
node VX reaches the over-current threshold (VIT,TH+) at that current level.
VIT,TH+ = R0IDC-(R1/(R1+R2))
Figure 13: Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to
exceed 5 V; if necessary, an external voltage clamp may be used.
Over-Temperature Shutdown Protection
The ITRIP input of the IRS26310D can also be used to detect over-temperature events in the system and initiate a
shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will
need to design the resistor network as shown in Figure 14 and select the maximum allowable temperature.
This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the
resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should
be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that
the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.
When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes
(e.g., DL4148) can be used. This network is shown in Figure 15; the OR-ing diodes have been labeled D1 and D2.
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IRS26310DJPbF
Figure 14: Programming over-temperature protection
Figure 15: Using over-current protection and overtemperature protection
DC bus Over-Voltage Protection
When driving permanent magnet ac motors there is a potential to regenerate some of the motor mechanical
energy back onto the dc bus. “Zero vector braking” prevents charging of the dc bus capacitor by shorting all three
motor terminals to a common rail to dissipate this mechanical energy in the motor windings. The dc bus overvoltage protection feature on the IC initiates zero vector braking when the dc bus voltage goes above some
critical voltage level to prevent damage to dc bus components. Zero vector braking should only be used when the
motor winding inductance is sufficient to limit the motor short circuit current to a safe level. Dc bus protection
operates even when all PWM inputs are disabled so will protect the motor when operating in high speed field
weakening mode.
The IRS26310D ICs have a DCbusSense input pin to detect over-voltage events on the DC bus. Once the IC
detects an over-voltage event, zero vector mode braking is forced (all Low side output turn-on, all High side
output-turn-off) overriding the PWM signals coming from the controller. A fault is not reported on the FAULT pin
for this condition because the power inverter is still active. DC bus over-voltage protection is not latched and so
the zero vector mode is released when DCbusSense pin is lower than OVDCBUSVTH- .
The level of voltage at which the over-voltage protection is initiated is determined by the resistor divider (i.e., R0 and
R1) connected to DCbusSense as shown in Figure 16, and the DCbusSense threshold (OVDCBUSVTH+). The circuit
designer will need to determine the maximum allowable level of DC bus voltage and select R0 and R1 such that the
voltage at node VX reaches the over-voltage threshold (OVDCBUSVTH+).
OVDCBUSVTH+= R1VDCBUS/(R0+R1)
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DCbus
R0
DCbusSense
Vx
R1
Vss
Figure 16: Programming the DC bus over-voltage protection
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Table 4 provides the truth table for the IRS26310D. The first line shows that the UVLO for VCC has been tripped; the
FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and
when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that
DCbus OV has been tripped and that the zero vector mode has been activated.
The third case shows that the UVLO for VBS has been tripped and that the high-side gate drive output has been
disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new or rising
transition of HIN. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive
outputs have been disabled and a fault has been reported through the fault pin (When ITRIP< VITRIP FAULT returns to
High impedance after RCIN pin becomes greater than 8V). In the fifth case, the HVIC has received a command
through the EN input to shutdown; as a result, the gate drive outputs have been disabled. The last case shows the
normal operation of the HVIC (a shoot-through protection prevention logic prevent LO1,2,3 and HO1,2,3 for each
channel turn on simultaneously).
VCC
UVLO VCC
<VCCUV
DCbus OV
15 V
UVLO VBS
15 V
ITRIP fault
15 V
EN
command
Normal
operation
15 V
15 V
DCbus
sense
-->OVdcb
us
<OVdcb
us
<OVdcb
us
<OVdcb
us
<OVdcb
us
VBS
ITRIP
EN
RCIN
FAULT
LO
HO
---
---
---
High
0
0
0
---
---
---
High
High Z
1
0
<VBSUV
0V
5V
High
High Z
LIN
0
15 V
>VITRIP
5V
Low
0
0
0
15 V
0V
0V
High
High Z
0
0
15 V
0V
5V
High
High Z
LIN
HIN
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Table 4: DCbus OV, UVLO, ITRIP, EN, RCIN, & FAULT truth table
Advanced Input Filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject
noise spikes and short pulses. This input filter has been applied to the HIN, LIN, and EN inputs. The working
principle of the new filter is shown in Figures 17 and 18.
Figure 17 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the
difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with a
duration slightly longer then tFIL,IN; the resulting output is approximately the difference between the input signal and
tFIL,IN.
Figure 18 shows the advanced input filter and the symmetry between the input and output. The upper pair of
waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is
approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal
with a duration slightly longer then tFIL,IN; the resulting output is approximately the same duration as the input signal.
Figure 17: Typical input filter
Figure 18: Advanced input filter
Short-Pulse / Noise Rejection
This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the
input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 19 shows the input and output in
the low state with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2 of
Figure 19 shows the input and output in the high state with negative noise spikes of durations less than tFIL,IN; the
output does not change states.
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Example 2
Example 1
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Figure 19: Noise rejecting input filters
Figures 20 and 21 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF
pulses.
The input filter characteristic is shown in Figure 20; the left side illustrates the narrow pulse ON (short positive pulse)
characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 20
shows the duration of PW IN, while the y-axis shows the resulting PW OUT duration. It can be seen that for a PW IN
duration less than tFIL,IN, that the resulting PW OUT duration is zero (e.g., the filter rejects the input signal/noise). We
also see that once the PW IN duration exceed tFIL,IN, that the PW OUT durations mimic the PW IN durations very well over
this interval with the symmetry improving as the duration increases. To ensure proper operation of the HVIC, it is
suggested that the input pulse width for the high-side inputs be ≥ 500 ns.
Time (ns)
The difference between the PW OUT and PW IN signals of both the narrow ON and narrow OFF cases is shown in
Figure 21; the careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PW IN,
while the y-axis shows the resulting PW OUT–PW IN duration. This data illustrates the performance and near symmetry
of this input filter.
Figure 20: Input filter characteristic
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Figure 21: Difference between the input pulse and the output pulse
Integrated Bootstrap Functionality
The new IRS26310D family features integrated high-voltage bootstrap MOSFETs that eliminate the need of the
external bootstrap diodes and resistors in many applications.
There is one bootstrap MOSFET for each high-side output channel and it is connected between the VCC supply and
its respective floating supply (i.e., VB1, VB2, VB3); see Figure 22 for an illustration of this internal connection.
The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source
current due to RBS. The VBS voltage will be charged each cycle depending on the on-time of LO and the value of the
CBS capacitor, the drain-source (collector-emitter) drop of the external IGBT (or MOSFET), and the low-side freewheeling diode drop.
The bootstrap MOSFET of each channel follows the state of the respective low-side output stage (i.e., the bootstrap
MOSFET is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 110%
of VCC. In that case, the bootstrap MOSFET is designed to remain off until VB returns below that threshold; this
concept is illustrated in Figure 23.
VB1
VCC
VB2
VB3
Figure 22: Internal bootstrap MOSFET connection
Figure 23: Bootstrap MOSFET state diagram
A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with the
external bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap as
a replacement of the external bootstrap network may have some limitations. An example of this limitation may arise
when this functionality is used in non-complementary PWM schemes (typically 6-step modulations) and at very high
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PWM duty cycle. In these cases, superior performances can be achieved by using an external bootstrap diode in
parallel with the internal bootstrap network.
Bootstrap Power Supply Design
For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality
of the IRS26310, please refer to Application Note 1123 (AN-1123) entitled “Bootstrap Network Analysis: Focusing on
the Integrated Bootstrap Functionality.” This application note is available at www.irf.com.
For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode)
please refer to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is
available at www.irf.com.
Separate Logic and Power Grounds
The IRS26310D has separate logic and power ground pin (VSS and COM respectively) to eliminate some of the noise
problems that can occur in power conversion applications. Current sensing shunts are commonly used in many
applications for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for
motor current measurements. In these situations, it is often beneficial to separate the logic and power grounds.
Figure 24 shows a HVIC with separate VSS and COM pins and how these two grounds are used in the system. The
VSS is used as the reference point for the logic and over-current circuitry; VX in the figure is the voltage between the
ITRIP pin and the VSS pin. Alternatively, the COM pin is the reference point for the low-side gate drive circuitry. The
output voltage used to drive the low-side gate is VLO-COM; the gate-emitter voltage (VGE) of the low-side switch is the
output voltage of the driver minus the drop across RG,LO.
DC+ BUS
DBS
VB
(x3)
VCC
CBS
HO
(x3)
HVIC
ITRIP
RG,HO
VS
(x3)
LO
(x3)
VS1
VS3
RG,LO
+
+
VSS
VS2
VGE1
COM
+
VGE2
-
-
VGE3
-
R2
R0
+
VX
R1
-
DC- BUS
Figure 24: Separate VSS and COM pins
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Tolerant to Negative VS Transients
A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage
as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is
shown in Figure 25; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 26 and 27) switches off, while the U phase current is flowing to
an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the lowside switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus
voltage to the negative DC bus voltage.
Figure 25: Three phase inverter
DC+ BUS
Q1
ON
IU
VS1
Q2
OFF
D2
DC- BUS
Figure 26: Q1 conducting
Figure 27: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 28 and 29), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
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Figure 28: D3 conducting
Figure 29: Q4 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it
swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 30 depicts one leg of the three phase inverter; Figures 31 and 32 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from
the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on,
VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the
circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling
diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the
DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the
DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin).
Figure 30: Parasitic Elements
Figure 31: VS positive
Figure 32: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is
greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. The IRS26310D has been seen to withstand large negative VS transient conditions on the order of -50 V
for a period of 50 ns. An illustration of the IRS26310D’s performance can be seen in Figure 33. This experiment was
conducted using various loads to create this condition; the curve shown in this figure illustrates the successful
operation of the IRS26310D under these stressful conditions.
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Figure 33: Negative VS transient results for an International Rectifier HVIC
Even though the IRS26310D has been shown able to handle these large negative VS transient conditions, it is highly
recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB
layout and component use.
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the
floating voltage pins (VB and VS) near the respective high voltage portions of the device. The IRS26310D in the
PLCC44 package has had some unused pins removed in order to maximize the distance between the high voltage
and low voltage pins. Please see the Case Outline PLCC44 information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
34). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops
must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT
collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a
voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 34: Antenna Loops
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Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins.
connection is shown in Figure 35. A ceramic 1 µF ceramic capacitor is suitable for most applications.
component should be placed as close as possible to the pins in order to reduce parasitic elements.
This
This
Vcc
HIN (x3)
VB (x3)
LIN (x3)
HO (x3)
EN
VS (x3)
FAULT
CIN
RCIN
LO (x3)
ITRIP
COM
VSS
Figure 35: Supply capacitor
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at
the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it
is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side
emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps
may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch
node (see Figure 36), and in some cases using a clamping diode between VSS and VS (see Figure 37). See DT04-4
at www.irf.com for more detailed information.
Figure 36: VS resistor
Figure 37: VS clamping diode
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Integrated Bootstrap FET limitation
The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to
the HVIC:
•
•
VCC pin voltage = 0V AND
VS or VB pin voltage > 0
In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a
current conduction path is created between VCC & VB pins, as illustrated in Fig.38 below, resulting in power loss
and possible damage to the HVIC.
Figure 38: Current conduction path between VCC and VB pin
Relevant Application Situations:
The above mentioned bias condition may be encountered under the following situations:
• In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF.
In this condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS
nodes resulting unwanted current flow to VCC.
• Potential situations in other applications where VS/VB node voltage potential increases before the
VCC voltage is available (for example due to sequencing delays in SMPS supplying VCC bias)
Application Workaround:
Insertion of a standard p-n junction diode between VCC pin of IC and positive terminal of VCC capacitors (as
illustrated in Fig.39) prevents current conduction “out-of” VCC pin of gate driver IC. It is important not to connect
the VCC capacitor directly to pin of IC. Diode selection is based on 25V rating or above & current capability
aligned to ICC consumption of IC - 100mA should cover most application situations. As an example, Part number
# LL4154 from Diodes Inc (25V/150mA standard diode) can be used.
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IRS26310DJPbF
VCC
VCC
Capacitor
VB
VSS
(or COM)
Figure 39: Diode insertion between VCC pin and VCC capacitor
Note that the forward voltage drop on the diode (VF) must be taken into account when biasing the VCC pin of the
IC to meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – VF of Diode.
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
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Parameter Temperature Trends
Figures 40-60 provide information on the experimental performance of the IRS26310D HVIC. The line plotted in
each figure is generated from actual lab data. A small number of individual samples were tested at three
temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp.
consist of three data points (one data point at each of the tested temperatures) that have been connected together
to illustrate the understood temperature trend. The individual data points on the curve were determined by
calculating the averaged experimental value of the parameter (for a given temperature).
1000
1000
800
Toff_Lo_1 (ns)
Ton_Lo_1 (ns)
800
Exp.
600
400
200
Exp.
600
400
200
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Figure 40: tON vs. temperature
Figure 41: tOFF vs. temperature
600
1500
1250
Titrip (ns)
DT (ns)
450
Exp.
300
1000
Exp.
750
500
150
250
0
0
-50
-25
0
25
50
75
100
125
-50
o
-25
0
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Figure 43: tITRIP vs. temperature
Figure 42: DT vs. temperature
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IRS26310DJPbF
1000
500
400
Exp.
TfilterEn (ns)
TitripFlt (ns)
800
600
400
200
300
Exp.
200
100
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
o
75
100
125
100
125
Temperature ( C)
Figure 44: tFLT vs. temperature
Figure 45 tEN vs. temperature
100
100
80
80
Ron_FLT (ohm)
Ron_Rcin (ohm)
50
o
Temperature ( C)
60
40
25
Exp.
20
60
40
Exp.
20
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
Temperature (oC)
Figure 46: RON,RCIN vs. temperature
Figure 47: RON,FLT vs. temperature
100
5.00
2.50
IQBS (uA)
IQCC (mA)
80
3.75
Exp.
1.25
60
Exp.
40
20
0
0.00
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
o
Temperature ( C)
Temperature (oC)
Figure 48: IQCC vs. temperature
Figure 49: IQBS vs. temperature
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37
20.00
20.00
16.00
16.00
12.00
vcc_UV- (V)
vcc_UV+ (V)
IRS26310DJPbF
Exp.
8.00
4.00
12.00
Exp.
8.00
4.00
0.00
0.00
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
50
75
100
125
Figure 51: VCCUV- vs. temperature
25.00
25.00
20.00
20.00
vbs_1_UV- (V)
vbs_1_UV+ (V)
Figure 50: VCCUV+ vs. temperature
15.00
Exp.
10.00
5.00
15.00
Exp.
10.00
5.00
0.00
0.00
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Figure 52: VBSUV+ vs. temperature
Figure 53: VBSUV- vs. temperature
1.00
1.00
0.80
0.80
VIT_TH- (V)
VIT_TH+ (V)
25
Temperature (oC)
0.60
Exp.
0.40
0.60
Exp.
0.40
0.20
0.20
0.00
0.00
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 54: VIT,TH+ vs. temperature
Figure 55: VIT,TH- vs. temperature
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© 2008 International Rectifier
38
500
500
400
400
Io-_lo_1 (mA)
Io+_lo_1 (mA)
IRS26310DJPbF
300
Exp.
200
100
Exp.
300
200
100
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Figure 56: IO+ vs. temperature
Figure 57: IO- vs. temperature
Figure 58: VDCBUSSTH+ vs. temperature
Figure 59: VDCBUSSTH- vs. temperature
10.00
itrip_1 (uA)
8.00
6.00
Exp.
4.00
2.00
0.00
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 60: IITRIP+ vs. temperature
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© 2008 International Rectifier
39
IRS26310DJPbF
Package Details: PLCC44
www.irf.com
© 2008 International Rectifier
40
IRS26310DJPbF
Tape and Reel Details: PLCC44
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR 44PLCC
Metric
Imperial
Code
Min
Max
Min
Max
A
23.90
24.10
0.94
0.948
B
3.90
4.10
0.153
0.161
C
31.70
32.30
1.248
1.271
D
14.10
14.30
0.555
0.562
E
17.90
18.10
0.704
0.712
F
17.90
18.10
0.704
0.712
G
2.00
n/a
0.078
n/a
H
1.50
1.60
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 44PLCC
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
38.4
G
34.7
35.8
H
32.6
33.1
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
1.511
1.366
1.409
1.283
1.303
© 2008 International Rectifier
41
IRS26310DJPbF
Part Marking Information
www.irf.com
© 2008 International Rectifier
42
IRS26310DJPbF
Ordering Information
Standard Pack
Base Part Number
IRS26310D
Package Type
PLCC44
Complete Part Number
Form
Quantity
Tube/Bulk
27
IRS26310DJPBF
Tape and Reel
500
IRS26310DJTRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of
other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any
patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This
document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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© 2008 International Rectifier
43
IRS26310DJPbF
Revision History
Revision
1.6
1.7
1.8
Date
04-17-08
04-18-08
06-01-11
Change comments
Corrected unit for deadtime from “uS” to “nS”
Updated Qualification information table per new IR standard
Add bootstrap FET limitation
www.irf.com
© 2007 International Rectifier
44