Data Sheet

HT49RA1/HT49CA1
Remote Type 8-Bit MCU with LCD
Features
· Operating voltage: 2.0V~3.6V
· 8-bit prescaler for RTC
· 12 bidirectional I/O lines, 8 input lines,
· One carrier output (1/2 or 1/3 duty)
8 segment output, PC0 (input/output)/REM
· Software LCD, RTC control
· Two external interrupt inputs shared with an I/O line
· Watchdog Timer function
· 8-bit programmable Timer/Event Counter with
· Power down and wake-up functions to reduce
overflow interrupt function
power consumption
· Single 16-bit programmable timer/event counter
· Up to 1ms instruction cycle with 4MHz system clock
with overflow interrupt function
· 4-level subroutine nesting
· RC oscillator and 32768Hz crystal oscillator
· Bit manipulation instruction
· LCD driver with 33´2, 33´3 or 32´4 segments
· Table read instructions
(C type only), 8 logical output option for
SEG12~SEG19 and 4 I/O port option for
SEG0~SEG3 by changing LCDC register
· 63 powerful instructions
· All instructions executed in one or two machine
cycles
· 4096´15 program memory
· Low voltage reset/detector function
· 160´8 data memory
· 64-pin LQFP package
· Real Time Clock - RTC
General Description
The HT49RA1/HT49CA1 is a Remote Type 8-bit MCU
8 -b it h igh per f o r m anc e R I S C ar c hi t e ct u r e
microcontroller. With its internal carrier generator and
LCD Driver functions the device is is especially suitable
for multiple I/O remote control product applications. The
usual Holtek MCU features such as power down and
wake-up functions, oscillator options, etc. combine to
ensure user applications require a minimum of external
components.
The benefits of low power consumption, high performance, I/O flexibility and low-cost, provide these devices with the versatility to suit a wide range of
application possibilities such as industrial control, consumer products and particularly suitable for use in products such as infrared LCD remote controllers and
various, subsystem controllers, etc.
Device Types
Devices which have the letter ²R² within their part number,
indicate that they are OTP devices offering the advantages of easy and effective program updates, using the
Holtek range of development and programming tools.
These devices provide the designer with the means for
fast and low-cost product development cycles. Devices
which have the letter ²C² within their part number indicate
that they are mask version devices. These devices offer a
complementary device for applications that are at a mature state in their design process and have high volume
and low cost demands.
Rev. 1.10
Fully pin and functionally compatible with their OTP
sister devices, the mask version devices provide the
ideal substitute for products which have gone beyond
their development cycle and are facing cost-down demands.
In this datasheet, for convenience, when describing
device functions, only the OTP types are mentioned
by name, however the same described functions also
apply to the Mask type devices.
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March 30, 2014
HT49RA1/HT49CA1
Block Diagram
I/O
P o rts
C a r r ie r
G e n e ra to r
Note:
W a tc h d o g
T im e r
O T P
P r o g r a m m in g
C ir c u itr y
S ta c k
O T P
P ro g ra m
M e m o ry
D a ta
M e m o ry
L C D
D r iv e r
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
In te rru p t
C o n tr o lle r
L o w
V o lta g e
R e s e t
T im e r s
R C S y s te m
O s c illa to r
This block diagram represents the OTP devices, for the mask devices there is no Device Programming
Circuitry.
Pin Assignment
P D 3
P D 2
P D 1
P D 0
/S
/S
/S
/S
O
O
O
S
E G 4
E G 3
E G 2
E G 1
E G 0
S C 4
S C 3
V D D
S C 1
R E S
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P B
P B
P B 2
P B 3
P C
P A 6
P A 7
0 /IN T 0
1 /IN T 1
/T M R 0
/T M R 1
P B 4
P B 5
V S S
0 /R E M
P B 6
P B 7
V L C D
V 1
V 2
C 1
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
1
4 8
4 7
2
3
4 6
5
4 4
4 5
4
6
7
8
H T 4 9 R A 1 /H T 4 9 C A 1
6 4 L Q F P -A
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C 2
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 /S E G 3 2
2
1
0
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
Pin Description
I/O
Configuration
Option
Description
PA0~PA7
I/O
¾
Bidirectional NMOS 8-bit input/output port. Each bit can be chosen as an
NMOS output or Schmitt trigger input using software instructions. Pull-high
resistors are permanently connected to these pins.
PB0/INT0
PB1/INT1
PB2/TMR0
PB3/TMR1
PB4~PB7
I
Wake-up
8-bit Schmitt trigger input lines with pull-high resistors. Each bit can be configured as a wake-up input via configuration options. Pins PB0, PB1, PB2
and PB3 are pin-shared with INT0, INT1, TMR0 and TMR1 respectively
PC0/REM
I/O
Carrier Output Bidirectional I/O port. PC0 can be configured as a CMOS output pin or carPull-high
rier output pin using a configuration option.
I/O
¾
Bidirectional NMOS 4-bit input/output port. Each bit can be chosen as an
NMOS output or Schmitt trigger input using software instructions. Each pin
on this port can be configured either as a segment pin or normal I/O pin using the LCDC register. When used as I/O pins pull-high resistors are permanently connected to these pins.
OSC1
I
¾
A resistor is connected between OSC1 and ground to implement the internal
system clock.
OSC3
OSC4
I
O
¾
Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purpose. It is not used as the system clock. If the
RTC is not selected as fS. then OSC3, OSC4 should be left floating.
VLCD
¾
¾
LCD power supply. VLCD should be larger than VDD for connect operation
i.e. VLCD ³ VDD
V1, V2, C1, C2
LCD voltage pump
COM0~COM2
COM3/SEG32
O
1/2, 1/3 or 1/4
Duty
COM0~COM2 are the LCD panel common connections. Pin COM3/SEG32
can be setup as an LCD panel segment or as a common output driver via
configuration options.
SEG4~SEG11
O
¾
SEG12~SEG19
O
SEG20~SEG31
O
Pin Name
PD0/SEG0~
PD3/SEG3
LCD panel segments driver outputs.
SEG12~SEG19 LCD panel segments driver outputs . SEG12~SEG19 can be setup as LCD
CMOS Output segment outputs or as CMOS output via a configuration option.
¾
LCD panel segments driver outputs.
RES
I
¾
Schmitt Trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
Note:
Each pin on PB can be programmed through a configuration option to have a wake-up function.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
2.0
¾
3.6
V
VDD
Operating Voltage
¾
IDD
Operating Current (RC OSC)
3V
No load, fSYS=4MHz
¾
0.7
1.5
mA
ISTB1
Standby Current (*fS=T1)
3V
No load, system HALT,
LCD off at HALT
¾
0.1
1
mA
ISTB2
Standby Current
(*fS=32.768kHz OSC)
3V
No load, system HALT,
LCD On at HALT, C type
¾
2.5
5
mA
ISTB3
Standby Current
(*fS=WDT RC OSC)
3V
No load, system HALT
LCD On at HALT, C type
¾
2
5
mA
VIL1
Input Low Voltage for I/O Ports,
TMR0/TMR1 and INT0/INT1
3V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0/TMR1 and INT0/INT1
3V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
3V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
3V
¾
0.9VDD
¾
VDD
V
IOL1
I/O Port & REM Sink Current
3V
VOL=0.1VDD
4
8
¾
mA
IOH1
I/O Port & REM Source Current
3V
VOH=0.9VDD
-5
-7
¾
mA
IOL2
LCD Common and Segment Current
3V
VOL=0.1VDD
210
420
¾
mA
IOH2
LCD Common and Segment Current
3V
VOH=0.9VDD
-80
-160
¾
mA
RPH
Pull-high Resistance of I/O Ports
3V
100
150
200
kW
VLVR
¾
1.98
2.10
2.22
V
Low Voltage Reset Voltage
VLVD
Low Voltage Detector Voltage
¾
¾
LVR 2.1V option
LVR 3.15V optio
2.98
3.15
3.32
V
LVD voltage 2.2V option
2.08
2.20
2.32
V
LVD voltage 3.3V option
3.12
3.30
3.50
V
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RPOR
VDD Rise Rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
Note:
tSYS=1/fSYS
²*fS² please refer to WDT clock option
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.0V~ 4MHz ± 3%,
3.6V Temp.= 0°C ~ 50°C
¾
4000
¾
kHz
3.0V 4MHz ± 2%, Temp.= 25°C
¾
4000
¾
kHz
VDD
fSYS
System Clock
Conditions
fRTCOSC
RTC Frequency
¾
¾
¾
32768
¾
Hz
fTIMER
Timer I/P Frequency
(TMR0/TMR1)
3V
¾
0
¾
4000
kHz
tWDTOSC Watchdog Oscillator Period
3V
¾
45
90
180
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note: *tSYS=1/fSYS
Rev. 1.10
5
March 30, 2014
HT49RA1/HT49CA1
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O with maximum reliability and flexibility. This makes these devices suitable
for low-cost, high-volume production for controller applications requiring 4K words of Program Memory and 160
bytes of Data Memory storage.
Clocking and Pipelining
The main system clock, derived from RC oscillator is
subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which
time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions.
In this way, one T1~T4 clock cycle forms one instruction
cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the
pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction
cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as
subroutine calls or jumps, in which case the instruction
will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
Program Counter
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. For the Remote Type series of microcontrollers with LCD, note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack can have 4 levels is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
Program Counter Bits
Mode
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
1
0
0
0
0
Time Base Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
RTC Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter + 2
Loading PCL
PC11 PC10 PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: PCL bits
#11~#0: Instruction code address bits
S11~S0: Stack register bits
The Program Counter is 12 bits wide, i.e. from b11~b0.
Rev. 1.10
7
March 30, 2014
HT49RA1/HT49CA1
P ro g ra m
0 0 0 H
C o u n te r
0 0 4 H
T o p o f S ta c k
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
S ta c k L e v e l 1
S ta c k L e v e l 3
o f S ta c k
0 0 8 H
P ro g ra m
M e m o ry
0 0 C H
S ta c k L e v e l 4
0 1 0 H
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
0 1 4 H
0 1 8 H
E x te rn a l
In te rru p t 0 V e c to r
E x te rn a l
In te rru p t 1 V e c to r
T im e r /E v e n t C o u n te r
0 In te rru p t V e c to r
T im e r /E v e n t C o u n te r
1 In te rru p t V e c to r
T im e B a s e
In te rru p t V e c to r
R T C
In te rru p t V e c to r
3 0 0 H
3 F F H
4 0 0 H
7 F F H
8 0 0 H
F F F H
Arithmetic and Logic Unit - ALU
1 5 b its
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
Program Memory Structure
production runs. The other type of memory is the mask
ROM memory, denoted by having a ²C² within the device
name. These devices offer the most cost effective solutions for high volume products.
Structure
The Program Memory has a capacity of 4K by 15 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by
separate table pointer registers.
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
Special Vectors
RLC
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
· Location 000H
SIZA, SDZA, CALL, RET, RETI
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
Program Memory
The Program Memory is the location where the user code
or program is stored. For microcontrollers, two types of
Program Memory are usually supplied. The first type is
the One-Time Programmable, OTP, memory where users can program their application code into the device.
Devices with OTP memory are denoted by having an ²R²
within their device name. By using the appropriate programming tools, OTP devices offer users the flexibility to
freely develop their applications which may be useful
during debug or for products requiring frequent upgrades
or program changes. OTP devices are also applicable for
use in applications that require low or medium volume
Rev. 1.10
In itia lis a tio n
V e c to r
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin INT0 on the device receives an active edge, the program will jump to this location and
begin execution if the external interrupt is enabled and
the stack is not full.
· Location 008H
This vector is used by the external interrupt. If the external interrupt pin INT1 on the device receives an active edge, the program will jump to this location and
begin execution if the external interrupt is enabled and
the stack is not full.
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March 30, 2014
HT49RA1/HT49CA1
· Location 00CH
The following diagram illustrates the addressing/data
flow of the look-up table:
This internal vector is used by the Timer/Event Counter 0. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
· Location 010H
This internal vector is used by the Timer/Event Counter 1. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts H ig h B y te
T a b le C o n te n ts L o w
B y te
Table Program Example
· Location 014H
This internal vector is used by the Time Base interrupt.
If a Time Base interrupt occurs, the program will jump
to this location and begin execution if the time base interrupt is enabled and the stack is not full.
The following example shows how the table pointer and
table data is defined and retrieved from the HT49RA1
microcontroller. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory of the HT49RA1
microcontroller. The table pointer is setup here to have
an initial value of ²06H². This will ensure that the first
data read from the data table will be at the Program
Memory address ²F06H² or 6 locations after the start of
the last page. Note that the value for the table pointer is
referenced to the first address of the present page if the
²TABRDC [m]² instruction is being used. The high byte
of the table data which in this case is equal to zero will
be transferred to the TBLH register automatically when
the ²TABRDL [m]² instruction is executed.
· Location 018H
This internal vector is used by the Real Time Clock interrupt. The program will jump to this location and begin execution when a Real Time Clock interrupt signal
is generated if the interrupt is enabled and the stack is
not full.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
Table Location Bits
Instruction
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: Table Pointer TBLP bits
The table address location is 12 bits, i.e. from b11~b0.
Rev. 1.10
9
March 30, 2014
HT49RA1/HT49CA1
tempreg1 db
tempreg2 db
:
:
?
?
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address
; is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
;
;
;
;
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²F06H² transferred to
tempreg1 and TBLH
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
:
:
org
F00h
; sets initial address of last page (for HT49RA1)
Dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into three sections, the first
of these is an area of RAM where special function registers are located. These registers have fixed locations
and are necessary for correct operation of the device.
Many of these registers can be read from and written to
directly under program control, however, some remain
S p e c
P u rp o
D a
M e m o
ia l
s e
ta
ry
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control. The third area is reserved for the
LCD Memory. This special area of Data Memory is
mapped directly to the LCD display so data written into
this memory area will directly affect the displayed data.
The addresses of the LCD Memory area overlap those
in the other Memory areas, switching between the two
areas is achieved by setting the Bank Pointer to the correct value.
0 0 H
1 F H
B a n k 1
L C D
M e m o ry
F F H
The Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of
each memory section is dictated by the type of
microcontroller chosen. The start address of the Data
Memory for all devices is the address 00H. Registers
which are common to all microcontrollers, such as ACC,
PCL, etc., have the same Data Memory address. The
LCD Data Memory is mapped into Bank 1 of the Data
Memory, however, only the lower four bits are used. The
higher four bits, if read by the program will return a zero
value. The start of LCD Data Memory for all devices is
the address 40H. However, since the LCD Data Memory
is located in Bank 1, to access this area the Bank
Pointer must first be set to a value of 01H. Note that after
power-on the contents of the Data Memory, including
4 0 H
5 F H
6 0 H
B a n k 0
G e n e ra l
P u rp o s e
D a ta
M e m o ry
Structure
6 0 H
B a n k 0
B a n k 1
Data Memory Structure
Note:
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
t h r ough t h e m em or y p o i nt er r e g i st e r s
Rev. 1.10
10
March 30, 2014
HT49RA1/HT49CA1
stored. Most of the registers are both readable and
writable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
the LCD Data Memory, will be in an unknown condition,
the programmer must therefore ensure that the Data
Memory is properly initialised.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory. As the General Purpose Data Memory
exists in Bank 0, it is necessary to first ensure that the
Bank Pointer is set to the correct value before accessing
the General Purpose Data Memory. When the Bank
Pointer is set to the value 01H, the LCD Memory will be
accessed. Bank 1must be addressed indirectly using
the Memory Pointer MP1 and the indirect addressing
register IAR1. Any direct addressing or any indirect addressing using MP0 and IAR0 will always result in data
from Bank 0 being accessed.
LCD Memory
The data to be displayed on the LCD is also stored in an
area of fully accessible Data Memory. By writing to this
area of RAM, the LCD display output can be directly controlled by the application program. As the LCD Memory
exists in Bank 1, but have addresses which map into the
Bank 0 Data Memory, it is necessary to first ensure that
the Bank Pointer is set to the value 01H before accessing
the LCD Memory. The LCD Memory can only be accessed indirectly using the Memory Pointer MP1 and the
indirect addressing register IAR1. When the Bank Pointer
is set to Bank 1 to access the LCD Data Memory.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory begins at the address ²00H². Any unused Data Memory locations between these special function registers and the
point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to
read data from these locations will return a value of
²00H².
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
IA R 0
M P 0
IA R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
IN T C 0
T M R
T M R
T M R
T M R
T M R
P A
Indirect Addressing Register - IAR0, IAR1
The IAR0 and IAR1 registers, located at Data Memory
addresses ²00H² and ²02H², are not physically implemented. These special function registers allows what is
known as indirect addressing, which permits data manipulation using Memory Pointers instead of the usual
direct memory addressing method where the actual
memory address is defined. Any actions on the IAR0
and IAR1 registers will result in corresponding
read/write operations to the memory locations specified
by the Memory Pointers MP0 and MP1. Reading the
IAR0 and IAR1 registers indirectly will return a result of
²00H² and writing to the register indirectly will result in
no operation.
0
0 C
1 H
1 L
1 C
P B
P C
P C C
P D
IN T C 1
L C D C
: U n u s e d , re a d a s "0 0 "
Special Purpose Data Memory
Rev. 1.10
11
March 30, 2014
HT49RA1/HT49CA1
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in
the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which
to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual
address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together
with Indirect Addressing Register, IAR0, are used to access data from Bank0, while MP1 and IAR1 are used to access
data from Bank0 and Bank1.
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Bank Pointer - BP
should be noted that the Special Function Data Memory
is not affected by the bank selection, which means that
the Special Function Registers can be accessed from
within either Bank 0 or Bank 1.
In the Data Memory area it should be noted that both the
LCD Memory and the other Data Memory share the
same addresses. Therefore when using instructions to
access the LCD Memory or the General Purpose Data
Memory, it is necessary to ensure that the correct area is
selected. The General Purpose is located in Bank 0
while the LCD Memory is located in Bank 1. Selecting
the correct Data Memory area is achieved by using the
Bank Pointer. If data in Bank 0 is to be accessed then BP
should be cleared to zero, while if the LCD Memory is to
be accessed, which is located in Bank 1, then BP should
be loaded with a value of 01H. It must be noted that data
in Bank 1can only be accessed indirectly using the MP1
Memory Pointer and the IAR1 indirect addressing register. Any direct addressing or any indirect addressing using MP0 and IAR0 will always result in data from Bank 0
being accessed. The Data Memory Bank Pointer is initialised to Bank 0 after a reset, except for the WDT
time-out reset in the Power Down Mode, in which case,
the Data Memory Bank Pointer remains unchanged. It
Accumulator - ACC
The Accumulator is central to the operation of any and
is closely related with operations carried out by the ALU.
The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator
it would be necessary to write the result of each calculation or logical operation such as addition, subtraction,
shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of
the Accumulator; for example, when transferring data
between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is
permitted.
b 7
b 0
B P 0
B P R e g is te r
B P 0
0
1
D a ta M e m o ry
B a n k 0
B a n k 1 L C D M e m o ry
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer Register
Rev. 1.10
12
March 30, 2014
HT49RA1/HT49CA1
Program Counter Low Register - PCL
²HALT² or ²CLR WDT² instruction or during a system
power-up.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
¨
C is set if an operation results in a carry during an
addition operation or if a borrow does not take place
during a subtraction operation; otherwise C is
cleared. C is also affected by a rotate through carry
instruction.
¨
AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high
nibble into the low nibble in subtraction; otherwise
AC is cleared.
¨
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
¨
OV is set if an operation results in a carry into the
highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
¨
PDF is cleared by a system power-up or executing
the ²CLR WDT² instruction. PDF is set by executing
the ²HALT² instruction.
¨
TO is cleared by a system power-up or executing
the ²CLR WDT² or ²HALT² instruction. TO is set by
a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
Real Time Clock Control Register - RTCC
The RTCC register controls two internal functions one of
which is the Real Time Clock (RTC) interrupt, whose
function is to provide an internal interrupt signal at regular fixed intervals. The driving clock for the RTC interrupt
comes from the internal clock source, known as fS,
which is then further divided to give longer time values,
which in turn generates the interrupt signal. The value of
this division ratio is determined by the value programmed into bits 2~0, known as RT2~RT0, of the
RTCC register. By writing a value directly into these
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.10
13
March 30, 2014
HT49RA1/HT49CA1
b 7
L V D O
Q O S C
L V D C
R T 2
R T 1
b 0
R T 0
R e a l T im e C lo c k C o n tr o l R e g is te r
R T C In te r r u p t P e r io d
R T 0
R T 1
R T 2
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
P e r io d
2 8/fS
2 9/fS
2 10/fS
2 11/fS
2 12/fS
2 13/fS
2 14/fS
2 15/fS
L o w V o lta g e D e te c to r C o n tr o l
1 : e n a b le
0 : d is a b le
R T C O s c illa to r Q u ic k - s ta r t
1 : d is a b le
0 : e n a b le
L o w V o lta g e D e te c to r O u tp u t
1 : lo w v o lta g e d e te c te d
0 : n o r m a l v o lta g e
N o t im p le m e n te d , r e a d a s " 0 "
RTCC Register
RTCC register bits, time-out values from 28/fS to 215/fS
can be generated. The RTCC register also controls the
quick start up function of the RTC oscillator. This oscillator, which has a fixed frequency of 32768Hz, can be
made to start up at a quicker rate by setting bit 4, known
as the QOSC bit to ²0². This bit will be set to a ²0² value
when the device is powered on, however, as some extra
power is consumed, the QOSC bit should be set to ²1²
after about 2 seconds to reduce power consumption.
the interrupt enable bits on or off. This bit is cleared
when an interrupt routine is entered to disable further interrupt and is set by executing the ²RETI² instruction.
LCDC Register - LCDC
The LCDC register is used as the control register for the
LCD panel. The LCDEN bit is the overall on/off control
for the LCD driver and can be used to power down the
driver and thus used to conserve power when the LCD is
not used. As four segment lines are also pin-shared with
four Port PD lines, bits SEGPT0~SEGPT3 in the LCDC
register are used to determine which function is chosen,
either LCD segment line or normal I/O line. This register
also contains a bit to control the RTC on/off enable. The
RTC on/off control is however also dependent upon
which clock is chosen as the internal fs clock source.
The accompanying table shows the overall RTC control
operation.
Interrupt Control Register - INTC0, INTC1
These 8-bit registers, known as INTC0 and INTC1, control the operation of both the external and internal interrupts. By setting various bits within these registers using
standard bit manipulation instructions, the enable/disable function of the external interrupts and each of the
internal interrupts can be independently controlled. A
master interrupt bit within these registers, the EMI bit,
acts like a global enable/disable and is used to set all of
LCDEN and RTCEN may decide LCD and RTC On/Off condition on normal operation.
fS Clock
Source
LCD/RTC Control Bits
LCDEN, RTCEN=0, 0
LCDEN, RTCEN=0, 1
LCDEN, RTCEN=1, 0
LCDEN, RTCEN=1, 1
fSYS/4
LCD off, RTC off
LCD off, RTC off
LCD on, RTC off
LCD on, RTC off
WDT OSC
LCD off, RTC off
LCD off, RTC off
LCD on, RTC off
LCD on, RTC off
RTC OSC
(WDT enable)
LCD off, RTC on
LCD off, RTC on
LCD on, RTC on
LCD on, RTC on
RTC OSC
(WDT disable)
LCD off, RTC off
LCD off, RTC on
LCD on, RTC on
LCD on, RTC on
Rev. 1.10
14
March 30, 2014
HT49RA1/HT49CA1
Timer/Event Counter 0/1 Registers TMR0, TMR0C, TMR1H, TMR1L, TMR1C
Port C and Port D and the input Port is known as Port B.
These ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data
Memory table. The Port A and Port D I/O ports can be
used for both input and output operations, however, it
must be noted that unlike Port C, they do not have port
control registers. Setting up an PA or PD port pin as an
input is achieved by first setting its output high which effectively places its NMOS output transistor in a high impedance state allowing the pin to be now used as an
input.
All devices possess a single internal 8-bit count-up
timer. An associated register known as TMR0 is the location where the timer¢s 8-bit value is located. This register can also be preloaded with fixed data to allow
different time intervals to be setup. An associated control register, known as TMR0C, contains the setup information for this timer, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
For input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
All devices possess a single internal 16-bit count-up
timer. An associated register known as TMR1H, TMR1L
is the location where the timer¢s 16-bit value is located.
This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated
control register, known as TMR1C, contains the setup
information for this timer, which determines in what
mode the timer is to be used as well as containing the
timer on/off control function.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all pins on Port A, Port B and Port D have a
permanently connected pull high resistor. The pull high
resistor on Port C is chosen via a configuration option.
These pull-high resistors are implemented using a weak
PMOS transistor.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC and PD. These
labeled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output
or input data on that port. One flexible feature of these
registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The PC
port also has a control register known as PCC, and has
the ability to change its I/O pin from output to input and
vice versa by manipulating the bit in the register.
Port B Wake-up
The device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port B pins from high to
low. After a ²HALT² instruction forces the microcontroller
into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition
of the selected wake-up pin on Port B changes from high
to low. This function is especially suitable for applications that can be woken up via external switches. Note
that each pin on Port B can be selected individually to
have this wake-up feature.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. Although Port B remains fixed as an input
only port, all pins on Port A, Port C and Port D, have the
ability to function as either input or output.
The device provides 13 bidirectional input/output lines
and 8 input lines. The I/O Ports are known as Port A,
V
V
D D
W e a k
P u ll- u p
D a ta B u s
W r ite
D
C K
S
D a ta B u s
S y s te m
Q
IN T
IN T
T M R /T M R
T M R
C h ip R e s e t
R e a d I/O
W a k e -u p
0 fo
1 fo
0 fo
1 fo
r P B
r P B
r P B
r P B
W a k e - u p O p tio n
0
1
2
3
PB Input Port
PA, PD Input/Output Ports
Rev. 1.10
P B 0 ~ P B 7
R e a d I/O
P A 0 ~ P A 7
P D 0 ~ P D 3
Q
D D
W e a k
P u ll- u p
15
March 30, 2014
HT49RA1/HT49CA1
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
D D
S
Q
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P C 0 /R E M
D a ta B it
Q
D
Q
C K
S
M
R E M 1
M
R e a d D a ta R e g is te r
U
U
X
P C 0 /R E M
S e le c t
X
PC0 Input/Output Port
· External Timer Clock Input
I/O Port Control Registers
The external timer pin TMR0 or TMR1 are pin-shared
with the I/O pin PB2 or PB3. To configure it to operate
as a timer input, the corresponding control bits in the
timer control register must be correctly set. For applications that do not require an external timer input, the
pin can be used as a normal I/O pin. Note that if used
as a normal I/O pin the timer mode control bits in the
timer control register must select the timer mode,
which has an internal clock source, to prevent the input pin from interfering with the timer operation.
The register PCC is used to control the input/output configuration of port PC. With this control register, this single CMOS output or input with or without pull-high
resistor structures can be reconfigured dynamically under software control. The pin of the Port C I/O port is directly mapped to a bit in its associated PCC port control
register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a
²1². This will then allow the logic state of the input pin to
be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O
pin will be setup as a CMOS output. If the pin is currently
setup as an output, instructions can still be used to read
the output register. However, it should be noted that the
program will in fact only read the status of the output
data latch and not the actual logic status of the output
pin.
I/O Pin Structures
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied as
a guide only to assist with the functional understanding
of the I/O pins.
Programming Considerations
Pin-shared Functions
Within the application program, one of the first things to
consider is port initialization. After a reset,the I/O port
registers will be set high. It is important to note that for
the NMOS types, when set high the output NMOS transistor will be placed into a high impedance condition, allowing the pin to be used also as an input. The
generation of a high level on the NMOS outputs therefore is reliant upon externally connected circuitry and
the pull-high resistor.
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
T 1
S y s te m
· External Interrupt Input
The external interrupt pin INT0 or INT1 are pin-shared
with the I/O pin PB0 or PB1. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin,
however to do this, the external interrupt enable bits in
the INTC0 register must be disabled.
Rev. 1.10
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
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March 30, 2014
HT49RA1/HT49CA1
When using the pin as an output, its logic level can be
setup by loading byte wide data into the appropriate port
register or by programming individual bits in these registers, using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports. However, in the
case of NMOS type pins, there are some special considerations that must be noted. In the case of an NMOS pin
that is set high by the microcontroller, i.e. placed into a
high impedance condition, but driven low by externally
connected circuitry, this pin would be read as being in a
low condition during the read phase of the ²SET [m].i
and ²CLR [m].i² instructions. When the ensuing write
phase occurs, this pin, having been read as being in a
low condition during the read phase, would then be consequently erroneously set low. For this reason great
care must be taken when using these bit control instructions with NMOS output types.
required, which vary in both amplitude and time, to drive
such a custom display require many special considerations for proper LCD operation to occur. This device includes internal LCD signal generating circuitry and
various configuration options, which will automatically
generate these time and amplitude varying signals to
provide a means of direct driving and easy interfacing to
a range of custom LCDs.
LCD Memory
The device provides a specific area of Data Memory for
the LCD data. This data area is known as the LCD Memory. Any data written here will be automatically read by
the internal LCD driver circuits, which will in turn automatically generate the necessary LCD driving signals.
Therefore any data written into the LCD Memory will be
immediately reflected into the actual LCD display connected to the microcontroller. The start address of the
LCD Memory is 40H, the end address of the LCD Memory is 60H.
As the LCD Data Memory addresses overlap those of
the General Purpose Data Memory, the LCD Data Memory is stored in its own memory data bank, which is different from that of the General Purpose Data Memory.
Port B has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
B pins. Single or multiple pins on Port B can be setup to
have this function.
The LCD Data Memory is stored in Bank 1. The Data
Memory Bank is chosen by using the Bank Pointer,
which is a special function register in the Data Memory,
with the name, BP. When the lowest bit of the Bank
Pointer have the binary value ²0², only the General Purpose Data Memory will be accessed, no read or write
actions to the LCD Memory will take place. To access
the LCD Memory therefore requires first that Bank 1 is
selected by setting the lowest bit of the Bank Pointer to
Liquid Crystal Display (LCD) Driver
For large volume applications, which incorporate an
LCD in their design, the use of a custom display rather
than a more expensive character based display reduces
costs significantly. However, the corresponding signals
b 7
S E G P T 3
b 0
S E G P T 2
S E G P T 1
L C D E N
S E G P T 0
R T C E N
L C D C
R e g is te r
R T C O s c illa to r E n a b le
1 : e n a b le
0 : d is a b le
L C D E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
S E G 0 /P D 0 p in fu n c tio n
1 : P D 0
0 : S E G 0
S E G 1 /P D 1 p in fu n c tio n
1 : P D 1
0 : S E G 1
S E G 2 /P D 2 p in fu n c tio n
1 : P D 2
0 : S E G 2
S E G 3 /P D 3 p in fu n c tio n
1 : P D 3
0 : S E G 3
LCD Control Register - LCDC
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
b 7
b 6
b 5
b 4
b 3
b 2
b 1
b 0
b 7
b 6
b 5
b 4
b 3
b 2
b 1
b 0
4 0 H
S E G
0
4 0 H
S E G
0
4 1 H
S E G
1
4 1 H
S E G
1
: U n u s e d
R e a d a s "0 "
5 F H
S E G
3 1
5 F H
S E G
3 1
6 0 H
S E G
3 2
6 0 H
S E G
3 2
C O M
C O M
1
2
3
C O M
C O M
1
0
C O M
2
C O M
C O M
0
(1 /4 D u ty )
(1 /2 o r 1 /3 D u ty )
LCD Memory Map
the binary value ²1². After this, the LCD Memory can
then be accessed by using indirect addressing through
the use of Memory Pointer MP1. With Bank 1 selected,
then using MP1 to read or write to the memory area,
40H~60H, depending upon which device is chosen, will
result in operations to the LCD Memory. Directly addressing the LCD Memory is not applicable and will result in a data access to the Bank 0 General Purpose
Data Memory.
divider, to provide an LCD clock source frequency as
near as possible to 4kHz.
LCD Clock Selection
WDT Oscillator
WDT/22
RTC Oscillator
RTC/23
fSYS/4
fS
/4
Y S
2
2
~
fS
/4
Y S
2
8
LCD Clock Frequency Selection
The accompanying diagrams show the LCD Memory
Map for the 33´2, 33´3 or 32´4 format pixel drive capability. The 4-COM format will be automatically setup if
the 1/4 duty configuration option is selected while the
3-COM format will be automatically setup if the 1/2 or
1/3 duty configuration option is selected.
The available division ratios, however, depends on the
clock source that is used for the internal clock source, fS.
If the clock source for fS originates from the WDT oscillator, then only a fixed division ratio of fS/22 is available. If
the clock source for fS originates from the RTC oscillator, then only one division ratio of fS/23 is available. However, if the clock source for fS originates from fSYS/4,
then a range of LCD clock frequencies are available
from fS/22 to fS/28, the value of which is selected by a further available configuration option. These ratios ensure
that for proper LCD operation, a signal frequency as
near as possible to 4kHz, can be selected. For an LCD
clock frequency of 4kHz, the microcontroller LCD driver
circuitry will generate an LCD frame frequency between
55Hz and 62Hz. This is in line with the general LCD operating frequency range which lies between 25Hz and
250Hz. Note that if the selected LCD clock frequency is
too high, this will result in a higher than required frame
frequency and give rise to higher power consumption
while selecting a too low frequency may result in flicker.
It is therefore important that if fSYS/4 is used as the clock
source for fS, the correct configuration option should be
chosen to obtain an LCD clock frequency as close to
4kHz as possible.
LCD Control Register - LCDC
The device contains a single register known as, LCDC,
which is used to control some internal LCD driver functions. The LCDEN bit is the overall on/off control for the
LCD driver and can be used to power down the driver
and thus used to conserve power when the LCD is not
used. As four segment lines are also pin-shared with
four Port PD lines, bits SEGPT0~SEGPT3 in the LCDC
register are used to determine which function is chosen,
either LCD segment line or normal I/O line.
LCD Clock
The LCD clock is driven by the internal clock source fS,
which can originate from either the WDT oscillator, the
RTC oscillator or fSYS/4, the choice of which is determined by a configuration option. For proper LCD operation, this fS internal clock source then passes through a
Rev. 1.10
fS Clock Source
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March 30, 2014
HT49RA1/HT49CA1
LCD Driver Output
voltage on the COM pin minus the voltage applied to the
SEG pin. This differential RMS voltage must be greater
than the LCD saturation voltage for the pixel to be on
and less than the threshold voltage for the pixel to be off.
The requirement to limit the DC voltage to zero and to
control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and applied to the application
LCD. These time and amplitude varying signals are automatically generated by the LCD driver circuits in the
microcontroller. What is known as the duty determines
the number of common lines used, which are also
known as backplanes or COMs. The duty, which is chosen by a configuration option to have a value of 1/2, 1/3
or 1/4 and which equates to a COM number of 2, 3 and 4
respectively, therefore defines the number of time divisions within each LCD signal frame. The accompanying
timing diagrams depict the LCD signals generated by
the microcontroller for various values of duty and bias.
The number of COM and SEG outputs supplied by the
LCD driver, as well as its biasing and duty options, are
dependent upon the configuration options selected. The
accompanying table lists the various options for each of
the devices.
Duty
Driver
Number
Bias
Bias
Type
1/2
33´2
1/2 or 1/3
C type
1/3
33´3
1/2 or 1/3
C type
1/4
32´4
1/2 or 1/3
C type
LCD Driver Outputs, Duty and Bias Options
The nature of Liquid Crystal Displays require that only
AC voltages can be applied to their pixels as the application of DC voltages to LCD pixels will cause permanent
damage. For this reason the relative contrast of an LCD
display is controlled by the actual RMS voltage applied
to each pixel, which is equal to the RMS value of the
D u r in g R e s e t o r in H A L T M o d e
V A
V B
C O M 0 , C O M 1
V S S
V A
V B
V S S
A ll s e g m e n t o u tp u ts
1 F ra m e
N o r m a l O p e r a tio n M o d e
V A
C O M 0
V B
V S S
V A
V B
V S S
V A
V B
V S S
C O M 1
A ll s e g m e n ts O F F
V A
V B
C O M 0 s e g m e n ts O N
V S S
V A
C O M 1 s e g m e n ts O N
V B
V S S
V A
V B
V S S
A ll s e g m e n ts O N
LCD Driver Output (1/2 Duty, 1/2 Bias)
Note
For 1/2 Bias, the VA=VLCD and VB=VLCD´1/2
The LCD function can be optioned as on or off during the Power Down Mode by a configuration option.
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
D u r in g R e s e t o r in H A L T M o d e
V A
V B
C O M 0 , C O M 1 , C O M 2
V S S
V A
V B
V S S
A ll s e g m e n t o u tp u ts
N o r m a l O p e r a tio n M o d e
1 F ra m e
V A
V B
C O M 0
V S S
V A
C O M 1
V B
V S S
V A
V B
V S S
V A
V B
V S S
V A
V B
V S S
C O M 2
A ll s e g m e n ts O F F
C O M 0 s e g m e n ts O N
V A
V B
C O M 1 s e g m e n ts O N
V S S
V A
C O M 2 s e g m e n ts O N
V B
V S S
V A
V B
C O M 0 , 1 s e g m e n ts O N
V S S
V A
C O M 0 , 2 s e g m e n ts O N
V B
V S S
V A
C O M 1 , 2 s e g m e n ts O N
V B
V S S
V A
A ll s e g m e n ts O N
V B
V S S
LCD Driver Output (1/3 Duty, 1/2 Bias)
Note:
For 1/2 Bias, the VA=VLCD and VB=VLCD´1/2
The LCD function can be optioned as on or off during the Power Down Mode by a configuration option.
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
D u r in g R e s e t o r in H A L T M o d e
V A
V B
C O M 0 , C O M 1 , C O M 2 , C O M 3
V C
A ll s e g m e n t o u tp u ts
1 F ra m e
N o r m a l O p e r a tio n M o d e
V S S
V A
V B
V C
V S S
V A
V B
C O M 0
V C
V S S
V A
V B
C O M 1
V C
V S S
V A
V B
V C
V S S
C O M 2
V A
V B
C O M 3
V C
V S S
V A
V B
A ll s e g m e n ts O F F
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
C O M 0 s e g m e n ts O N
C O M 1 s e g m e n ts O N
V A
V B
C O M 2 s e g m e n ts O N
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
C O M 3 s e g m e n ts O N
C O M 0 , 1 s e g m e n ts O N
C O M 0 , 2 s e g m e n ts O N
C O M 0 , 3 s e g m e n ts O N
( o th e r c o m b in a tio n s a r e o m itte d )
V A
V B
A ll s e g m e n ts O N
V C
V S S
LCD Driver Output (1/4 Duty, 1/3 Bias)
Note:
For 1/3 bias VA=VLCD´1.5, VB=VLCD and VC=VLCD´1/2.
The LCD function can be optioned as on or off during the Power Down Mode by a configuration option.
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
D u r in g R e s e t o r in H A L T M o d e
V A
V B
C O M 0 , C O M 1 , C O M 2
V C
A ll s e g m e n t o u tp u ts
1 F ra m e
N o r m a l O p e r a tio n M o d e
V S S
V A
V B
V C
V S S
V A
V B
C O M 0
V C
V S S
V A
V B
C O M 1
V C
V S S
V A
V B
V C
V S S
C O M 2
V A
V B
A ll s e g m e n ts O F F
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
C O M 0 s e g m e n ts O N
C O M 1 s e g m e n ts O N
V A
V B
C O M 2 s e g m e n ts O N
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
V A
V B
V C
V S S
C O M 0 , 1 s e g m e n ts O N
C O M 0 , 2 s e g m e n ts O N
C O M 1 , 2 s e g m e n ts O N
A ll s e g m e n ts O N
LCD Driver Output (1/3 Duty, 1/3 Bias)
Note:
For 1/3 bias the VA=VLCD´1.5, VB=VLCD and VC=VLCD´1/2.
The LCD function can be optioned as on or off during the Power Down Mode by a configuration option.
Rev. 1.10
22
March 30, 2014
HT49RA1/HT49CA1
LCD Voltage Source and Biasing
generally modeled as mainly capacitive in nature, it is
important that this is not excessive, a point that is particularly true in the case of the COM lines which may be
connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD.
The time and amplitude varying LCD signals generated
by the microcontroller require the generation of several
voltage levels for their operation. The number of voltage
levels used by the signal depends upon device and the
chosen bias configuration options.
S E G 0
The device has a configuration option to select either
1/2 or 1/3 bias. For the 1/2 bias configuration option,
three voltage levels VSS, VA and VB are utilised. VB is
generated internally by the microcontroller and will have
a value equal to VLCD/2. For the 1/3 bias option, four
voltage levels VSS, VA, VB and VC are utilised. An external LCD voltage source is also provided on pin VLCD
to generate these voltages. As the C type bias option
uses a charge pump circuit, higher voltages than what is
provided externally on VLCD can be generated. This
f e a t u re i s us e f u l i n a p p l i c at i o n s w he r e t h e
microcontroller supply voltage is less than the supply
voltage required by the LCD.
C O M 2
C O M 3
LCD Panel Equivalent Circuit
Setting the correct frequency of the LCD clock is another factor which must be taken into account in user applications. To have the LCDs operate at their best frame
frequency, which is normally between 25Hz and 250Hz,
it is important to select an appropriate LCD clock frequency configuration option. The correct option should
be chosen to ensure that an LCD clock frequency as
close to 4kHz as possible is achieved. With such a frequency chosen, the microcontroller internal LCD driver
circuits will ensure that the appropriate LCD driving signals are generated to obtain a suitable LCD frame frequency.
Programming Considerations
Certain precautions must be taken when programming
the LCD. One of these is to ensure that the LCD memory
is properly initialized after the microcontroller is powered on. Like the General Purpose Data Memory, the
contents of the LCD memory are in an unknown condition after power-on. As the contents of the LCD memory
will be mapped into the actual LCD, it is important to initialize this memory area into a known condition soon after applying power to obtain a proper display pattern.
Note that as the LCD driver will consume a certain
amount of power it can be disabled using the LCDEN bit
in the LCDC register. In battery applications where
power consumption is an important consideration to
prolong battery life, this bit should be used to power
down the LCD circuitry to conserve power.
Consideration must also be given to the capacitive load
of the actual LCD used in the application. As the load
presented to the microcontroller by LCD pixels can be
V L C D
A
C 1
(= V L C D ´ 1 .5 )
V
B
C h a rg e
P u m p
C 2
V L C D
L C D
P o w e r S u p p ly
V
C
(= V L C D ´ 0 .5 )
C
C 1
A
(= V L C D )
0 .1 m F
V 1
V
0 .1 m F
V
S E G n
C O M 1
As the LCD driver has a C type bias, a charge-pump capacitor between pins C1 and C2 and filter capacitors on
pins V1 and V2 are required to generate the necessary
voltage levels.
(= V L C D )
S E G 2
C O M 0
LCD Biasing
V
S E G 1
C 2
0 .1 m F
0 .1 m F
V 1
0 .1 m F
B
(= V L C D ´ 0 .5 )
V 2
C h a rg e
P u m p
L C D
P o w e r S u p p ly
V 2
0 .1 m F
ty p e 1 /3 B ia s
C ty p e 1 /2 B ia s
C Type Bias Voltage Levels
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
Timer/Event Counters
upon which timer is used. Depending upon the condition
of the T0E or T1E bit, each high to low, or low to high
transition on the external timer pin will increment the
counter by one.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The devices contain one
8-bit and one 16-bit count-up timers. As each timer has
three different operating modes, they can be configured
to operate as a general timer, an external event counter
or as a pulse width measurement device.
Timer Registers - TMR0, TMR1H, TMR1L
The timer registers are special function registers located in
the Special Purpose Data Memory and is the place where
the actual timer value is stored. These registers are known
as TMR0, TMR1H or TMR1L, depending upon which device is used. The value in the timer registers increases by
one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer
will count from the initial value loaded by the preload register to the full count of FFH or FFFFH at which point the
timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial
preload register value and continue counting.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register
retrieves the contents of the Timer/Event Counter. The
second type of associated register is the Timer Control
Register which defines the timer options and determines how the timer is to be used. All devices can have
the timer clock configured to come from the internal
clock source. In addition, the timer clock source can also
be configured to come from an external timer pin.
Note that to achieve a maximum full range count of FFH
or FFFFH, the preload register must first be cleared to
all zeros. It should be noted that after power-on, the
preload registers will be in an unknown condition. Note
that if the Timer/Event Counters are in an OFF condition
and data is written to their preload registers, this data
will be immediately written into the actual counter. However, if the counter is enabled and counting, any new
data written into the preload data registers during this
period will remain in the preload registers and will only
be written into the actual counter the next time an overflow occurs.
Configuring the Timer/Event Counter Input Clock
Source
The internal timer¢s clock can originate from various
sources, depending upon which timer is chosen. The
system clock input timer source is used when the timer
is in the timer mode or in the pulse width measurement
mode.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on an external timer pin TMR0 or TMR1, depending
D a ta B u s
P r e lo a d R e g is te r
fS
R T C
fS
Y S
Y S
/4
M
O p tio n
S e le c t
In te rru p t
U
T 0 M 1
T 0 M 0
X
T im e r /E v e n t
C o u n te r
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 0 S
T M R 0
R e lo a d
T 0 O N
T 0 E
O v e r flo w
to In te rru p t
8 - B it T im e r /E v e n t C o u n te r
Timer/Event Counter 0 Structure
D a ta B u s
L o w B y te
B u ffe r
fS Y S /4
3 2 7 6 8 H z
M
U
X
T 1 M 1
1 6 - B it
P r e lo a d R e g is te r
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 1 S
T M R 1
H ig h B y te
T 1 O N
L o w
B y te
1 6 - B it T im e r /E v e n t C o u n te r
R e lo a d
O v e r flo w
to In te rru p t
T 1 E
Timer/Event Counter 1 Structure
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
pair T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON or T1ON, depending upon which timer is used, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. If
the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control
Register which is known as T0E or T1E depending upon
which timer is used.
For the 16-bit Timer/Event Counter which has both low
byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted
when using instructions to preload data into the low byte
timer register, namely TMR1L, the data will only be
placed in a low byte buffer and not directly into the low
byte timer register. The actual transfer of the data into
the low byte timer register is only carried out when a
write to its associated high byte timer register, namely
TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will
result in the data being directly written to the high byte
timer register. At the same time the data in the low byte
buffer will be transferred into its associated low byte
timer register. For this reason, the low byte timer register
should be written first when preloading data into the
16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the
high byte timer register must be executed first to latch
the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low
byte timer register can be read in the normal way. Note
that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer
and not the actual contents of the low byte timer register.
Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, the
bit pair, T0M1/T0M0 or T1M1/T1M0 depending upon
which timer is used, must be set to 1 and 0 respectively.
In this mode the internal clock is used as the timer clock.
The timer-on bit, T0ON or T1ON, depending upon which
timer is used, must be set high to enable the timer to run.
Each time an internal clock high to low transition occurs,
the timer increments by one; when the timer is full and
overflows, an interrupt signal is generated and the timer
will preload the value already loaded into the preload
register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the
wake-up sources, however, the internal interrupts can
be disabled by ensuring that the ET0I or ET1I bits of the
INTC0, INTC1 register are reset to zero.
Timer Control Registers - TMR0C, TMR1C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
It is the Timer Control Register together with its corresponding timer registers that control the full operation of
the Timer/Event Counters. Before the timers can be
used, it is essential that the appropriate Timer Control
Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be recorded by the internal timer. For the timer to operate in
the event counting mode, the bit pair, T0M1/T0M0 or
T1M1/T1M0 depending upon which timer is used, must
be set to 0 and 1 respectively. The timer-on bit T0ON or
T1ON depending upon which timer is used, must be set
high to enable the timer to count. Depending upon which
counter is used, if T0E or T1E is low, the counter will increment each time the external timer pin receives a low
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
Rev. 1.10
25
March 30, 2014
HT49RA1/HT49CA1
to high transition. If T0E or T1E is high, the counter will
increment each time the external timer pin receives a
high to low transition. As in the case of the other two
modes, when the counter is full, the timer will overflow
and generate an internal interrupt signal. The counter
will then preload the value already loaded into the
preload register. As the external timer pins are
pin-shared with other I/O pins, to ensure that the pin is
configured to operate as an event counter input pin, two
things have to happen. The first is to ensure that the
b 7
T 0 M 1
T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event
Counter in the event counting mode, the second is to ensure that the port control register configures the pin as
an input. It should be noted that a timer overflow is one
of the interrupt and wake-up sources. Note that the timer
interrupts can be disabled by ensuring that the ET0I or
ET1I bits in the INTC0 or INTC1 register are reset to
zero.
b 0
T 0 M 0
T 0 S
T 0 O N
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
T M R 0 C
T 0 E
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C
1 : c o u n
0 : c o u n
P u ls e W
1 : s ta rt
0 : s ta rt
o u n te r a c tiv e e d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e s e le c t
t a c tiv e e d g e s e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1 : o p tio n c lo c k s o u r c e
0 : R T C in te r r u p t
O p e r a tin
T 0 M 1 T
0
0
1
1
g m o d e
0 M 0
n o
0
e v
1
tim
0
p u
1
s e le c t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register - TMR0C
b 7
T 1 M 1
b 0
T 1 M 0
T 1 S
T 1 O N
T 1 E
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
T M R 1 C
N o t im p le m e n te d , r e a d a s " 0 "
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n
t o n
t o n
id th
c o u n
c o u n
te r a c tiv e e d g
fa llin g e d g e
r is in g e d g e
M e a s u re m e n
tin g o n r is in g
tin g o n fa llin g
e s e le c t
t a c tiv e e d g e s e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1 : 3 2 7 6 8 H z
0 : fS Y S /4
O p e r a tin g m o d e
T 1 M 1 T 1 M 0
n o
0
0
e v
0
1
1
tim
0
1
1
p u
s e le c t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register - TMR1C
Rev. 1.10
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HT49RA1/HT49CA1
Configuring the Pulse Width Measurement Mode
is to ensure that the port control register configures the
pin as an input. It should be noted that a timer overflow
and corresponding timer interrupt is one of the wake-up
sources. Note that the timer interrupts can be disabled
by ensuring that the ET0I or ET1I bits in the INTC0 or
INTC1 register are reset to zero.
In this mode, the width of external pulses applied to the
external timer pin can be measured. In the Pulse Width
Measurement Mode the timer clock source is supplied
by the internal clock. For the timer to operate in this
mode, the bit pair, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must both be set high. Depending upon which counter is used, if the T0E or T1Ebit
is low, once a high to low transition has been received
on the external timer pin, the timer will start counting until the external timer pin returns to its original high level.
At this point the T0ON or T1ON bit, depending upon
which counter is used, will be automatically reset to zero
and the timer will stop counting. If the T0E or T1E bit is
high, the timer will begin counting once a low to high
transition has been received on the external timer pin
and stop counting when the external timer pin returns to
its original low level. As before, the T0ON or T1ON, bit
will be automatically reset to zero and the timer will stop
counting. It is important to note that in the Pulse Width
Measurement Mode, the T0ON or T1ON bit is automatically reset to zero when the external control signal on
the external timer pin returns to its original level,
whereas in the other two modes the T0ON or T1ON bit
can only be reset to zero under program control. The residual value in the timer, which can now be read by the
program, therefore represents the length of the pulse received on the external timer pin. As the T0ON or T1ON
bit has now been reset, any further transitions on the external timer pin, will be ignored. Not until the T0ON or
T1ON bit is again set high by the program can the timer
begin further pulse width measurements. In this way,
single shot pulse measurements can be easily made. It
should be noted that in this mode the counter is controlled by logical transitions on the external timer pin and
not by the logic level. As in the case of the other two
modes, when the counter is full, the timer will overflow
and generate an internal interrupt signal. The counter
will also be reset to the value already loaded into the
preload register. If the external timer pin is pin-shared
with other I/O pins, to ensure that the pin is configured to
operate as a pulse width measuring input pin, two things
have to happen. The first is to ensure that the
T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event
Counter in the pulse width measuring mode, the second
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, require the use of the external pin for correct operation. As
this pin is a shared pin it must be configured correctly to
ensure it is setup for use as a Timer/Event Counter input
and not as a normal I/O pin. This is implemented by ensuring that the mode select bits in the Timer/Event
Counter control register, select either the event counter
or pulse width measurement mode. Additionally the Port
Control Register must be set high to ensure that the pin
is setup as an input. Any pull-high resistor on this pin will
remain valid even if the pin is used as a Timer/Event
Counter input.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not synch r o n i ze d w i t h t h e i n t e r n a l t i m e r cl o ck, t h e
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be
small differences in measured values requiring programmers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode, which again is an external event
and not synchronised with the internal system or timer
clock.
E x te rn a l T M R 0 /T M R 1
P in In p u t
T 0 O N /T 1 O N
( w ith T 0 E /T 1 E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
Rev. 1.10
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HT49RA1/HT49CA1
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must
be properly set otherwise the internal interrupt associated
with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also
important to ensure that an initial value is first loaded into
the timer registers before the timer is switched on; this is
because after power-on the initial values of the timer registers are unknown. After the timer has been initialised
the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the
timer enable bit high to turn the timer on, should only be
executed after the timer mode bits have been properly
setup. Setting the timer enable bit high together with a
mode bit modification, may lead to improper timer operation if executed as a single timer control register byte
write instruction.
will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a
Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
Timer Program Example
This program example shows how the Timer/Event
Counter registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter to
be in the timer mode, which uses the internal system
clock as the clock source.
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
org 04h
; external interrupt vector
reti
org 0Ch
; Timer/Event Counter 0 interrupt vector
jmp tmrint
; jump here when Timer overflows
:
org 20h
; main program
;internal Timer/Event Counter 0 interrupt routine
tmrint:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
:
begin:
;setup Timer 0 registers
mov a,09bh
; setup Timer 0 preload value
mov tmr0,a;
mov a,080h
; setup Timer 0 control register
mov tmr0c,a
; timer mode
; setup interrupt register
mov a,009h
; enable master interrupt and timer interrupt
mov int0c,a
set tmr0c.4
; start Timer/Event Counter 0 - note mode bits must be previously setup
Rev. 1.10
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HT49RA1/HT49CA1
Carrier Generator
with the following equation the required carrier
frequency can be generated.
Some remote control transmitter applications require a
carrier frequency generator to transmit the remote control signal at the appropriate frequency to the receiving
device. These devices include an internal carrier frequency generator for this purpose, the frequency of
which is specified by selecting the correct configuration
options.
Carrier Frequency =
Clock Source
mx2n
The value of ²m² can be either 2 or 3 while the value of
²n² can range from 0 to 3, both values are chosen by selecting the required configuration options. If ²m² is equal
to ²2² the duty cycle of the output waveform will always
be equal to 1/2. If ²m² is equal to ²3², with the exception
of ²n² being equal to ²0², the duty cycle can be either 1/2
or 1/3, the actual value of which is determined by configuration options.
This carrier signal is supplied on the REM pin, which is
also pin-shared with PC0. The selection of the required
function, whether remote output or CMOS output, is implemented by selecting the required configuration option. If the remote output REM is selected by
configuration option, the REM output will be activated if
the PC0 data bit in the PC register is set to high. This
output data bit is used as the on/off control bit for the
REM output. Note that the REM output will be low if the
PC0 output data bit is set to zero. However, if the line is
configured as a PC0 output pin it will switch to a high
level and remain so until the application program resets
the pin to a zero. It is therefore important to note that, for
OTP devices, if the pin is configured as a PC0 output
pin, and a NPN transistor is connected to this output to
drive an infrared LED, the LED will be turned on during
this power-on reset period. For general purpose remote
controller applications, it is therefore recommended that
the REM configuration option is selected together with
an external NPN transistor to drive the infrared LED.
m´2n
Duty Cycle
2, 4, 8, 16
1/2
3
1/3
6, 12, 24
1/2 or 1/3
The following table shows examples of different carrier
frequencies:
fSYS
fCARRIER
Duty
m´2n
37.92kHz
1/3 only
3
56.9kHz
1/2 only
2
455kHz
The clock source for the Carrier Generator is supplied
by the system clock divided by 4. By selecting values for
²m² and ²n² using configuration options in association
F r e q u e n c y D iv id e r
fS
Y S
/4
3 - b it C o u n te r
C o n fig u r a tio n O p tio n
C a r r ie r
1 /2 o r
C o n fig . O
S e le
D u ty
1 /3
p tio n
c t
C o n fig u r a tio n
O p tio n
S e le c t
R E M /P C 0
P C 0 D a ta R e g is te r
Carrier Signal Generation
Rev. 1.10
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HT49RA1/HT49CA1
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter, Time Base or RTC Interrupt requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the
main program allowing the microcontroller to direct attention to their respective needs. The device contains two
external interrupts and four internal interrupt functions.
The external interrupt is controlled by the action of the external INT0, INT1 pin, while the internal interrupts are
controlled by the two Timer/Event Counter overflows, the
Time Base interrupt and the RTC interrupt.
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Priority
Interrupt Register
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the INTC0 and
INTC1 registers, which are located in the Data Memory.
By controlling the appropriate enable bits in these register each individual interrupt can be enabled or disabled.
Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global
enable flag if cleared to zero will disable all interrupts.
Interrupt Source
Priority
External Interrupt 0/1
1/2
Interrupt Operation
Timer/Event Counter 0/1 Overflow
3/4
A Timer/Event Counter overflow, Time Base or RTC
overflow or the external interrupt line being triggered will
all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program
Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Time Base Interrupt
5
Real Time Clock Interrupt
6
External Interrupt
For an external interrupt to occur, the global interrupt
enable bit, EMI, and external interrupt enable bit, EEI0,
EEI1, must first be set. Additionally the correct interrupt
edge bit must be selected to enable the external interrupt
function and to choose the trigger edge type. An actual
external interrupt will take place when the external
interrupt request flag, EIF0 or EIF1, is set, a situation that
will occur when a transition, whose type is chosen by
configuration option appears on the INT0 and, INT1 pins.
The external interrupt pins are pin-shared with the I/O
pins PB0 and PB1 and can only be configured as an
external interrupt pin if the corresponding external
interrupt enable bit in the INTC0 register have been set.
The pins must also be setup as inputs. When the interrupt
is enabled, the stack is not full and the correct transition
type appears on the external interrupt pin, a subroutine
call to the relevant external interrupt vectors at locations
04H and 08H, will take place. When the interrupt is
serviced, the external interrupt request flag, EIF0, EIF1,
will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts.
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
Rev. 1.10
30
March 30, 2014
HT49RA1/HT49CA1
b 7
b 0
T 0 F
E IF 1
E IF 0
E T 0 I E E I1
E E I0
IN T C 0 R e g is te
E M I
M a s te r in te r r u p t g lo b a l e n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l in te r r u p t 0 e n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l in te r r u p t 1 e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l in te r r u p t 0 r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
E x te r n a l in te r r u p t 1 r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
F o r te s t m o d e u s e d o n ly
M u s t b e w r itte n a s " 0 " ; o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e
Interrupt Control Register INTC0
b 7
b 0
R T F
T B F
T 1 F
E R T I E T B I E T 1 I
IN T C 1 R e g is te r
T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e B a s e in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
R e a l T im e C lo c k in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e B a s e r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
R e a l T im e C lo c k r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register INTC1
Rev. 1.10
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HT49RA1/HT49CA1
Timer/Event Counter Interrupt
Time Base interrupt period, can originate from three different sources, the RTC oscillator, Watchdog Timer oscillator or the System oscillator/4, the choice of which is
determine by the fS clock source configuration option.
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, ET0I, ET1I must first be set. An actual
Timer/Event Counter interrupt will take place when the
relevant Timer/Event Counter request flag, T0F, T1F is
set, a situation that will occur when the relevant
Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 0CH, 10H, will take place. When the interrupt is serviced, the timer interrupt request flag, T0F,
T1F will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Real Time Clock Interrupt
For a Real Time Clock interrupt to occur the global interrupt enable bit, EMI, and the corresponding internal interrupt enable bit, which is bit 2 of the INTC1 register,
known as ERTI, must be first set. An actual Real Time
Clock interrupt will be generated when the Real Time
Clock interrupt request flag is set which is bit 6 of the
INTC1 register and known as RTF. When the master interrupt global enable bit is set, the stack is not full and
the corresponding Real Time Clock interrupt enable bit
is set, an internal Real Time Clock interrupt will be generated when a time-out signal occurs, a subroutine call
to location 018H will be created. When a Real Time interrupt occurs, the EMI bit will be cleared to disable
other interrupts.
Time Base Interrupt
For a Time Base interrupt to occur the the global interrupt enable bit, EMI, and the corresponding internal interrupt enable bit, which is bit 1 of the INTC1 register,
known as ETBI, must be first set. An actual Time Base
interrupt will be generated when the Time Base interrupt
request flag is set which is bit 5 of the INTC1 register
and known as TBF. This will occur when when a time-out
signal is generated from the Time Base. When the master interrupt global enable bit is set, the stack is not full
and the corresponding Time Base interrupt enable bit is
set, an internal Time Base interrupt will be generated
when a time-out signal is generated from the Time Base.
This will create a subroutine call to location 014H. When
a Time Base interrupt occurs, the EMI bit will be cleared
to disable other interrupts. The purpose of the Time
Base interrupt is to provide an interrupt signal at fixed
time periods. The Time Base interrupt clock source originates from the internal clock source fS. This fS input
clock first passes through a divider, the division ratio of
which is selected by configuration options to provide
longer Time Base interrupt periods. The Time Base interrupt time-out period ranges from 212/fS~215/fS. The
clock source that generates fS, which in turn controls the
fS
Y S
/4
W D T O s c illa to r
R T C
O s c illa to r
fS S o u rc e
C o n fig u r a tio n
O p tio n
fS
Similar in operation to the Time Base interrupt, the purpose of the RTC interrupt is also to provide an interrupt
signal at fixed time periods. The RTC interrupt clock
source originates from the internal clock source fS. This
fS input clock first passes through a divider, the division
ratio of which is selected by programming the appropriate bits in the RTCC register to obtain longer RTC interrupt periods whose value ranges from 28/fS~215/fS. The
clock source that generates fS, which in turn controls the
RTC interrupt period, can originate from three different
sources, the RTC oscillator, Watchdog Timer oscillator
or the System oscillator/4, the choice of which is determine by the fS clock source configuration option. Note
that if the RTC oscillator is selected as the system clock,
then fS, and correspondingly the RTC interrupt, will also
have the RTC oscillator as its clock source.
C o n fig u r a tio n O p tio n
D iv id e b y 2 1 2 ~ 2 1 5
T im e B a s e In te r r u p t
2 12/fS ~ 2 15/fS
Time Base Interrupt
fS
Y S
/4
W D T O s c illa to r
R T C O s c illa to r
fS S o u rc e
C o n fig u r a tio n
O p tio n
D iv id e b y 2 8 ~ 2
(S e t b y R T C C
R e g is te r s )
fS
1 5
R T C In te rru p t
2 8/fS ~ 2 15/fS
R T 2 ~ R T 0
RTC Interrupt
Rev. 1.10
32
March 30, 2014
HT49RA1/HT49CA1
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF 0
E E I0
E x te rn a l In te rru p t
R e q u e s t F la g E IF 1
E E I1
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
T im e B a s e
In te r r u p t R e q u e s t F la g T B F
E T B I
R e a l T im e C lo c k
In te r r u p t R e q u e s t F la g R T F
E R T I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
Note that the RTC interrupt period is controlled by both
configuration options and an internal register RTCC. A
configuration option selects the source clock for the internal clock fS, and the RTCC register bits RT2, RT1 and
RT0 select the division ratio. Note that the actual division ratio can be programmed from 28 to 215. For details
of the actual RTC interrupt periods, consult the RTCC
register section.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
Note after a wake-up the system requires 1024 clock cycles to resume normal operation.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Programming Considerations
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC0, INTC1 registers until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
Rev. 1.10
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HT49RA1/HT49CA1
Reset and Initialisation
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
tR
D D
S T D
S S T T im e - o u t
In te rn a l R e s e t
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
V D D
1 0 0 k W
R E S
0 .1 m F
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Reset Functions
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
0 .0 1 m F
V D D
1 0 0 k W
· Power-on Reset
R E S
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
Rev. 1.10
0 .9 V
R E S
1 0 k W
0 .1 m F
V S S
Enhanced Reset Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
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March 30, 2014
HT49RA1/HT49CA1
· RES Pin Reset
· Watchdog Time-out Reset during Power Down
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
D D
W D T T im e - o u t
D D
tR
tS
S T D
S T
S S T T im e - o u t
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
In te rn a l R e s e t
RES Reset Timing Chart
Reset Initial Conditions
· Low Voltage Reset - LVR
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device,
which is selected via a configuration option. If the supply
voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For
a valid LVR signal, a low voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for greater than the
value tLVR specified in the A.C. characteristics. If the low
voltage state does not exceed 1ms, the LVR will ignore it
and will not perform a reset function.
TO PDF
L V R
tR
S T D
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
S S T T im e - o u t
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
In te rn a l R e s e t
Low Voltage Reset Timing Chart
Item
· Watchdog Time-out Reset during Normal Operation
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
In te rn a l R e s e t
Prescaler
The Timer Counter Prescaler will
be cleared
WDT Time-out Reset during Normal Operation
Timing Chart
Input/Output Ports I/O ports will be setup as inputs
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
Stack Pointer
Rev. 1.10
35
Stack Pointer will point to the top
of the stack
March 30, 2014
HT49RA1/HT49CA1
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation
for the larger package type.
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
RTCC
--00 0111
--00 0111
--00 0111
--uu uuuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1---
0000 1---
0000 1---
uuuu u---
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Register
TMR1C
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
----
---1
----
---1
----
---1
----
---u
PCC
----
---1
----
---1
----
---1
----
---u
PD
----
1111
----
1111
----
1111
----
uuuu
INTC1
-000 -000
-000 -000
-000 -000
-uuu -uuu
LCDC
0000 --11
0000 --11
0000 --11
0000 --uu
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.10
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HT49RA1/HT49CA1
Oscillator
OSC4 pins, should be connected to a 32768Hz crystal
to implement this internal RTC oscillator. However, for
some crystals, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
The one methods of generating the system clock are:
· External RC oscillator
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
External RC Oscillator
As an RC oscillator is used, an external resistor between OSC1 and VSS is required whose value should
be 12kW for a frequency of 4MHz. The RC oscillator provides a ±3% accuracy, the conditions are:
· VDD=2.0V~3.6V
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
· Temp.= 0°C ~ 50°C
· fSYS=4MHz
O S C 1
Ca
Cb
Rf
TBD
TBD
TBD
RTC Oscillator Internal Component Values
RTC Oscillator C1 and C2 Values
Crystal Frequency
32768Hz
Note:
RC Oscillator
External RTC Oscillator
When the microcontroller enters the Power Down Mode,
the system clock is switched off to stop microcontroller
activity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
the internal timers operational even when the
microcontroller is in the Power Down Mode. To do this,
another clock, independent of the system clock, must be
provided. To do this a configuration option exists for a
Real Time Clock - RTC oscillator. Here the OSC3 and
C 1
3 2 7 6 8 H z
C2
CL
TBD
TBD
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
32768 Hz Crystal Recommended Capacitor Values
O S C 3
R p
R f
C a
C b
C 2
C1
TBD
O S C 4
T o in te r n a l
c ir c u its
N o te : R p is n o r m a lly n o t r e q u ir e d .
External RTC Oscillator
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
· The WDT will be cleared and resume counting if the
During power up there is a time delay associated with
the RTC oscillator waiting for it to start up. A bit in the
RTCC register, known as the QOSC bit, is provided to
give a quick start-up function and can be used to minimise this delay. During a power up condition, this bit will
be cleared to 0 which will initiate the RTC oscillator quick
start-up function. However, as there is additional power
consumption associated with this quick start-up function, to reduce power consumption after start up takes
place, it is recommended that the application program
should set the QOSC bit high about 2 seconds after
power on. It should be noted that, no matter what condition the QOSC bit is set to, the RTC oscillator will always
function normally, only there is more power consumption associated with the quick start-up function.
WDT clock source is selected to come from the WDT
oscillator. The WDT will stop if its clock source originates from the system clock.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. This also applies to devices which
have different package types, as there may be
undonbed pins, which must either be setup as outputs
or if setup as inputs must have pull-high resistors
connected. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Watchdog Timer Oscillator
The WDT oscillator is a fully integrated free running RC
oscillator with a typical period of 90ms at 3V, requiring no
external components. It is selected via configuration option. If selected, when the device enters the Power Down
Mode, the system clock will stop running, however the
WDT oscillator will continue to run and keep the watchdog function active. However, as the WDT will consume a
certain amount of power when in the Power Down Mode,
for low power applications, it may be desirable to disable
the WDT oscillator by configuration option.
Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode, also known as the HALT Mode or
Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely
low standby current level. This occurs because when
the device enters the Power Down Mode, the system
oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port B
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
Rev. 1.10
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HT49RA1/HT49CA1
In the Remote Type with LCD series of microcontrollers,
all Watchdog Timer options, such as enable/disable,
WDT clock source and clear instruction type all selected
through configuration options. There are no internal registers associated with the WDT in the Remote Type
MCU with LCD series. One of the WDT clock sources is
an internal oscillator which has an approximate period of
90ms at a supply voltage of 3V. However, it should be
noted that this specified internal clock period can vary
with VDD, temperature and process variations. The
other WDT clock source option is the fSYS/4 clock.
Whether the WDT clock source is its own internal WDT
oscillator, or from fSYS/4, it is further divided by 16 via an
internal 15-bit counter and a clearable single bit counter
to give longer Watchdog time-outs. As this ratio is fixed it
gives an overall Watchdog Timer time-out value of 215/fS
to 216/fS. As the clear instruction only resets the last
stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out
can vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog Timer
counter before the clear instruction is executed. It is important to realise that as there are no independent internal registers or configuration options associated with
the length of the Watchdog Timer time-out, it is completely dependent upon the frequency of fSYS/4, the internal WDT oscillator or RTC oscillator.
Each pin on Port B can be setup via an individual configuration option to permit a negative transition on the pin
to wake-up the system. When a Port B pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
If the fSYS/4 clock is used as the WDT clock source, it
should be noted that when the system enters the Power
Down Mode, then the instruction clock is stopped and
the WDT will lose its protecting purposes. For systems
that operate in noisy environments, using the internal
WDT oscillator is strongly recommended.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such
as electrical noise. It operates by providing a device reset
when the WDT counter overflows. The WDT clock is supplied by one of three sources selected by configuration
option: its own self contained dedicated internal RTC oscillator, WDT oscillator or fSYS/4. Note that if the WDT
configuration option has been disabled, then any instruction relating to its operation will result in no operation.
C L R
W D T 1 F la g
C L R
W D T 2 F la g
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instructions and the third is via a ²HALT² instruction.
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS Y S /4
W D T O s c illa to r
R T C O s c illa to r
W D T C lo c k S o u r c e
C o n fig u r a tio n
O p tio n
fS
C L R
1 5 - b it C o u n te r
¸
2
W D T T im e - o u t
2 15/fS ~ 2 16/fS
W D T C lo c k S o u r c e
Watchdog Timer
Rev. 1.10
39
March 30, 2014
HT49RA1/HT49CA1
of this instruction will have no effect, only the execution of
a ²CLR WDT2² instruction will clear the WDT. Similarly
after the ²CLR WDT2² instruction has been executed,
only a successive ²CLR WDT1² instruction can clear the
Watchdog Timer.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use the
two commands ²CLR WDT1² and ²CLR WDT2². For the
first option, a simple execution of ²CLR WDT² will clear
the WDT while for the second option, both ²CLR WDT1²
and ²CLR WDT2² must both be executed to successfully
clear the WDT. Note that for this second option, if ²CLR
WDT1² is used to clear the WDT, successive executions
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later as the application software has no control over the configuration options. All options must
be defined for proper system function, the details of which are shown in the table.
Item
Options
I/O Options
1
PB0~PB7: wake-up enable or disable (bit option)
2
PC0: CMOS output or carrier output (bit option)
3
PC0: Pull-high enable or disable (bit option)
LCD Options
4
LCD clock: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28
5
LCD duty: 1/2, 1/3, 1/4
6
LCD bias: 1/2, 1/3
7
LCD segment 12~15 output or CMOS output(Nibble Option)
8
LCD segment 16~19 output or CMOS output(Nibble Option)
Interrupt Options
9
INT0 function: enable or disable
10
Triggering edge: rising, falling or both
11
INT1 function: enable or disable
12
Triggering edge: rising, falling or both
Oscillator Options
13
fS internal clock source: RTC oscillator, WDT oscillator or fSYS/4
Timer Options
14
Timer/Event Counter 0 clock source: fSYS or fSYS/4
Time Base Options
15
Time Base division ratio: fS/212, fS/213, fS/214, fS/215
Watchdog Options
16
WDT enable or disable
17
CLRWDT instructions: 1 or 2 instructions
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
Item
Options
LVD/LVR Options
18
LVD function: enable or disable
19
LVR function: enable or disable
20
LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V
Carrier Options
21
Carrier duty: 1/2 duty or 1/3 duty
22
Carrier frequency: fSYS/8, fSYS/16, fSYS/32, fSYS/64 for 1/2 duty cycle
23
Carrier frequency: fSYS/12, 1/3 duty cycle
24
Carrier frequency: fSYS/24, fSYS/48, fSYS/96 for 1/2 duty or 1/3 duty cycle
Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
C O M 0 ~
C O M 3 /S E G 3 2
S E G 4 ~ S E G 3 1
L C D
P A N E L
R E S
P A 0 ~ P A 7
0 .1 m F
V S S
O S C
C ir c u it
O S C 1
P B 0 /IN
P B 1 /IN
P B 2 /T M
P B 3 /T M
P B 4 ~ P
T 0
T 1
R 0
R 1
B 7
P C 0 /R E M
P D 0 /S E G 0 ~
P D 3 /S E G 3
S e e O s c illa to r
S e c tio n
O S C 3
O S C 4
C 1
0 .1 m F
C 2
3 3 W
1 W
V D D
V 1
0 .1 m F
1 0 0 m F
V b a t
2 2 0 W ~ 1 k W
Rev. 1.10
V 2
P C 0 /R E M
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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HT49RA1/HT49CA1
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.10
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March 30, 2014
HT49RA1/HT49CA1
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.10
54
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HT49RA1/HT49CA1
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated
at regular intervals users are reminded to consult the Holtek website for the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page.
· Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
· Packing Meterials Information
· Carton information
Rev. 1.10
55
March 30, 2014
HT49RA1/HT49CA1
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
a
J
1 6
1
Symbol
Nom.
Max.
A
¾
0.354 BSC
¾
B
¾
0.276 BSC
¾
C
¾
0.354 BSC
¾
D
¾
0.276 BSC
¾
E
¾
0.016 BSC
¾
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
0.024
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
¾
9.00 BSC
¾
B
¾
7.00 BSC
¾
C
¾
9.00 BSC
¾
D
¾
7.00 BSC
¾
E
¾
0.40 BSC
¾
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
0.60
0.75
K
0.09
¾
0.20
a
0°
¾
7°
56
March 30, 2014
HT49RA1/HT49CA1
Copyright Ó 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and
Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a
risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its
products without prior notification. For the most up-to-date information, please visit our web
site at http://www.holtek.com.tw.
Rev. 1.10
57
March 30, 2014