TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces HT56RU25 Revision: V1.00 Date: �������������� March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Table of Contents Features............................................................................................................. 7 General Description.......................................................................................... 8 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 9 Pin Description............................................................................................... 10 Absolute Maximum Ratings............................................................................11 D.C. Characteristics........................................................................................ 12 A.C. Characteristics........................................................................................ 14 A/D Converter Electrical Characteristics...................................................... 15 Power-on Reset Characteristics.................................................................... 16 DC/DC Converter and LDO Electrical Characteristics................................ 16 System Architecture....................................................................................... 18 Clocking and Pipelining.......................................................................................................... 18 Program Counter.................................................................................................................... 19 Stack...................................................................................................................................... 20 Arithmetic and Logic Unit − ALU............................................................................................ 21 Flash Program Memory.................................................................................. 21 Structure................................................................................................................................. 21 Special Vectors...................................................................................................................... 22 Look-up Table......................................................................................................................... 23 Table Program Example......................................................................................................... 24 Data Memory................................................................................................... 25 Structure................................................................................................................................. 25 General Purpose Data Memory............................................................................................. 26 Special Purpose Data Memory.............................................................................................. 26 Special Function Registers Description....................................................... 27 Indirect Addressing Registers − IAR0, IAR1.......................................................................... 27 Memory Pointers − MP0, MP1............................................................................................... 27 Bank Pointer − BP.................................................................................................................. 28 Accumulator − ACC................................................................................................................ 29 Program Counter Low Register − PCL................................................................................... 29 Look-up Table Registers − TBLP, TBHP, TBLH...................................................................... 29 Status Register − STATUS..................................................................................................... 30 Interrupt Control Registers..................................................................................................... 31 Timer/Event Counter Registers.............................................................................................. 31 Input/Output Ports and Control Registers.............................................................................. 31 Pulse Width Modulator Registers........................................................................................... 31 A/D Converter Registers − ADRL, ADRH, ADCR, ACSR....................................................... 32 Serial Interface Module Registers.......................................................................................... 32 Rev. 1.00 2 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Port A Wake-up Register − PAWU......................................................................................... 32 Pull-High Registers − PAPU, PBPU, PCPU........................................................................... 32 Clock Control Register − CLKMOD........................................................................................ 32 Miscellaneous Register − MISC0, MISC1.............................................................................. 32 Input/Output Ports.......................................................................................... 33 Pull-high Resistors................................................................................................................. 33 Port A Wake-up...................................................................................................................... 34 Port A Open Drain Function................................................................................................... 34 I/O Port Control Registers...................................................................................................... 34 Pin-shared Functions............................................................................................................. 35 I/O Pin Structures................................................................................................................... 36 Programming Considerations................................................................................................. 37 Timer/Event Counters.................................................................................... 38 Configuring the Timer/Event Counter Input Clock Source..................................................... 38 Timer Registers − TMR0, TMR1L/TMR1H, TMR2, TMR3..................................................... 40 Configuring the Timer Mode................................................................................................... 41 Configuring the Event Counter Mode..................................................................................... 42 Configuring the Pulse Width Measurement Mode.................................................................. 43 Programmable Frequency Divider − PFD.............................................................................. 44 Prescaler................................................................................................................................ 44 I/O Interfacing......................................................................................................................... 45 Timer/Event Counter Pins Internal Filter................................................................................ 45 Programming Considerations................................................................................................. 46 Timer Program Example........................................................................................................ 47 Pulse Width Modulator................................................................................... 48 PWM Overview...................................................................................................................... 48 8+4 PWM Mode Modulation................................................................................................... 49 PWM Output Control.............................................................................................................. 49 PWM Register Pairs − PWMnH/PWMnL (n=0~3).................................................................. 50 PWM Programming Example................................................................................................. 50 Analog to Digital Converter........................................................................... 51 A/D Overview......................................................................................................................... 51 A/D Converter Data Registers − ADRL, ADRH...................................................................... 51 A/D Converter Control Registers − ADCR, ADPCR, ACSR................................................... 52 A/D Operation........................................................................................................................ 54 A/D Input Pins........................................................................................................................ 55 Initialising the A/D Converter.................................................................................................. 55 Programming Considerations................................................................................................. 57 A/D Programming Example.................................................................................................... 57 A/D Transfer Function............................................................................................................ 59 Rev. 1.00 3 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Serial Interface Function − SIM..................................................................... 60 SPI Interface.......................................................................................................................... 60 I2C Interface........................................................................................................................... 68 I2C Bus Communication......................................................................................................... 72 Peripheral Clock Output................................................................................. 76 Peripheral Clock Operation.................................................................................................... 76 Buzzer.............................................................................................................. 77 PA0/PA1 Pin Function Control............................................................................................... 78 Interrupts......................................................................................................... 79 Interrupt Registers.................................................................................................................. 80 Interrupt Operation................................................................................................................. 84 Interrupt Priority...................................................................................................................... 85 External Interrupt.................................................................................................................... 85 External Peripheral Interrupt.................................................................................................. 87 Timer/Event Counter Interrupt................................................................................................ 87 A/D Interrupt........................................................................................................................... 88 Smart Card Interrupt.............................................................................................................. 88 Smart Card Insertion/Removal Interrupt................................................................................ 88 SIM (SPI/I2C Interface) Interrupts........................................................................................... 88 Multi-function Interrupt........................................................................................................... 89 Real Time Clock Interrupt....................................................................................................... 89 Time Base Interrupt................................................................................................................ 91 Programming Considerations................................................................................................. 92 Reset and Initialisation................................................................................... 93 Reset Functions..................................................................................................................... 93 Reset Initial Conditions.......................................................................................................... 95 Oscillator......................................................................................................... 98 System Clock Configurations................................................................................................. 98 External Crystal/ Ceramic Oscillator − HXT.......................................................................... 98 External RC Oscillator − ERC................................................................................................ 99 Internal High Speed RC Oscillator − HIRC.......................................................................... 100 Internal Low Speed Oscillator − LIRC.................................................................................. 100 External 32.768kHz Oscillator − LXT................................................................................... 100 External Oscillator − EC....................................................................................................... 101 Supplementary Oscillators................................................................................................... 101 System Operating Modes............................................................................. 102 Clock Sources...................................................................................................................... 102 Operating Modes.................................................................................................................. 105 Power Down Mode and Wake-up................................................................. 106 Power Down Mode............................................................................................................... 106 Entering the Power Down Mode.......................................................................................... 106 Standby Current Considerations.......................................................................................... 106 Wake-up............................................................................................................................... 107 Rev. 1.00 4 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Low Voltage Detector − LVD........................................................................ 108 LVD Operation...................................................................................................................... 108 Watchdog Timer............................................................................................ 109 Watchdog Timer Operation.................................................................................................. 109 Clearing the Watchdog Timer................................................................................................110 UART Interface...............................................................................................111 UART External Interface.......................................................................................................112 UART Data Transfer Scheme...............................................................................................112 UART Status and Control Registers.....................................................................................112 Baud Rate Generator............................................................................................................118 UART Setup and Control..................................................................................................... 120 UART Transmitter................................................................................................................ 121 UART Receiver.................................................................................................................... 123 Managing Receiver Errors................................................................................................... 125 UART Interrupt Structure..................................................................................................... 126 UART Power Down Mode and Wake-up.............................................................................. 127 Digital to Analog Converter − DAC............................................................. 128 Operation............................................................................................................................. 128 DC/DC Converter and LDO.......................................................................... 129 Smart Card Interface.................................................................................... 130 Interface Pins....................................................................................................................... 130 Card Detection..................................................................................................................... 131 Internal Time Counter − ETU, GTC, WTC........................................................................... 131 Elementary Time Unit − ETU............................................................................................... 131 Guard Time Counter − GTC................................................................................................. 132 Waiting Time Counter − WTC.............................................................................................. 133 Smart Card UART Mode...................................................................................................... 134 Power Control...................................................................................................................... 135 Smart Card Interrupt Structure............................................................................................. 136 Programming Considerations............................................................................................... 137 Smart Card Interface Status and Control Registers............................................................. 138 Configuration Options.................................................................................. 149 Application Circuits...................................................................................... 150 Instruction Set............................................................................................... 151 Introduction.......................................................................................................................... 151 Instruction Timing................................................................................................................. 151 Moving and Transferring Data.............................................................................................. 151 Arithmetic Operations........................................................................................................... 151 Logical and Rotate Operation.............................................................................................. 152 Branches and Control Transfer............................................................................................ 152 Bit Operations...................................................................................................................... 152 Table Read Operations........................................................................................................ 152 Other Operations.................................................................................................................. 152 Rev. 1.00 5 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Instruction Set Summary............................................................................. 153 Table Conventions................................................................................................................ 153 Instruction Definition.................................................................................... 155 Package Information.................................................................................... 164 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 165 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions............................................ 166 Rev. 1.00 6 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Features • Operating voltage: ♦♦ fSYS=32.768kHz: 2.2V~5.5V ♦♦ fSYS=4MHz: 2.2V~5.5V ♦♦ fSYS=12MHz: 3.0V~5.5V ♦♦ fSYS=20MHz: 4.5V~5.5V • Operating current: fSYS=1MHz at 3V, 170µA, typ. • OTP Program Memory: 16K×16 • RAM Data Memory: 1280×8 • 12 levels subroutine nesting • Up to 24 bidirectional I/O lines • TinyPower technology for low power operation • Three pin-shared external interrupts lines • Three 8-bit programmable Timer/Event Counters with overflow interrupt and 7-stage prescaler • One 16-bit programmable Timer/Event Counters with overflow interrupt • External Crystal (HXT), RC (ERC) and 32.768kHz (LXT) crystal oscillators • Internal high speed RC oscillator – HIRC • Fully integrated RC 32kHz oscillator – LIRC • Externally supplied system clock option – EC • Watchdog Timer function • PFD/Buzzer for audio frequency generation – only available for 44-LQFP package type • Dual Serial Interface Modules (SIM): SPI and I2C • 4 operating modes: Normal, Slow, Idle and Sleep • 8-channel 12-bit resolution A/D converter – only available for 44-LQFP package type • 4-channel 12-bit PWM outputs – only available for 44-LQFP package type • 12-bit D/A converter with 8-level volume control • Smartcard interface compatible with and certifiable to the ISO 7816-3 standards • DC/DC converter and LDO function • Low voltage reset function: 2.1V, 3.15V, 4.2V • Low voltage detect function: 2.2V, 3.3V, 4.4V • Bit manipulation instruction • Table read instructions • 63 powerful instructions • Up to 0.2µs instruction cycle with 20MHz system clock at VDD=5V • All instructions executed in one or two machine cycles • Power down and wake-up functions to reduce power consumption • UART Interface for fully duplex asynchronous comminucation • Package type: 28-pin SSOP and 44-pin LQFP Rev. 1.00 7 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces General Description The TinyPowerTM A/D Type 8-bit high performance RISC architecture microcontroller is specifically designed for applications that interface directly to analog signals. The device includes analog features such as an integrated multi-channel Analog to Digital Converter, 12-bit Digital to Analog Converter, DC/DC Converter and LDO. With their fully integrated SPI and I2C functions, designers are provided with a means of easy communication with external peripheral hardware. The benefits of integrated analog features such as A/D, D/A, etc., and PWM functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, provides the device with the versatility for a wide range of products in the home appliance and industrial application areas. Some of these products could include electronic metering, environmental monitoring, handheld instruments, electronically controlled tools, motor driving in addition to many others. The UART module is contained in this device. It can support the applications such as data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery operated device communication, etc. This device also includes a Smartcard Interface, which is compatible with and certified to ISO 7816 standards, to provide communication with various types of Smart Card. The unique Holtek TinyPower technology also offers the advantages of extremely low current consumption characteristics, an extremely important consideration in the present trend for low power battery powered applications. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc., combine to ensure user applications require a minimum of external components. Block Diagram Low Voltage Reset OTP P�og�amming �emo�y (＊) PFD (＊) PW� OTP P�og�am �emo�y Wat��dog Time� Low Voltage Dete�t Sta�k Data �emo�y 8-bit RISC �CU Co�e Inte�nal RC Os�illato�s Inte��upt Cont�olle� Reset Ci��uit Exte�nal XTAL/RC/EC Os�illato�s Exte�nal ��.768kHz Os�illato� (＊) A/D Conve�te� I/O Po�ts SI�s Time�s UART Sma�t�a�d Inte�fa�e D/A Conve�te� LDO DC/DC Conve�te� (*): Only available for 44-LQFP package type. Rev. 1.00 8 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Pin Assignment PC5/PW�1/PCLK PA0/BZ/INT0/AN0 PA1/BZ/INT1/AN1 PC0/AUD/AN� PC1/PFD/AN� PA�/T�R�/TX/AN� PA5/T�R�/RX/PW��/AN5 PA6/T�R0/AN6 PA7/T�R1/AN7/VREF AVDD VDD NC NC NC PC�/XT� PC�/XT1 AVSS VSS LDOVSS PA�/OSC1 PA�/OSC� CDET �� �� �� �1 �0 �9 �8 �7 �6 �5 �� 1 �� � �� � �1 � �0 5 �9 HT56RU25 6 �8 44 LQFP-A 7 �7 8 �6 9 �5 10 �� 11 �� 1� 1� 1� 15 1617 18 19 �0 �1 �� PC6/PW��/PINT PC7/RES PC�/PW�0/SCS0 PB0/SCK0/SCL0 PB1/SDI0/SDA0 PB�/SDO0 PB� PB�/SDO1 PB5/SDI1/SDA1 PB6/SCK1/SCL1 PB7/SCS1 CC8 CIO CC� CCLK CRST CRDVCC LDOIN VO CVSS SELF SELF PB0/SCK0/SCL0 1 �8 PB1/SDI0/SDA0 PC�/SCS0 � �7 PB�/SDO0 PC7/RES PA0/INT0 � �6 �5 CC8 � PA1/INT1 5 �� CIO CC� PA�/T�R�/TX PA5/T�R�/RX 6 �� CCLK 7 �� CRST PA6/T�R0 8 PA7/T�R1 9 �1 �0 CRDVCC LDOIN VDD/AVDD 10 19 VSS/AVSS 11 18 VO CVSS LDOVSS 1� 1� 1� 17 16 PA�/OSC1 PA�/OSC� 15 SELF SELF CDET HT56RU25 HT56RU25 28 SSOP-A 28 SSOP-A Rev. 1.00 9 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Pin Description The following table depicts the pins common to all devices. Pin Name I/O Configuration Option Description BZ/BZ (*) HXT or ERC or HIRC or EC Bidirectional 8-bit input/output port. Each individual bit on this port can be configured as a wake-up input by the PAWU register control bit. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A pull-high resistor can be connected to each pin determined by the PAPU register. Port A is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once a Port A line is selected as an A/D input, the I/O function and pull-high resistor are disabled automatically. The BZ/INT0, BZ/INT1, TMR2/TX, TMR3/RX/PWM3, TMR0 and TMR1 are pin-shared with PA0, PA1 and PA4~PA7 respectively. The OSC1 and OSC2 pins are connected to an external RC network or crystal, determined by configuration options, for the internal system clock. If the RC system clock option is selected, the OSC2 pin can be used as an I/O pin. The internal system can come from the internal high speed RC oscillator, HIRC, which is selected by configuration options. When the HIRC is selected as the system oscillator, the OSC1 and OSC2 pins can be used as normal I/O pins. The abbreviation EC stands for External Clock mode. In the EC mode, an external clock source is provided on OSC1 as the system clock. The VREF pin is the ADC reference voltage input pin. The “VREFS” bit in the ACSR register is used to select either VREF or AVDD as the ADC reference voltage. SIM0 SIM1 Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected to each pin by the PBPU register. The SDO1, SDI1/SDA1, SCK1/SCL1 and SCS1 pins are the the SIM1 interface pins, pin-shared with PB4~PB7 respectively and enabled by a configuration option, as well as the SIM0 interface pins. When the configuration option enables the SIM function, the I/O function will be disabled. PFD(*) 32.768kHz SIM0 Bidirectional 7-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected to each pin determined by the PCPU register. The AUD pin is the audio output pin from the D/A Converter and pin-shared with PC0. When the D/A-Converter is enabled, the PC0 I/O function will be disabled automatically, including any pull-high resistors. If the D/A Converter output, AUD, and the A/D Converter input, AN2, are both enabled, then the A/D converter output will be connected to the AN2 input channel allowing the D/A output to be measured by the A/D Converter. The PFD functional pin is pin-shared with PC1. The XT1 and XT2 are connected to a 32.768kHz crystal oscillator to form a clock source for fSUB or fSL. The PWM0, PWM1 and PWM2 pins are pin-shared with PC4, PC5 and PC6 respectively. PC4 is also pin-shared with SCS0, the chip select pin for the Serial Interface Module 0. The PCLK is a peripheral clock output pin which is enabled by the “PCKEN” in the SIM0CTRL register and pin-shared with PC5. The PINT pin is the external peripheral interrupt pin and pin-shared with PC6. Input/Output PA0/BZ(*)/INT0/AN0(*) PA1/BZ(*)/INT1/AN1(*) PA2/OCS1 PA3/OCS2 PA4/TMR2/TX/AN4(*) PA5/TMR3/RX/ PWM3(*)/AN5(*) PA6/TMR0/AN6(*) PA7/TMR1/AN7(*)/ VREF(*) PB0/SCK0/SCL0 PB1/SDI0/SDA0 PB2/SDO0 PB3 PB4/SDO1 PB5/SDI1/SDA1 PB6/SCK1/SCL1 PB7/SCS1 PC0/AUD/AN2(*) PC1/PFD(*)/AN3(*) PC2/XT1 PC3/XT2 PC4/PWM0(*)/SCS0 PC5/PWM1(*)/PCLK PC6/PWM2(*)/PINT Rev. 1.00 I/O I/O I/O 10 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Configuration Option Description I/O RES Schmitt Trigger reset input pin, active low. The RES pin is pin-shared with PC7 whose function is determined by a configuration option. When PC7 is configured as an I/O pin, software instructions determine if this pin is an open drain output or a Schmitt Trigger input without pull-high resistor. VDD P — Positive power supply VSS P — Negative power supply, ground AVDD P — Analog positive power supply AVSS P — Analog negative power supply, ground CVSS P — DC/DC Converter Negative power supply, ground LDOVSS P — LDO Negative power supply, ground Pin Name PC7/RES I/O Power & Ground ISO 7816 - Smart Card Interface VO P — External diode connection pin for DC/DC converter LDOIN P — LDO input voltage pin This pin must externally be connected to the VO pin SELF P — External inductor connection pin for DC/DC converter The two SELF pins should externally be connected together CRST O — Smart card reset output CCLK O — Smart card clock output CC4 I/O — Smart card C4 input/output CC8 I/O — Smart card C8 input/output CIO I/O — Smart card data input/output CDET I — Smart card detection input CRDVCC P — Positive power supply for external smart card The two CRDVCC pins should externally be connected together (*): Only available for 44-LQFP package type. Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOH Total.....................................................................................................................................-80mA IOL Total...................................................................................................................................... 80mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Rev. 1.00 11 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces D.C. Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions — — Min. Typ. Max. Unit 2.2 — 5.5 V Operating Voltage VDD Operating Voltage Operating Current IDD1 Operating Current (HXT, ERC OSC) 3V No load, fSYS=fM=1MHz 5V ADC off — 170 250 µA — 380 570 µA IDD2 Operating Current (HXT, ERC OSC) 3V No load, fSYS=fM=2MHz 5V ADC off — 240 360 µA — 490 730 µA IDD3 Operating Current (HXT, ERC, HIRC OSC) 3V No load, fSYS=fM=4MHz 5V ADC off — 440 660 µA — 900 1450 µA IDD4 Operating Current (EC Mode) 3V No load, fSYS=fM=4MHz 5V ADC and Clock input filter off — 380 570 µA — 680 1020 µA IDD5 Operating Current (HXT, ERC OSC) 3V No load, fSYS=fM=6MHz 5V ADC off — 700 1050 µA — 1300 1950 µA IDD6 Operating Current (HXT, ERC, HIRC OSC) 5V No load, fSYS=fM=8MHz ADC off — 1.8 2.7 mA IDD7 Operating Current (HXT, ERC, HIRC OSC) 5V No load, fSYS=fM=12MHz ADC off — 2.6 4.5 mA IDD8 Operating Current (HXT, ERC OSC) 5V No load, fSYS=fM=20MHz ADC off — 5.5 8.5 mA IDD9 Operating Current (Slow Mode, fM=4MHz) (HXT, ERC, HIRC OSC) 3V No load, f =f SYS SLOW=500kHz ADC off 5V — 150 220 µA — 340 510 µA IDD10 Operating Current (Slow Mode, fM=4MHz) (HXT, ERC, HIRC OSC) 3V No load, f =f SYS SLOW=1MHz 5V ADC off — 180 270 µA — 400 600 µA IDD11 Operating Current (Slow Mode, fM=4MHz) (HXT, ERC, HIRC OSC) 3V No load, f =f SYS SLOW=2MHz 5V ADC off — 270 400 µA — 560 840 µA IDD12 Operating Current (Slow Mode, fM=8MHz) (HXT, ERC, HIRC OSC) 3V No load, f =f SYS SLOW=1MHz 5V ADC off — 350 530 µA — 700 1070 µA IDD13 Operating Current (Slow Mode, fM=8MHz) (HXT, ERC, HIRC OSC) 3V No load, f =f SYS SLOW=2MHz 5V ADC off — 450 670 µA — 890 1320 µA IDD14 Operating Current (Slow Mode, fM=8MHz) (HXT, ERC, HIRC OSC) 3V No load, f =f SYS SLOW=4MHz 5V ADC off — 500 900 µA — 1000 1700 µA IDD15 Operating Current (fSYS=LXT or LIRC) 3V WDT off, ADC off, 5V LXT in low power mode — 8 16 µA — 15 30 µA — 0.2 1.0 µA — 0.3 2.0 µA — 1 2 µA — 3 5 µA Standby Current ISTB1 Sleep Mode Standby Current (fM=4MHz HIRC, fSYS, fSUB, fS, fWDT=off) 3V System HALT, WDT off, 5V DC/DC converter off ISTB2 Sleep Mode Standby Current (fM=4MHz HIRC, fSYS, fWDT=fSUB=LXT or LIRC) 3V System HALT, WDT on, DC/DC converter off, 5V LXT in low power mode Rev. 1.00 12 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Symbol ISTB3 Parameter Idle Mode Standby Current (fM=4MHz HIRC, fSYS=fM; fWDT, fS=fSUB=LXT or LIRC) Test Conditions Min. Typ. Max. Unit 3V System2HALT, WDT off, SPI or I C on, PCLK on, PCLK=fSYS/8,LXT in low power 5V mode — 150 250 µA — 350 550 µA Conditions VDD Input High/Low Voltage VIL1 Input Low Voltage for I/O Ports, TMR and INT Pins — — 0 — 0.3VDD V VIH1 Input High Voltage for I/O Ports, TMR and INT Pins — — 0.7VDD — VDD V VIL2 Input Low Voltage (RES) — — 0 — 0.4VDD V VIH2 Input High Voltage (RES) — — 0.9VDD — VDD V mA Sink/Source Current – GPIO IOL1 I/O sink current (PA, PB, PC) IOH1 I/O source current (PA, PB, PC) IOL2 PC7/RES Sink Current 3V 5V 3V 5V 6 12 — 10 25 — mA −2 −4 — mA −5 −8 — mA 2 3 — mA VO=5.5V VCRDVCC=3V, VOL=0.1VCRDVCC 40 — — µA VO=5.5V VCRDVCC=5V, VOL=0.1VCRDVCC 60 — — µA VO=5.5V VCRDVCC=3V, VOH=0.9VCRDVCC 40 — — µA VO=5.5V VCRDVCC=5V, VOH=0.9VCRDVCC 60 — — µA VO=5.5V VCRDVCC=3V, VOL=0.1VCRDVCC 400 — — µA VO=5.5V VCRDVCC=5V, VOL=0.1VCRDVCC 600 — — µA VO=5.5V VCRDVCC=3V, VOH=0.9VCRDVCC 15 — — µA VO=5.5V VCRDVCC=5V, VOH=0.9VCRDVCC 15 — — µA VO=5.5V VCRDVCC=3V, VOL=0.1VCRDVCC 400 — — µA VO=5.5V VCRDVCC=5V, VOL=0.1VCRDVCC 600 — — µA VO=5.5V VCRDVCC=3V, VOH=0.9VCRDVCC 15 — — µA VO=5.5V VCRDVCC=5V, VOH=0.9VCRDVCC 15 — — µA VOL=0.1VDD VOH=0.9VDD 5V VOL=0.1VDD Sink/Source Currnt – Smartcard interface IO IOL3 IOH3 IOL4 IOH4 IOL5 IOH5 Card Clock (CCLK) Sink Current Card Clock (CCLK) Source Current Card I/O (CIO) Sink Current Card I/O (CIO) Source Current Card Reset (CRST), C4/C8 Sink Current Card Reset (CRST), C4/C8 Source Current 5V 5V 5V 5V 5V 5V Pull-High Resistance 3V RPH1 Pull-high Resistance for General I/O Ports & Card Detection (CDET) RPH2 Pull-high resistance for Card I/O (CIO) 5V VO=5.5V, VCRDVCC=3V/5V — 5V 40 60 80 kΩ 10 30 50 kΩ 7.5 15.0 22.5 kΩ 1.98 2.10 2.22 V 2.98 3.15 3.32 V 3.98 4.20 4.42 V LVR/LVD LVR=2.1V Option VLVR1 VLVR2 Low Voltage Reset Voltage VLVR3 Rev. 1.00 — LVR=3.15V Option LVR=4.2V Option 13 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Symbol Parameter Test Conditions Low Voltage Detector Voltage Typ. Max. Unit LVD=2.2V Option 2.08 2.20 2.32 V 3.12 3.30 3.50 V LVD=4.4V Option 4.12 4.40 4.70 V — -3%× typ. +3%× 1.24 typ. VLVD3 VBG Min. — LVD=3.3V Option VLVD1 VLVD2 Conditions VDD Bandgap reference with buffer voltage — V A.C. Characteristics Ta=25°C Symbol Parameter Test Conditions 4000 — 12000 kHz 4.5V~5.5V 400 — 20000 kHz 2.2V~5.5V — 32768 — Hz External RERC=150kΩ, Ta=0°C~70°C −7% 4 +7% MHz External RERC=150kΩ, Ta=-40°C~85°C −11% 4 +11% MHz 3V/5V Ta=25°C −2% 4 +2% MHz 3V/5V Ta=25°C −2% 8 +2% MHz 5V Ta=25°C −2% 12 +2% MHz 3V/5V Ta=0°C~70°C −5% 4 +5% MHz 3V/5V Ta=0°C~70°C −5% 8 +5% MHz 5V Ta=0°C~70°C −5% 12 +5% MHz 2.2V~5.5V Ta=0°C~70°C −8% 4 +8% MHz 3.0V~5.5V Ta=0°C~70°C −8% 8 +8% MHz MHz — TMRn Input Frequency kHz — System clock (LXT) fTIMER Unit 400 fSYS2 4/8/12MHz Internal RC OSC Max. 400 — fHIRC Typ. 2.2V~5.5V System Clock (HXT, ERC, HIRC) 4MHz External RC OSC Min. 3.0V~5.5V fSYS1 f4MERC Conditions VDD 2.2V~5.5V 4.5V~5.5V Ta=0°C~70°C −8% 12 +8% 2.2V~5.5V Ta=−40°C~85°C −12% 4 +12% MHz 3.0V~5.5V Ta=−40°C~85°C −12% 8 +12% MHz 4.5V~5.5V Ta=−40°C~85°C −12% 12 +12% MHz 2.2V~5.5V 400 — 4000 3.0V~5.5V 400 — 12000 kHz 4.5V~5.5V 400 — 20000 kHz 2.2~5.5V, Ta=25°C, after trimming 28.1 32.0 34.4 kHz — kHz fLIRC Internal 32kHz RC oscillator (LIRC) 5V tRES External Reset Low Pulse Width — — 10 — — µs tINT Interrupt Pulse Width — — 10 — — µs — — 100 µs tLVDS LVD Output Stable Time 5V LVR disable, LVD enable, Bandgap voltage ready tSST1 System start-up timer period for HXT/LXT (without fast start-up) — Power on or wake up from 1024 Idle mode — — tSYS tSST2 System start-up timer period for HXT/LXT (with fast start-up) — fSL=LXT — 1 2 tLXT fSL=LIRC — 1 2 tLIRC tSST3 System start-up timer period (Wake-up from HALT, fSYS on at HALT state) — — 2 — — tSYS tSST4 System start-up timer period (Reset) — — 1024 — — tSYS Rev. 1.00 14 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Symbol Parameter Test Conditions Min. Typ. Max. Unit — 25 50 100 ms — — 8.3 16.7 33.3 ms EEPROM Read Time — — 1 2 4 tSYS EEPROM Write Timet — — 1 2 4 ms VDD Conditions System Reset Delay Time (Power On Reset, LVR reset, LVRC software reset, WDTC software reset) — System Reset Delay Time (RES reset, WDT normal reset) tEERD tEEWR tRSTD Note: tSYS=1/fSYS, tLXT=1/fLXT, tLIRC=1/fLIRC A/D Converter Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions AVDD Analog operating voltage — VREF=AVDD VAD A/D Input Voltage — 44-pin LQFP VREF A/D Input Reference Voltage Range DNL Min. Typ. Max. Unit 3.0 — 5.5 V 0 — VREF V — AVDD=5V 2.1 — AVDD+0.1 V A/C Differential Non-Linearity AVDD=5V, VREF=AVDD, — tAD=0.5µs −2 — 2 LSB INL ADC Integral Non-Linearity — AVDD=5V, VREF=AVDD, tAD=0.5µs −4 — 4 LSB IADC Additional Power Consumption if A/D Converter 3V is Used 5V — — 0.50 0.75 mA — 1.00 1.50 mA tAD A/D Converter Clock Period — — 0.5 — 10 µs tADC A/D Conversion Time (Include Sample and Hold Time) — 12-bit A/D Converter — 16 — tAD tADS A/D Sampling Time — — 4 — tAD tON2ST A/D on to A/D start — 2.7V~5.5V 2 — — µs — Note: ADC conversion time (tADC)=n (bits ADC) + 4 (sampling time). The conversion for each bit needs one ADC clock (tAD). Rev. 1.00 15 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter Conditions VDD Typ. Max. Unit IPOR DC Operating Current — — 0.7 µA VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD raising rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms 2.2V~5.5V Ta=25°C Min. DC/DC Converter and LDO Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions Conditions VDD Min. Typ. Max. Unit DC/DC VIN DC/DC Input Voltage — 5.500 V VO1DC/DC DC/DC Output Voltage 1 — VIN=2.8V~5.5V, VSEL=0 -5% 3.800 +5% V VO2DC/DC DC/DC Output Voltage 2 — VIN=2.8V~5.5V, VSEL=1 -5% 5.500 +5% V — VIN=4.75V, ISC=60mA, CPU Idle IVDD VDD Supply Current — 2.800 — — — 100 mA V 5V Regulator Output VIN DC/DC Input Voltage — 2.8 — 5.5 VCRDVCC Smart Card Power Supply Voltage — VO=5.5V, ISC=60mA — 4.6 5.0 5.4 V ISC Smart Card Supply Current — VO=5.5V, VCRDVCC=4.6V 60 — — mA IOCDET Current Overload Detection — 70 95 120 mA — 100 150 µA 170 — 1400 µs — IQUI Quiescent Current — VO=5.5V, CLOAD=4.7µF, No load current tIDET Detection Time on Current Overload — VO=5.5V, ISC from 60mA to 120mA tOFF VCRDVCC Turn Off Time — VO=5.5V, CLOAD=4.7μF, VCRDVCC from VCRDVCC to 0.4V — — 750 µs tON VCRDVCC Turn On Time — VO=5.5V, CLOAD=4.7μF, VCRDVCC from 0V to VCRDVCC (min.) — — 750 µs V5PWRGOOD LDO 5V Power Good Voltage — VO=5.5V, CLOAD=4.7μF 4.7 — — V V5RIPPLE Ripple on Card Voltage — VO=5.5V, CLOAD=4.7μF — — 200 mV Rev. 1.00 16 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Symbol Parameter Test Conditions Conditions VDD Min. Typ. Max. Unit 3V Regulator Output VIN DC/DC Input Voltage — VCRDVCC Smart Card Power Supply Voltage — VO=3.8V, ISC=55mA ISC Smart Card Supply Current — VO=3.8V, VCRDVCC=2.76V IOCDET Current Overload Detection — — — 2.80 — 5.50 2.76 3.00 3.24 V V 55 — — mA 70 95 120 mA 170 — 1400 µs tIDET Detection Time on Current Overload — VO=3.8V, ISC from 55mA to 120mA tOFF VCRDVCC Turn Off Time — VO=3.8V, CLOAD=4.7μF, VCRDVCC from VCRDVCC to 0.4V — — 750 µs tON VCRDVCC Turn On Time — VO=3.8V, CLOAD=4.7μF, VCRDVCC from 0V to VCRDVCC (min.) — — 750 µs V3PWRGOOD LDO 3V Power Good Voltage — VO=3.8V, CLOAD=4.7μF 2.8 — — V V3RIPPLE Ripple on Card Voltage — VO=3.8V, CLOAD=4.7μF — — 200 mV 1.8V Regulator Output VIN DC/DC is turned off 3.4 — 5.5 DC/DC Input Voltage — DC/DC must be turned on, VO=3.8V 2.8 — 3.4 1.66 1.80 1.94 V 35 — — mA 70 95 120 mA 170 — 1400 µs V VCRDVCC Smart Card Power Supply Voltage — ISC=35mA ISC Smart Card Supply Current — VCRDVCC=1.66V IOVDET Current Overload Detection — tIDET Detection Time on Current Overload (time for flag IOVF 0 → 1) — ISC=35mA → 120mA tON VCRDVCC Turn on Time (time for Card Voltage to reach min of VCRDVCC from 0V) — CLOAD≤4.7µF, Card voltage=0V to VCRDVCC (min.) — — 750 µs tOFF VCRDVCC Turn off Time (time for Card Voltage down to 0.4V) — CLOAD≤4.7µF, Card voltage=VCRDVCC to 0.4V — — 750 µs V18PWRGOOD LDO 1.8V Power Good Voltage — CLOAD=4.7µF 1.7 1.73 — V Ripple on card Voltage(VCRDVCC) — CLOAD=4.7µF — — 100 mV V18RIPPLE Rev. 1.00 — 17 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontrollers ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the external RC oscillator is used, OSC2 is free for use as a nomral I/O pin. System Clocking and Pipelining Rev. 1.00 18 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as ″JMP″ or ″CALL″ that demand a jump to a nonconsecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontrollers manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Mode Program Counter Bits b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Smart Card Interrupt 0 0 0 0 0 0 0 0 0 0 0 1 0 0 UART Interrupt 0 0 0 0 0 0 0 0 0 0 1 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 External Interrupt 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 0 1 0 1 0 0 Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Smart Card Insertion/Removal Interrupt 0 0 0 0 0 0 0 0 0 1 1 1 0 0 A/D Converter Interrupt 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Multi-Function 0 Interrupt 0 0 0 0 0 0 0 0 1 0 0 1 0 0 Multi-Function 1 Interrupt 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Skip Program Counter+2 (within current bank) Loading PCL PC13 PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S13 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 S12 Program Counter Note: PC13~PC8: Current Program Counter bits #12~#0: Instruction code address bits Rev. 1.00 @7~@0: PCL bits S13~S0: Stack register bits 19 BP.5: Bank pointer bit March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. And is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. P ro g ra m T o p o f S ta c k Rev. 1.00 S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 1 2 20 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Arithmetic and Logic Unit − ALU The arithmetic-logic unit or ALU is a critical area of the microcontrollers that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontrollers data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Flash Program Memory The Program Memory is the location where the user code or program is stored. For the device the Program Memory is an OTP type, which means it can be programmed only one time. By using the appropriate programming tools, this OTP memory device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming. Structure The Program Memory has a capacity of 16K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt-entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 0000H 000�H 00�8H 1FFFH �000H HT56RU�5 Reset Inte��upt Ve�to� 16 bits Bank 1 �FFFH Program Memory Structure Rev. 1.00 21 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts. Location 000H This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Location 004H This vector is used by the Smart Card interrupt. If a related Smart Card interrupt event occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Location 008H This vector is used by the UART interrupt. If the related UART interrupt event occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Location 00CH This vector is used by the external interrupt 0. If the related external interrupt pin receives an active edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Location 010H This vector is used by the external interrupt 1. If the related external interrupt pin receives an active edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Location 014H This internal vector is used by the Timer/Event Counter 0. If a Timer/Event Counter 0 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. Location 018H This internal vector is used by the Timer/Event Counter 1. If a Timer/Event Counter 1 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. Location 01CH This vector is used by the Smart Card Insertion/Removal interrupt. If a Smart Card Insertion or Removal event occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Location 020H This vector is reserved for the A/D Converter interrupt. If the completion of an A/D conversion occurs, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Rev. 1.00 22 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Location 024H This internal vector is used by the Multi-function 0 Interrupt. The Multi-function 0 Interrupt vector is shared by several internal functions such as a Serial Interface Module 0 interrupt, an active edge appearing on the External Peripheral interrupt pin, a Time Base overflow or a Real Time Clock overflow. The program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. Location 028H This internal vector is used by the Multi-function 1 Interrupt. The Multi-function 1 Interrupt vector is shared by several internal functions such as a Serial Interface Module 1 interrupt, a Timer/Event Counter 2 or a Timer/Event Counter 3 overflow. The program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer pair must first be setup by placing the address of the look up data to be retrieved in the table pointer register pair, TBLP and TBHP. This register pair defines the address of the look-up table. After setting up the table pointer pair, the table data can be retrieved from the specific Program Memory page or last Program Memory page using the ″TABRD [m]″ or ″TABRDL [m]″ instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. The following diagram illustrates the addressing/data flow of the look-up table: A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r Rev. 1.00 D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te 23 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the HT56RU25. This example uses raw table data located in the last page. The value at ″3F00H″ which refers to the start address of the last page within the 16K Program Memory of the HT56RU25 device. The table pointer is setup here to have an initial value of ″06H″. This will ensure that the first data read from the data table will be at the Program Memory address ″3F06H″ or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the TBLP and TBHP registers if the ″TABRD [m]″ instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ″TABRDL [m]″ instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example: Rombank 1 code1 ds .section 'data' Tempreg1 db ? ; temporaryregister#1 tempreg2 db ? ; temporaryregister#2 : : code0 .section 'code' mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,03fh ; initialise high table pointer mov tbhp,a ; it is not necessary to set tbhp if executing tabrdl : : tabrd tempreg1 tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog.memory address 3F06H transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address 3F05H transferred to tempreg2 and TBLH ; in this example the data 1AH is transferred to tempreg1 and data 0FH ; to tempreg2 ; the value 00H will be transferred to the high byte register TBLH : : code1 .section 'code' org 1F00h ; sets initial address of lastpage dc 00Ah,00Bh,00Ch,00Dh,00Eh,00Fh,01Ah,01Bh Rev. 1.00 24 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two parts, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The general purpose data memory is divided into several banks and switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. Structure The Data Memory is subdivided into several banks, all of which are implemented in 8-bit wide RAM. The Data Memory located in Bank 0 is subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The address of the Special Data Memory for the device is from address “00H” to “7FH”. Registers in Special Data Memory are common to the microcontroller, such as ACC, PCL, etc. Banks 3 to 11 contain only General Purpose Data Memory for the device with larger Data Memory capacities. As the Special Purpose Data Memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. Data Memory Capacity Banks Special Purpose 128×8 Common to Bank 0~11: 00H~7FH 1280×8 0: 80H~FFH 1~2: Unimplemented 3: 80H~FFH : : 11: 80H~FFH General Purpose 0 0 H S p e c ia l P u r p o s e D a ta M e m o ry 7 F H 8 0 H G e n e ra l P u rp o s e D a ta M e m o ry B a n k 0 F F H B a n k 3 B a n k 4 B a n k 1 1 Data Memory Structure Rev. 1.00 25 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. For the device with larger Data Memory capacities, the General Purpose Data Memory, in addition to being located in Bank 0, is also stored in Banks 3 to Bank 11. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both read and write type but some are protected and are read only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the unknow value. The Special Function registers are mapped into all banks and can therefore be accessed from any bank location. 00H 01H 0�H IAR0 �P0 IAR1 0�H �P1 0�H BP ACC PCL 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H TBLP TBLH �7H �8H �9H �AH �BH RTCC STATUS TBHP �CH �DH �EH �ISC0 �FH �0H �ISC1 CLKMOD DC�DC INTC0 11H INTC1 1�H INTC� Unused �FIC0 1�H 1�H 15H �FIC1 16H Unused 17H Unused PAWU PAPU 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH �0H �1H ��H ��H ��H �5H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH �0H �1H ��H ��H ��H �5H �6H PA PAC PBPU PB PBC PCPU PC PCC Unused Unused Unused Unused USR UCR1 UCR� BRG TXR_RXR PW�0L PW�0H PW�1L PW�1H PW��L PW��H PW��L PW��H �1H ��H ��H ��H �5H T�R0 T�R0C T�R1H T�R1L T�R1C T�R� T�R�C T�R� T�R�C Unused Unused Unused RCFLT ADRL ADRH ADCR ACSR ADPCR SI�0CTL0 �6H SI�0CTL1 �7H SI�0DR �8H SI�0AR/SI�0CTL� �9H SI�1CTL0 �AH SI�1CTL1 �BH SI�1DR �CH SI�1AR/SI�1CTL� �DH �EH �FH 50H 51H 5�H 5�H 5�H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H : : : 7FH DAL DAH DACTRL CCR CSR CCCR CETU1 CETU0 CGT1 CGT0 CWT� CWT1 CWT0 CIER CIPR CTXB CRXB Unused Unused Unused : Unused� �ead as “xx” Special Purpose Data Memory Rev. 1.00 26 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Special Function Registers Description To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address ″00H″. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a unknow value. Indirect Addressing Registers − IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ″00H″ and writing to the registers indirectly will result in no operation. Memory Pointers − MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks. The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. data .section ′data′ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ′code′ org 00h start: mov a,04h; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.00 27 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bank Pointer − BP The Data Memory is divided into a total of 30 banks. Selecting the required Data Memory area is achieved using the Bank Pointer. If data in Bank 0 is to be accessed, then the BP register must be loaded with the value 00H, while if data in Bank 3 is to be accessed, then the BP register must be loaded with the value 03H, and so on. The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. Bit 7 6 5 4 3 2 1 0 Name — — BP5 — BP3 BP2 BP1 BP0 R/W — — R/W — R/W R/W R/W R/W POR — — 0 — 0 0 0 0 Bit 7~6 Unimplemented, read as ″0″ Bit 5BP5: Program memory bank point 0: Program Memory Bank 0 1: Program Memory Bank 1 The Program Memory has the capacity of 16K words implemented as 8K words×2 Banks. Bit 4 Unimplemented, read as ″0″ Bit 3~0BP3~BP0: Data memory bank point 0000: General Purpose Data Memory Bank 0 0001~0010: Not exist 0011: General Purpose Data Memory Bank 3 0100: General Purpose Data Memory Bank 4 0101: General Purpose Data Memory Bank 5 0110: General Purpose Data Memory Bank 6 0111: General Purpose Data Memory Bank 7 1000: General Purpose Data Memory Bank 8 1001: General Purpose Data Memory Bank 9 1010: General Purpose Data Memory Bank 10 1011: General Purpose Data Memory Bank 11 Rev. 1.00 28 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Accumulator − ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register − PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers − TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP registers are the lower order byte and high order byte table pointers and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the ″INC″ or ″DEC″ instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.00 29 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Status Register − STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system powerup, a WDT time-out or by executing the ″CLR WDT″ or ″HALT″ instruction. The PDF flag is affected only by executing the ″HALT″ or ″CLR WDT″ instruction or during a system power-up. T h e Z , O V, A C an d C f la gs ge ne ra lly re fle c t the s ta tus of the la te s t ope ra tions . In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x ″x″ unknown Bit 7, 6 Unimplemented, read as ″0″ Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the ″CLR WDT″ or ″HALT″ instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the ″CLR WDT″ instruction 1: By executing the ″HALT″ instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation. C is also affected by a rotate through carry instruction. Rev. 1.00 30 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Interrupt Control Registers These 8-bit registers, known as INTC0, INTC1, INTC2, MFIC0, MFIC1 and MISC0, control the overall operations of the device interrupt functions. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within the INTC0 register, the EMI bit, acts like a global enable/disable control and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt subroutine is entered to disable further interrupt and is set by executing the ″RETI″ instruction. The MISC0 register is used to select the active edges for the two external interrupt pins INT0 and INT1. Timer/Event Counter Registers The device contains several internal 8-bit and 16-bit Timer/Event Counters. The registers TMR0, TMR2, TMR3 and the register pair TMR1L/TMR1H are the locations where the timer values are located. These registers can also be preloaded with fixed data to allow different time intervals to be setup. The associated control registers, TMR0C, TMR1C, TMR2C and TMR3C contain the setup information for these timers, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O data registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB and PC. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC and PCC also mapped to specific addresses within the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high while for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the ″SET [m].i″ and ″CLR [m].i″ instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Pulse Width Modulator Registers The device contains multiple Pulse Width Modulator outputs each with their own related independent control register pair, known as PWM0L/PWM0H, PWM1L/PWM1H, PWM2L/ PWM2H and PWM3L/PWM3H. The 12-bit contents of each register pair, which defines the duty cycle value for the modulation cycle of the Pulse Width Modulator, along with an enable bit are contained in these register pairs. Rev. 1.00 31 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces A/D Converter Registers − ADRL, ADRH, ADCR, ACSR The device contains a multiple channel 12-bit A/D converter. The correct operation of the A/ D requires the use of two data registers and two control registers. The two data registers, a high byte data register known as ADRH, and a low byte data register known as ADRL, are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. Functions such as the A/D enable/disable, A/D channel selection and A/D clock frequency are determined using the two control registers, ADCR and ACSR. Serial Interface Module Registers The device contains two Serial Interface Modules named SIM0 and SIM1 and each SIM contains an SPI and an I2C interface. The SIMxCTL0, SIMxCTL1, SIMxCTL2 and SIMxAR are the control registers for the Serial Interface function while the SIMxDR is the data register for the Serial Interface Data where x means 0 and 1. Port A Wake-up Register − PAWU All pins on Port A have a wake-up function enable a low going edge on these pins to wake-up the device when it is in a power down mode. The pins on Port A that are used to have a wake-up function are selected using this resister. Pull-High Registers − PAPU, PBPU, PCPU All I/O pins on Ports PA, PB and PC if setup as inputs, can be connected to an internal pullhigh resistor. The pins which require a pull-high resistor to be connected are selected using these registers. Clock Control Register − CLKMOD The device operates using a dual clock system whose mode is controlled using this register. The register controls functions such as the clock source, the idle mode enable and the division ratio for the slow clock. Miscellaneous Register − MISC0, MISC1 These registers name MISC0 and MISC1 are used to control the miscellaneous functions such as the active edge selection of the external interrupt pins, the clock divided ratio selection of the Smart Card and the Watchdog Timer enable control bits. There are also four bits used to determine if the output type is open drain or CMOS output for PA0~PA3. Rev. 1.00 32 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Input/Output Ports Holtek microcontroller offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides up to 24 bidirectional input/output lines labeled with port names PA, PB and PC. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction ″MOV A,[m]″, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU, PBPU and PCPU are implemented using weak PMOS transistors. PAWU, PAPU, PA, PAC, PBPU, PB, PBC, PCPU, PC and PCC Registers Bit Register Name POR 7 6 5 4 3 2 1 0 PAWU 00H PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU 00H PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA FFH PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC FFH PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PBPU 00H PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PB FFH PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC FFH PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PCPU 00H PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PC FFH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC FFH PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PAWUn: PA wake-up function enable 0: Disable 1: Enable PAPUn/PBPUn/PCPUn: Pull-high function enable 0: Disable 1: Enable PAn/PBn/PCn: I/O port data bit PACn/PBCn/PCCn: I/O port type selection bit 0: Output 1: Input Rev. 1.00 33 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Port A Wake-up The HALT instruction forces the microcontroller into a Power Down condition which preserves power, a feature that is important for battery and otuher low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a Power Down condition, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Port A Open Drain Function All I/O pins in the device have CMOS structures, however Port A pins PA0~PA3 can also be setup as open drain structures. This is implemented using the ODE0~ ODE3 bits in the MISC1 register. MISC1 Register Bit 7 6 5 4 Name ODE3 ODE2 ODE1 ODE0 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 1 0 1 0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Bit 7ODE3: PA3 Open Drain control 0: Disable 1: Enable Bit 6ODE2: PA2 Open Drain control 0: Disable 1: Enable Bit 5ODE1: PA1 Open Drain control 0: Disable 1: Enable Bit 4ODE0: PA0 Open Drain control 0: Disable 1: Enable Bit 3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable Described in Watchdog Timer section. I/O Port Control Registers Each I/O port has its own control register known as PAC, PBC, etc., to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a ″1″. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ″0″, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Rev. 1.00 34 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control. External Interrupt Inputs The external interrupt pins INT0 and INT1 are pin-shared with the I/O pins PA0 and PA1. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC0 register must be disabled. External Timer Clock Input The external timer pins TMR0, TMR1, TMR2 and TMR3 are pin-shared with I/O pins. To configure them to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set and the pin must also be setup as an input. Note that the original I/O function will remain even if the pin is setup to be used as an external timer input. PFD Output The device contains a PFD function whose single output is pin-shared with an I/O pin. The output function of this pin is chosen via a configuration option and remains fixed after the device is programmed. Note that the corresponding bit of the port control register must setup the pin as an output to enable the PFD output. If the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the PFD configuration option has been selected. Note that the PFD output fnction is only available for the 44-LQFP package type. PWM Outputs The device contains several PWM outputs name PWM0~PWM3 shared with I/O pins. The PWM output functions are chosen via registers. Note that the corresponding bit of the port control register bit must setup the pin as an output to enable the PWM output. If the port control register bit has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the PWM registers have enabled the PWM function. Note that the PWM output fnction is only available for the 44-LQFP package type. A/D Inputs The device contains multi-channel A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port A and Port C respectively. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor register remain, however if used as A/D inputs then any pull-high resistor selections associated with these pins will be automatically disconnected. Note that the A/D input fnction is only available for the 44-LQFP package type. Rev. 1.00 35 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces I/O Pin Structures The accompanying diagrams illustrate the internal structures of some I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure A/D Input/Output Structure Rev. 1.00 36 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC, PBC, etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, etc., are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the ″SET [m].i″ and ″CLR [m].i″ instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.00 37 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Timer/Event Counters The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The device contains several 8-bit and 16-bit count-up timers. As each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. The provision of a prescaler to the clock circuitry of the 8-bit Timer/Event Counter also gives added range to this timer. There are two types of registers related to the Timer/Event Counters. The first are the registers that contain the actual value of the Timer/Event Counter and into which an initial value can be preloaded. Reading from these registers retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and determines how the Timer/Event Counter is to be used. The Timer/Event Counters can have their clock configured to come from an internal clock source. In addition, their clock source can also be configured to come from an external timer pin. Configuring the Timer/Event Counter Input Clock Source The internal timer′s clock can originate from various sources. The system clock source is used when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode. For the 8-bit Timer/Event Counter this internal clock source is fSYS which is also divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register, TMRnC, bits TnPSC0~ TnPSC2. For the 16-bit Timer/Event Counter this internal clock source can be chosen from a combination of internal clocks using a configuration option and the TnS bit in the TMRnC register. An external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin TMR0, TMR1, TMR2 or TMR3 depending upon which timer is used. Depending upon the condition of the TnE bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Bits Data Register Control Register Timer/Event Counter 0 Name 8 TMR0 TMR0C Timer/Event Counter 1 16 TMR1H/TMR1L TMR1C Timer/Event Counter 2 8 TMR2 TMR2C Timer/Event Counter 3 8 TMR3 TMR3C 8-bit Timer/Event Counter Structure Rev. 1.00 38 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces 16-bit Timer/Event Counter Structure Timer/Event Counter Control Register − TMRnC (n=0, 2, 3) Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 — TnON TnE TnPSC2 TnPSC1 TnPSC0 R/W R/W R/W — R/W R/W R/W R/W R/W POR 0 0 — 0 1 0 0 0 Bit 7~6TnM1~TnM0: Timer/Event Counter Operating mode selection bit 00: No mode available 01: Event Counter mode 10: Timer mode 11: Pulse width measurement mode Bit 5 Unimplemented, read as ″0″ Bit 4TnON: Timer/Event Counter counting enable control 0: Disable 1: Enable Bit 3TnE: Timer/Event Counter active edge selection bits For Event counter mode: 0: Count on rising edge 1: Count on falling edge For Pulse width measurement mode: 0: Start counting on falling edge 1: Start counting on rising edge Bit 2~0TnPSC2~TnPSC0: Timer/Event Counter prescaler rate selection bits 000: 1/1 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 110: 1/64 111: 1/128 Rev. 1.00 39 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Timer/Event Counter Control Register − TMRnC (n=1) Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnS TnON TnE — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 1 — — — Bit 7~6TnM1~TnM0: Timer/Event Counter Operating mode selection bit 00: No mode available 01: Event Counter mode 10: Timer mode 11: Pulse width measurement mode Bit 5TnS: Timer/Event Counter clock source selection bit 0: fSYS/4 1: fSUB Bit 4TnON: Timer/Event Counter counting enable control 0: Disable 1: Enable Bit 3TnE: Timer/Event Counter active edge selection bits For Event counter mode: 0: Count on rising edge 1: Count on falling edge For Pulse width measurement mode: 0: Start counting on falling edge 1: Start counting on rising edge Bit 2~0 Unimplemented, read as ″0″ Timer Registers − TMR0, TMR1L/TMR1H, TMR2, TMR3 To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding Timer Control Register, which are known as the bit pair TnM1/TnM0, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as TnE. An additional TnS bit in the 16-bit Timer/Event Counter control register is used to determine the clock source for the Timer/Event Counter. Rev. 1.00 40 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Configuring the Timer Mode In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Bit6 Bit7 0 1 Control Register Operating Mode Select Bits for the Timer Mode Timer Mode Timing Chart In this mode the internal clock, fSYS, is used as the internal clock for 8-bit Timer/Event Counters and fSUB or fSYS/4 is used as the internal clock for 16-bit Timer/Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. Each time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. Rev. 1.00 41 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Bit6 Bit7 1 0 Control Register Operating Mode Select Bits for the Event Counter Mode Event Counter Mode Timing Chart In this mode, the external timer pin, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit, TnE, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Power Down Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wakeup source. Rev. 1.00 42 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Configuring the Pulse Width Measurement Mode In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/ TnM0, in the Timer Control Register must be set to the correct value as shown. Bit6 Bit7 1 1 Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode Pulse Width Measure Mode Timing Chart In this mode the internal clock, fSYS, is used as the internal clock for the 8-bit Timer/Event Counter and fSUB or fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the external timer pin. If the Active Edge Select bit TnE, which is bit 3 of the Timer Control Register, is low, once a high to low transition has been received on the external timer pin, the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the Pulse Width Measurement Mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily Made. It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode, the second is to ensure that the port control register configures the pin as an input. Rev. 1.00 43 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Programmable Frequency Divider − PFD The Programmable Frequency Divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. The PFD output is pin-shared with the I/O pin PC1. The PFD function is selected via configuration option, however, if not selected, the pin can operate as a normal I/O pin. The clock source for the PFD circuit can originate from either Timer/Event Counter 0 or Timer/ Event Counter 1 overflow signal selected via configuration option. The output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. The timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The timer will then be automatically reloaded with the preload register value and continue counting-up. For the PFD output to function, it is essential that the corresponding bit of the Port A control register PCC bit 1 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if bit PC1 is set to ″1″. This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PC1 output data bit is cleared to ″0″. Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. Note that the PFD function is only available for 44-LQFP package type. PFD Output Control Prescaler Bits TnPSC0~TnPSC2 of the control register can be used to define the pre-scaling stages of the internal clock source of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for the PFD and Timer Interrupt. Rev. 1.00 44 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of external pins for correct operation. As these pins are shared pins they must be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as a normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register must be set high to ensure that the pin is setup as an input. Any pull-high resistor on these pins will remain valid even if the pin is used as a Timer/Event Counter input. Timer/Event Counter Pins Internal Filter The external Timer/Event Counter pins are connected to an internal filter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the external Timer/Event Counter input signal. As this internal filter circuit will consume a limited amount of power, several control bits named TMnFLT in the RCFLT register are provided to switch off the filter function, a choice which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. RC Filter Control Register − RCFLT Bit 7 6 5 4 3 2 1 0 Name — — INT1FLT INT0FLT TM3FLT TM2FLT TM1FLT TM0FLT R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as ″0″ Bit 5INT1FLT: External Interrupt 1 input RC Filter enable control Described elsewhere. Bit 4INT0FLT: External Interrupt 0 input RC Filter enable control Described elsewhere. Bit 3TM3FLT: Timer/Event Counter 3 input RC Filter enable control 0: Disable 1: Enable Bit 2TM2FLT: Timer/Event Counter 2 input RC Filter enable control 0: Disable 1: Enable Bit 1TM1FLT: Timer/Event Counter 1 input RC Filter enable control 0: Disable 1: Enable Bit 0TM0FLT: Timer/Event Counter 0 input RC Filter enable control 0: Disable 1: Enable Rev. 1.00 45 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Rev. 1.00 46 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h; Smart Card interrupt vector reti org 08h; UART interrupt vector reti org 0ch ; External interrupt 0 vector reti org 10h ; External interrupt 1 vector reti org 14h ; Timer/Event Counter 0 interrupt vector jmp tmr0int ; jump here when the Timer/Event Counter 0 overflows : org 2Ch ; internal Timer/Event Counter 0 interrupt routine tmr0int: : ; Timer/Event Counter 0 main program placed here reti : : begin:; setup Timer 0 registers mov a,09bh ; setup Timer 0 preload value mov tmr0,a; mov a,081h ; setup Timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,002h ; timer 0 interrupt mov int1c,a set int0c.0 ; enable master interrupt set tmr0c.4 ; start Timer/Event Counter 0 - note mode bits must be previously setup Rev. 1.00 47 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Pulse Width Modulator The device contains a series of Pulse Width Modulation, PWM, outputs. Useful for the applications such as motor speed control, the PWM function provides an output with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. PWM Mode PWM Channels Output Pin Register Names PWM0 PC4 PWM0H/PWM0L PWM1 PC5 PWM1H/PWM1L PWM2 PC6 PWM2H/PWM2L PWM3 PA5 PWM3H/PWM3L 8+4 PWM Overview A register pair, located in the Data Memory is assigned to each Pulse Width Modulator output and are known as the PWM registers. It is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. The PWM registers also contain the enable/disable control bit for the PWM outputs. To increase the PWM modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. Note that it is only necessary to write the required modulation value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. The PWM clock source is the system clock fSYS. This method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is 12-bits wide, the overall PWM cycle frequency is fSYS/4096. However, when in the 8+4 mode of operation, the PWM modulation frequency will be fSYS/256. Rev. 1.00 PWM Modulation Frequency PWM Cycle Frequency PWM Cycle Duty fSYS/256 fSYS/4096 (PWM register value)/4096 48 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces 8+4 PWM Mode Modulation Each full PWM cycle, as it is 12-bits wide, has 4096 clock periods. However, in the 8+4 PWM mode, each PWM cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as ″i″ in the table. Each one of these sixteen sub-cycles contains 256 clock cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit 4~bit 11 is denoted here as the DC value. The second group which consists of bit 0~bit 3 is known as the AC value. In the 8+4 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. Parameter AC (0~15) DC (Duty Cycle) Modulation cycle i (i=0~15) i<AC (DC+1)/256 i≥AC DC/256 8+4 Mode Modulation Cycle Values The accompanying diagram illustrates the waveforms associated with the 8+4 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 16 individual modulation cycles, numbered 0~15 and how the AC value is related to the PWM value. PWM Output Control The four PWM0~PWM3 outputs are shared with I/O pins. To operate as a PWM output and not as an I/O pin, the relevant PWM enable control bit in PWMnL register must be set high where n denotes 0 from 3. A zero must also be written to the corresponding bit in the relevant port control register, to ensure that the PWM output pin is setup as an output. After these two initial steps have been carried out, and of course after the required PWM 12-bit value has been written into the PWM register pair register, writing a ″1″ to the corresponding port data register will enable the PWM data to appear on the pin. Writing a ″0″ to the bit will disable the PWM output function and force the output low. In this way, the Port data register bits, can also be used as an on/off control for the PWM function. Note that if the enable bit in the PWMnL register is set high to enable the PWM function, but a ″1″ has been written to its corresponding bit in the port control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. 8+4 PWM Mode Rev. 1.00 49 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces PWM Register Pairs − PWMnH/PWMnL (n=0~3) PWMnH Register Bit 7 6 5 4 3 2 1 0 Name D11 D10 D9 D8 D7 D6 D5 D4 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PWMnL Register Bit Name D3 D2 D1 D0 — — — PWMnEN R/W R/W R/W R/W R/W — — — R/W POR 0 0 0 0 — — — 0 ″—″ Unimplemented, read as ″0″ D11~D4: PWMn duty DC value D3~D0: PWMn duty AC value PWMnEN: PWMn output enable control 0: I/O pin enable 1: PWM output pin enable PWM Programming Example The following sample program shows how the PWM output is setup and controlled. mov a,64h ; setup PWM0 value to 1600 decimal which is 640H mov pwm0h,a ; setup PWM0H register value clr pwm0l ; setup PWM0L register value clr pcc.4 ; setup pin PC4 as an output set pwm0en ; set the PWM0 enable bit set pc.4 ; Enable the PWM0 output : : : : clr pc.4 ; PWM0 output disabled - PC4 will remain low Rev. 1.00 50 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Structure A/D Overview The device contains an 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. Input Channels Conversion Bits Input Pins 8 12 PA0~PA1, PC0~PC1, PA4~PA7 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Data Registers − ADRL, ADRH The device, which has an internal 12-bit A/D converter, requires two data registers, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. Only the high byte register, ADRH, utilises its full 8-bit contents. The low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. In the following table, D0~D11 is the A/D conversion data result bits. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ADRL D3 D2 D1 D0 — — — Bit0 — ADRH D11 D10 D9 D8 D7 D6 D5 D4 A/D Data Registers Rev. 1.00 51 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces A/D Converter Control Registers − ADCR, ADPCR, ACSR To control the function and operation of the A/D converter, three control registers known as ADCR, ADPCR and ACSR are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS2~ACS0 bits in the ADCR register define the channel number. As the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. The ADPCR control register contains the PCR7~PCR0 bits which determine which pins on I/O Ports are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the PCRn bit has a value of 1, the related I/O pin will be set as an analog input. If the PCRn bit is set to zero, then the related I/O pin will be setup as a normal I/O or other pin-shared functional pin. ACSR Register Bit 7 6 5 4 3 2 1 0 Name TEST ADONB ACS4 VBGEN VREFS ADCS2 ADCS1 ADCS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 0 0 0 0 0 0 Bit 7TEST: For test only, read as 1 Bit 6ADONB: A/D Converter enable control 0: A/D converter is turned on 1: A/D converter is turned off Bit 5ACS4: Internal Band-gap reference voltage channel input selection 0: A/D converter analog channel is connected to the analog input from AN0 to AN/7 1: A/D converter analog channel is connected to the internal Band-gap voltage VBG Bit 4VBGEN: Band-gap reference voltage enable control 0: Band-gap voltage VBG is disabled and connected to the ground 1: Band-gap voltage VBG is enabled The band-gap reference voltage VBG is used for the A/D converter and LVD/LVR function, which is controlled by the band-gap reference voltage enable bit VBGEN in the ACSR register. If the VBG is not used for the A/D converter and the LVD/LVR function is disabled, the microcontroller hardware will automatically turned off the band-gap reference voltage to conserve power. Care must be taken as when the VREFS bit is set high for the A/D converter, then a VBG turn on time tBG must be allowed before any A/D conversions are implemented. Bit 3VREFS: A/D converter reference voltage selection bit 0: From the internal voltage AVDD 1: From the external pin VREF The A/D reference voltage can come from either the internal voltage AVDD or the external voltage VREF, which is selected by the VREFS bit in the ACSR register. When the VREFS bit is cleared to 0, the reference voltage of the A/D converter comes from the internal A/D power supply AVDD and the external VREF pin can be used as an I/O pin or other pin-shared function. When the VREFS bit is set to 1, the reference voltage of the A/D converter comes from the external VREF pin and the I/O or other pin-shared functions are disabled. Rev. 1.00 52 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 2~0ADCS2~ADCS0: Select A/D converter clock source 000: fSYS/2 001: fSYS/8 010: fSYS/32 011: Undefined 100: fSYS 101: fSYS/4 110: fSYS/16 111: Undefined ADCR Register Bit 7 6 5 4 3 2 1 0 Name START EOCB — — — ACS2 ACS1 ACS0 R/W R/W R — — — R/W R/W R/W POR 0 1 — — — 0 0 0 Bit 7START: Start the A/D conversion 0→1→0: start 0→1: reset the A/D converter and set EOCB to ″1″ Bit 6EOCB: End of A/D Conversion flag 0: A/D conversion ended 1: A/D conversion waiting or in progress Bit 5~3 Unimplemented, read as ″0″ Bit 2~0ACS2~ACS0: A/D converter channel selection bits 000: AN0 is selected 001: AN1 is selected 010: AN2 is selected 011: AN3 is selected 100: AN4 is selected 101: AN5 is selected 110: AN6 is selected 111: AN7 is selected ADPCR Register Bit 7 6 5 4 3 2 1 0 Name PCR7 PCR6 PCR5 PCR4 PCR3 PCR2 PCR1 PCR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PCR7~PCR0: A/D converter analog channel configuration 0: I/O pin or other pin-shared function 1: A/D analog channel When the related bit is set to 1, the corresponding pin is used as an analog input and all other pin-shared functions are disabled automatically. Rev. 1.00 53 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces A/D Operation The START bit in the register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a ″1″ and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to ″0″ by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in the ACSR register. Controlling the on/off function of the A/D converter circuitry is implemented using the ADONB bit in the ACSR register. When the ADONB bit is cleared to 0, the A/D converter is enabled. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2~ADCS0, there are some limitations on the A/D clock source speed range that can be selected. As the recommended range of permissible A/D clock period, tAD, is from 0.5μs to 10μs, care must be taken for selected system clock frequencies. For example, if the system clock operates at a frequency of 4MHz or 2MHz, the ADCS2~ADCS0 bits should not be set to 100B or 010B respectively. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. fSYS A/D Clock Period (tAD) ADCS=000 ADCS=001 ADCS=010 ADCS=011 ADCS=100 ADCS=101 ADCS=110 ADCS=111 (tAD=2/fSYS) (tAD=8/fSYS) (tAD=32/fSYS) (undefined) (tAD=1/fSYS) (tAD=4/fSYS) (tAD=16/fSYS) (undefined) 1MHz 2µs 8µs 32µs* Undefined 1µs 4µs 16µs* Undefined 2MHz 1µs 4µs 16µs* Undefined 500ns 2µs 8µs Undefined 4MHz 500ns 2µs 8µs Undefined 250ns* 1µs 4µs Undefined 8MHz 250ns* 1µs 4µs Undefined 125ns* 500ns 2µs Undefined 12MHz 167ns* 667ns 2.67µs Undefined 83ns* 333ns* 1.33µs Undefined A/D Clock Period Examples Rev. 1.00 54 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A and Port C in the ADPCR register, determine whether the input pins are setup as normal input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the PCR7~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own power supply pins AVDD and AVSS and a VREF reference pin. The analog input values must not be allowed to exceed the value of VREF. Initialising the A/D Converter The internal A/D converter must be initialised in a special way. Each time the A/D channel selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not initialised after the channel selection bits are changed, the EOCB flag may have an undefined value, which may produce a false end of conversion signal. To initialise the A/D converter after the channel selection bits have changed, then the START bit in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCS2, ADCS1 and ADCS0 in the register. • Step 2 Enable the A/D by clearing the ADONB bit in the ACSR register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS2~ACS0 bits which are also contained in the register. • Step 4 Select which pins on the I/O port are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR7~PCR0 bits in the ADPCR register. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC0 interrupt control register must be set to ″1″ and the A/D converter interrupt enable bit, EADI, in the INTC2 register must also be set to ″1″. • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from ″0″ to ″1″ and then to ″0″ again. Note that this bit should have been originally set to ″0″. Rev. 1.00 55 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the bit in the ADCR register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. The setting up and operation of the A/D converter function is fully under the control of the application program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. A/D Conversion Timing Rev. 1.00 56 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Programming Considerations The A/D converter can be powered down by setting the ADONB bit in ACSR register to reduce power consumption. It is an important ability for some applications such as battery powered or handheld appliance. Another important programming consideration is that when the A/D channel selection bits change value, the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D converter is not required to be re-initialised. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr EADI; mov a,00000001B mov ACSR,a; mov a,0FH ; mov ADPCR,a, ; mov a,00H ; mov ADCR,a ; :; : :; : Start_conversion: clr START set START; clr START; Polling_: sz EOCB ; jmp polling_EOC ; mov a,ADRL ; mov adrl_buffer,a ; mov a,ADRH ; mov adrh_buffer,a ; : jmp start_conversion ; Rev. 1.00 disable ADC interrupt select fSYS/8 as A/D clock and turn on ADONB bit setup ADPCR register to configure I/O pins PA0~PA1 and PC0~PC1 as A/D inputs and select AN0 to be connected to the A/D converter As the analog channel configuration bits have changed the following START signal (0-1-0) must be issued instruction cycles reset A/D start A/D poll the ADCR register EOCB bit to detect end of A/D conversion continue polling read low byte conversion result value save result to user defined register read high byte conversion result value save result to user defined register start next A/D conversion 57 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Example: using the interrupt method to detect the end of conversion clr EADI; mov a,00000001B mov ACSR,a; mov a,0FH ; mov ADPCR,a ; mov a,00H ; mov ADCR,a ; :; : : Start_conversion: clr START set START; clr START; clr ADF ; set EADI; set EMI ; : : : ; ADC_: mov acc_stack,a ; mov a,STATUS mov status_stack,a ; : : mov a,ADRL ; mov adrl_buffer,a ; mov a,ADRH ; mov adrh_buffer,a ; : : EXIT__ISR: mov a,status_stack mov STATUS,a ; mov a,acc_stack ; clr ADF ; reti Rev. 1.00 disable ADC interrupt select fSYS/8 as A/D clock and turn on ADONB bit setup ADPCR register to configure I/O pins PA0~PA1 and PC0~PC1 as A/D inputs and select AN0 to be connected to the A/D converter As the analog channel configuration bits have changed the following START signal(0-1-0) must be issued instruction cycles reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable global interrupt ADC interrupt service routine save ACC to user defined memory save STATUS to user defined memory read save read save low byte conversion result value result to user defined register high byte conversion result value result to user defined register restore STATUS from user defined memory restore ACC from user defined memory clear ADC interrupt flag 58 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces A/D Transfer Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog input value of (VDD or VREF ) ÷ 4096). The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitized value will change at a point 1.5 LSB below the VDD or VREF level. Ideal A/D Transfer Function Rev. 1.00 59 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Serial Interface Function − SIM The device contains two Serial Interface Modules named SIM0 and SIM1 to implement Serial Interface Function, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using a bit in an internal register. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the MCU can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, here, as only a single select pin, SCSn, is provided only one slave device can be connected to the SPI bus. SPI Master/Slave Connection SPI Block Diagram Rev. 1.00 60 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIn, SDOn, SCKn and SCSn where n stands for 0 and 1 respectively. Pins SDIn and SDOn are the Serial Data Input and Serial Data Output lines, SCKn is the Serial Clock line and SCSn is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by selecting the SIMn enable configuration options and setting the correct bits in the SIMnCTL0/SIMnCTL2 register. After the SIMn configuration option has been configured it can also be additionally disabled or enabled using the SIMEN bit in the SIMnCTL0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As each SIM only contains a single SCSn pin, only one slave device can be utilized for each SIM. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge • WCOLn and CSENn bit enabled or disable select The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSENn, SIMnEN and SCSn. In the table I, Z represents an input floating condition. There are several configuration options associated with the SPI interface. One of these is to enable the SIMn function which selects the SIMn pins rather than normal I/O pins. Note that if the configuration option does not select the SIMn function then the SIMnEN bit in the SIMnCTL0 register will have no effect. Another two SIMn configuration options determine if the CSENn and WCOLn bits are to be used. Configuration Option Function SIMn Function SIMn interface or I/O pins SPI CSENn bit Enable/Disable SPI WCOLn bit Enable/Disable SPI Interface Configuration Options Pin Master/Slave SIMnEN=0 Master – SIMnEN=1 CSENn=1 CSENn=0 Slave – SIMnEN=1 CSENn=0 SCSn Line=0 (CSENn=1) SCSn Line=1 (CSENn=1) SCSn Z L Z Z I, Z I, Z SDOn Z O O O O Z SDIn Z I, Z I, Z I, Z I, Z Z Z H: CKPOLn=0 L: CKPOLn=1 H: CKPOLn=1 L: CKPOLn=0 I, Z I, Z Z SCKn Note: ″Z″ floating, ″H″ output high, ″L″ output low, ″I″ Input, ″O″output level, ″I, Z″ input floating (no pull-high) SPI Interface Pin Status Rev. 1.00 61 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces SPI Registers There are three internal registers which control the overall operation of the SPI interface for each SIM. These are the SIMnDR data register and two control registers SIMnCTL0 and SIMnCTL2. Note that the SIMnCTL1 register is only used by the I2C interface. There is a control bit, SIMIDLE, which is used to select whether the master SPI interface continues running when the device is in the IDLE mode. Setting the bit high allows the clock source of the master SPI interface or the Peripheral clock PCLK, which is selected to come from the divided system clock, to keep active when the device is in the IDLE mode. This will maintain the master SPI interface operation or the Peripheral clock PCLK output active if the PCKEN bit is set to 1 in IDLE mode. Clearing the bit to zero disables any master SPI interface operations or PCLK output in the IDLE mode. This SPI/I2C idle mode control bit, SIMIDLE, is located at CLKMOD register bit4. The SIMnDR register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the microcontroller writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMnDR register. After the data is received from the SPI bus, the microcontroller can read it from the SIMnDR register. Any transmission or reception of data from the SPI bus must be made via the SIMnDR register. • SIMnDR Bits 7 6 5 4 3 2 1 0 Name SnD7 SnD6 SnD5 SnD4 SnD3 SnD2 SnD1 SnD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR X X X X X X X X There are also two control registers for the SPI interface, SIMnCTL0 and SIMnCTL2. Note that the SIMnCTL2 register also has the name SIMnAR which is used by the I2C function. The SIMnCTL1 register is not used by the SPI function, only by the I2C function. Register SIMnCTL0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMnCTL0 register is also used to control the Peripheral Clock prescaler. Register SIMnCTL2 is used for other control functions such as LSB/MSB selection, write collision flag etc. Rev. 1.00 62 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • SIM0 Control Register 0 − SIM0CTL0 Bit 7 6 5 Name S0SIM2 S0SIM1 S0SIM0 4 3 2 1 R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — PCKEN PCKPSC1 PCKPSC0 SIM0EN 0 — Bit 7~5S0SIM2~S0SIM0: SIM0 mode and clock selection 000: SIM0 in SPI master mode with fSYS/4 clock source 001: SIM0 in SPI master mode with fSYS/16 clock source 010: SIM0 in SPI master mode with fSYS/64 clock source 011: SIM0 in SPI master mode with fSUB clock source 100: SIM0 in SPI master mode with Timer/Event Counter 0 overflow/2 clock (PFD0) 101: SIM0 in SPI slave mode 110: SIM0 in I2C mode 111: Reserved Bit 4PCKEN: Peripheral Clock PCK enable control 0: PCK output is disabled 1: PCK output is enabled Bit 3~2PCKPSC1~PCKPSC0: Peripheral Clock PCK output clock prescaler 00: fSYS 01: fSYS/4 10: fSYS/8 11: Timer/Event Counter 0 overflow /2 (PFD0) Bit 1SIM0EN: SIM0 enable control 0: SIM0 is disabled 1: SIM0 is enabled Bit 0 Unimplemented, read as ″0″ • SIM1 Control Register 0 − SIM1CTL0 Bit 7 6 5 4 3 2 1 0 Name S1SIM2 S1SIM1 S1SIM0 D4 D3 D2 SIM1EN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5S1SIM2~S1SIM0: SIM1 mode and clock selection 000: SIM1 in SPI master mode with fSYS/4 clock source 001: SIM1 in SPI master mode with fSYS/16 clock source 010: SIM1 in SPI master mode with fSYS/64 clock source 011: SIM1 in SPI master mode with fSUB clock source 100: SIM1 in SPI master mode with Timer/Event Counter 0 overflow/2 clock (PFD0) 101: SIM1 in SPI slave mode 110: SIM1 in I2C mode 111: Reserved Bit 4~2 Undefined bit These bits can be read or written by user software program. Bit 1SIM1EN: SIM1 enable control 0: SIM1 is disabled 1: SIM1 is enabled Bit 0 Rev. 1.00 Unimplemented, read as ″0″ 63 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • SIMn Control Register 1 − SIMnCTL1 (n=0 or 1) for I2C Mode Bit 7 6 5 4 3 2 1 0 Name HCFn HAASn HBBn HTXn TXAKn SRWn — RXAKn R/W R/W R/W R/W R/W R/W R/W — R/W POR 1 0 0 0 0 0 — 0 Bit 7HCFn: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCFn flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6HAASn: I2C Bus address match flag 0: No address match 1: Address match The HAASn flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match, then this bit will be high. If there is no address match, then the flag will be low. Bit 5HBBn: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBBn flag is the I2C busy flag. This flag will be 1 when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to 0 when the bus is free which will occur when a STOP signal is detected. Bit 4HTXn: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAKn: I2C Bus transmit acknowledge flag 0: Slave sends acknowledge flag 1: Slave does not send acknowledge flag The TXAKn bit is the transmit acknowledge flag. After the slave device receipt of 8-bit of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAKn bit to 0 before further data is received. Bit 2SRWn: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRWn flag is the I2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data to or from the I2C bus. When the transmitted address and slave address is match, that is when the HAASn flag is set high, the slave device will check the SRWn flag to determine whether it should be in transmit mode or receive mode. If the SRWn flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRWn flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 Unimplemented, read as ″0″ Bit 0RXAKn: I2C Bus Receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAKn flag is the receiver acknowledge flag. When the RXAKn flag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAKn flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAKn flag is 1. When this occurs, the slave transmitter will release the SDAn line to allow the master to send a STOP signal to release the I2C Bus. Rev. 1.00 64 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • SIMn Control Register 2 − SIMnCTL2 (n=0 or 1) for SPI Mode Bit 7 6 5 4 3 2 1 0 Name — — CKPOLn CKEG MLSn CSENn WCOLn TRFn R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Undefined bit, read as "0" Bit 5CKPOLn: Determines the base condition of the SPI clock line 0: The SCKn line will be high when the SPI clock is inactive 1: The SCKn line will be low when the SPI clock is inactive The CKPOLn bit determines the base condition of the SPI clock line, if the bit is high, then the SCKn line will be low when the clock is inactive. When the CKPOLn bit is low, then the SCKn line will be high when the clock is inactive. Bit 4CKEG: Determines SPI SCKn active clock edge type CKPOLn=0 0: SCKn is high base level and data capture at SCKn rising edge 1: SCKn is high base level and data capture at SCKn falling edge CKPOLn=1 0: SCKn is low base level and data capture at SCKn falling edge 1: SCKn is low base level and data capture at SCKn rising edge The CKEGn and CKPOLn bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLn bit determines the base condition of the clock line. If the bit is high, then the SCKn line will be low when the clock is inactive. When the CKPOLn bit is low, then the SCKn line will be high when the clock is inactive. The CKEGn bit determines active clock edge type which depends upon the condition of CKPOLn bit. Bit 3MLSn: SPI Data shift order 0: LSB shift first 1: MSB shift first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2CSENn: SPI SCSn pin control 0: Disable 1: Enable The CSENn bit is used as an enable/disable for the SCSn pin. If this bit is low, then the SCSn pin will be disabled and placed into a floating condition. If the bit is high the SCSn pin will be enabled and used as a select pin. Note that using the CSENn bit can be disabled or enabled via configuration option. Bit 1WCOLn: SPI Write Collision flag 0: No collision 1: Collision The WCOLn flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMnDR register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOLn bit can be disabled or enabled via configuration option. Bit 0TRFn: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRFn bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI data transmission is completed, but must set to 0 by the application program. It can be used to generate an interrupt. Rev. 1.00 65 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces SPI Communication After the SPI interface is enabled by setting the SIMnEN bit high, then in the Master Mode, when data is written to the SIMnDR register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRFn flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMnDR register will be transmitted and any data on the SDIn pin will be shifted into the SIMnDR register. The master should output a SCSn signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled before/after a SCSn signal is received. The SPI will continue to function even after a HALT instruction has been executed. SPI Master Mode Timing SPI Slave Mode Timing (CKEGn=0) Rev. 1.00 66 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces SPI Slave Mode Timing (CKEGn=1) SPI Transfer Control Flowchart Rev. 1.00 67 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Block Diagram I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCLn. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. There are several configuration options associated with the I2C interface. One of these is to enable the function which selects the SIMn pins rather than normal I/O pins. Note that if the configuration option does not select the SIMn function then the SIMnEN bit in the SIMnCTL0 register will have no effect. A configuration option exists to allow a clock other than the system clock to drive the I2C interface. Another configuration option determines the debounce time of the I2C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. Configuration Option SIMn function I2C debounce Function SIMn interface or I/O pins No debounce, 1 system clock; 2 system clocks I2C Interface Configuration Options Rev. 1.00 68 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces I2C Registers There are three control registers associated with the I2C bus, SIMnCTL0, SIMnCTL1 and SIMnAR and one data register, SIMnDR. The SIMnDR register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMnDR register. After the data is received from the I2C bus, the microcontroller can read it from the SIMnDR register. Any transmission or reception of data from the I2C bus must be made via the SIMnDR register. Note that the SIMnAR register also has the name SIMnCTL2 which is used by the SPI function. Bits SIMIDLE, SIMnEN and bits SnSIM0~SnSIM2 in register SIMnCTL0 are used by the I2C interface. When the device is in the IDLE mode, the SIMIDLE bit has no effect if the I2C interface is selected to be used. Setting the bit high only allows the clock source of the Peripheral clock PCLK, which is selected to come from the divided system clock, to keep active when the device is in the IDLE mode. It will maintain the Peripheral clock PCLK output active if the PCKEN bit is set to 1 in IDLE mode. Clearing the bit to zero disables the PCLK output when the device is in the IDLE mode. This SPI/I2C idle mode control bit, SIMIDLE, is located at CLKMOD register bit 4. • SIMnDR Bits 7 6 5 4 3 2 1 0 Name SnD7 SnD6 SnD5 SnD4 SnD3 SnD2 SnD1 SnD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR X X X X X X X X “x”: unknown • SIMnAR Register Bit 7 6 5 4 3 2 1 0 Name SnA6 SnA5 SnA4 SnA3 SnA2 SnA1 SnA0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR x x x x x x x — “x”: unknown Bit 7~1SnA6~SnA0: I2C slave address SnA6~SnA0 is the I2C slave address bit6~bit0. The SIMnAR register is also used by the SPI interface but has the name SIMnCTL2. The SIMnAR register is the location where the 7-bit slave address of the slave device is stored. Bit7~bit1 of the SIMnAR register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMnAR register, the slave device will be selected. Note that the SIMnAR register is the same register address as SIMnCTL2 which is used by the SPI interface. Bit 0 Rev. 1.00 Unimplemented bit This bit can be read or written by user software program. 69 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • SIM0 Control Register 0 – SIM0CTL0 Bit 7 6 5 Name S0SIM2 S0SIM1 S0SIM0 4 3 2 1 R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — PCKEN PCKPSC1 PCKPSC0 SIM0EN 0 — Bit 7~5S0SIM2~S0SIM0: SIM0 mode and clock selection 000: SIM0 in SPI master mode with fSYS/4 clock source 001: SIM0 in SPI master mode with fSYS/16 clock source 010: SIM0 in SPI master mode with fSYS/64 clock source 011: SIM0 in SPI master mode with fSUB clock source 100: SIM0 in SPI master mode with Timer/Event Counter 0 overflow/2 clock (PFD0) 101: SIM0 in SPI slave mode 110: SIM0 in I2C mode 111: Reserved Bit 4PCKEN: Peripheral Clock PCK enable control 0: PCK output is disabled 1: PCK output is enabled Bit 3~2PCKPSC1~PCKPSC0: Peripheral Clock PCK output clock prescaler 00: fSYS 01: fSYS/4 10: fSYS/8 11: Timer/Event Counter 0 overflow /2 (PFD0) Bit 1SIM0EN: SIM0 enable control 0: SIM0 is disabled 1: SIM0 is enabled Bit 0 Unimplemented, read as “0” • SIM1 Control Register 0 – SIM1CTL0 Bit 7 6 5 4 3 2 1 0 Name S1SIM2 S1SIM1 S1SIM0 D4 D3 D2 SIM1EN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5S1SIM2~S1SIM0: SIM1 mode and clock selection 000: SIM1 in SPI master mode with fSYS/4 clock source 001: SIM1 in SPI master mode with fSYS/16 clock source 010: SIM1 in SPI master mode with fSYS/64 clock source 011: SIM1 in SPI master mode with fSUB clock source 100: SIM1 in SPI master mode with Timer/Event Counter 0 overflow/2 clock (PFD0) 101: SIM1 in SPI slave mode 110: SIM1 in I2C mode 111: Reserved Bit 4~2 Undefined bit These bits can be read or written by user software program. Bit 1SIM1EN: SIM1 enable control 0: SIM1 is disabled 1: SIM1 is enabled Bit 0 Rev. 1.00 Unimplemented, read as “0” 70 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • SIMn Control Register 1 – SIMnCTL1 (n=0 or 1) for I2C mode Bit 7 6 5 4 3 2 1 0 Name HCFn HAASn HBBn HTXn TXAKn SRWn — RXAKn R/W R/W R/W R/W R/W R/W R/W — R/W POR 1 0 0 0 0 0 — 0 Bit 7HCFn: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCFn flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6HAASn: I2C Bus address match flag 0: No address match 1: Address match The HAASn flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match, then this bit will be high. If there is no address match, then the flag will be low. Bit 5HBBn: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBBn flag is the I2C busy flag. This flag will be 1 when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to 0 when the bus is free which will occur when a STOP signal is detected. Bit 4HTXn: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAKn: I2C Bus transmit acknowledge flag 0: Slave sends acknowledge flag 1: Slave does not send acknowledge flag The TXAKn bit is the transmit acknowledge flag. After the slave device receipt of 8-bit of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAKn bit to 0 before further data is received. Bit 2SRWn: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRWn flag is the I2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data to or from the I2C bus. When the transmitted address and slave address is match, that is when the HAASn flag is set high, the slave device will check the SRWn flag to determine whether it should be in transmit mode or receive mode. If the SRWn flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRWn flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 Unimplemented, read as “0” Bit 0RXAKn: I2C Bus Receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAKn flag is the receiver acknowledge flag. When the RXAKn flag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAKn flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAKn flag is 1. When this occurs, the slave transmitter will release the SDAn line to allow the master to send a STOP signal to release the I2C Bus. Rev. 1.00 71 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the microcontroller matches that of the transmitted address, the HAASn bit in the SIMnCTL1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the microcontroller slave device must first check the condition of the HAASn bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRWn bit. This bit will be checked by the microcontroller to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus. The following are steps to achieve this: • Step 1 Write the slave address of the microcontroller to the I2C bus address register SIMnAR. • Step 2 Set the SIMnEN bit in the SIMnCTL0 register to ″1″ to enable the I2C bus. • Step 3 Set the ESIMn bit of the interrupt control register to enable the I2C bus interrupt. I2C Bus Initialisation Flow Chart Rev. 1.00 72 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the microcontroller, which is only a slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBBn bit will be set. A START condition occurs when a high to low transition on the SDAn line takes place when the SCLn line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRWn bit of the SIMnCTL1 register. The device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The microcontroller slave device will also set the status flag HAASn when the addresses match. As an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAASn bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMnDR register, or in the receive mode where it must implement a dummy read from the SIMnDR register to release the SCLn line. SRW Bit The SRWn bit in the SIMnCTL1 register defines whether the microcontroller slave device wishes to read data from the I2C bus or write data to the I2C bus. The microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. If the SRWn bit is set to ″1″ then this indicates that the master wishes to read data from the I2C bus, therefore the microcontroller slave device must be setup to send data to the I2C bus as a transmitter. If the SRWn bit is ″0″ then this indicates that the master wishes to send data to the I2C bus, therefore the microcontroller slave device must be setup to read data from the I2C bus as a receiver. Acknowledge Bit After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. This acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAASn bit is high, the addresses have matched and the microcontroller slave device must check the SRWn bit to determine if it is to be a transmitter or a receiver. If the SRWn bit is high, the microcontroller slave device should be setup to be a transmitter so the HTXn bit in the SIMnCTL1 register should be set to ″1″ if the SRWn bit is low then the microcontroller slave device should be setup as a receiver and the HTXn bit in the SIMnCTL1 register should be set to ″0″. Rev. 1.00 73 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Data Byte The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level ″0″, before it can receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the SDAn line and the master will send out a STOP signal to release control of the I2C bus. The corresponding data will be stored in the SIMnDR register. If setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the SIMnDR register. If setup as a receiver, the microcontroller slave device must read the transmitted data from the SIMnDR register. Receive Acknowledge Bit When the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as TXAKn, on the 9th clock. The microcontroller slave device, which is setup as a transmitter will check the RXAKn bit in the SIMnCTL1 register to determine if it is to send another data byte, if not then it will release the SDAn line and await the receipt of a STOP signal from the master. Data Timing Diagram I2C Communication Timing Diagram Rev. 1.00 74 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces I2C Bus ISR Flow Chart Rev. 1.00 75 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCLK, is shared with an I/O line, the required pin function is chosen via PCKEN in the SIM0CTL0 register. The Peripheral Clock function is controlled using the SIM0CTL0 register. The clock source for the Peripheral Clock Output can originate from either the Timer/Event Counter 0 overflow signal divided by two or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIM0CTL0 register is the overall on/off control, setting the bit high enables the Peripheral Clock, clearing it disables it. The required division ratio of the system clock is selected using the PCKPSC0 and PCKPSC1 bits in the same register. If the system enters the Sleep Mode, the Peripheral Clock output will be disabled. Peripheral Clock Block Diagram Rev. 1.00 76 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Buzzer Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complementary pair, and are pin-shared with I/O pins, PA0 and PA1. A configuration option is used to select from one of three buzzer options. The first option is for both pins PA0 and PA1 to be used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third option selects only the PA0 pin to be used as a BZ buzzer pin with the PA1 pin retaining its normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. The buzzer is driven by the internal clock source, which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22 to fS/29. The clock source that generates fS, which in turn controls the buzzer frequency, can originate from three different sources, the external 32.768kHz oscillator (LXT), the internal 32kHz RC oscillator (LIRC) or the System oscillator divided by 4 (fSYS/4), the choice of which is determined by the fS clock source configuration option. Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio. There are no internal registers associated with the buzzer frequency. If the configuration options have selected both pins PA0 and PA1 to function as a BZ and BZ complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits PAC0 and PAC1 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer outputs, if set low, both pins PA0 and PA1 will remain low. In this way the single bit PA0 of the PA register can be used as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PA1 data bit in the PA register has no control over the BZ buzzer pin PA1. Buzzer Function Rev. 1.00 77 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces PA0/PA1 Pin Function Control PAC Register PAC0 PAC Register PAC1 PA Data Register PA0 PA Data Register PA1 0 0 1 x PA0=BZ PA1=BZ 0 0 0 x PA0=″0″ PA1=″0″ 0 1 1 x PA0=BZ PA1=input line 0 1 0 x PA0=″0″ PA1=input line 1 0 x D PA0=input line PA1=D 1 1 x x PA0=input line PA0=input line Output Function ″x" stands for don′t care, ″D″ stands for Data ″0″ or ″1″ If configuration options have selected that only the PA0 pin is to function as a BZ buzzer pin, then the PA1 pin can be used as a normal I/O pin. For the PA0 pin to function as a BZ buzzer pin, PA0 must be setup as an output by setting bit PAC0 of the PAC port control register to zero. The PA0 data bit in the PA data register must also be set high to enable the buzzer output, if set low pin PA0 will remain low. In this way the PA0 bit can be used as an on/off control for the BZ buzzer pin PA0. If the PAC0 bit of the PAC port control register is set high, then pin PA0 can still be used as an input even though the configuration option has configured it as a BZ buzzer output. Buzzer Output Pin Control Note: The above drawing shows the situation where both pins PA0 and PA1 are selected by configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as output. The data setup on pin PA1 has no effect on the buzzer outputs. Note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the configuration option selection and force the pin to always behave as an input pin. This arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit. Rev. 1.00 78 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are controlled by the action of the external INT0, INT1 and PINT pins, while the internal interrupts are controlled by the Timer/Event Counter overflows, the Time Base interrupt, the RTC interrupt, the SIM (SPI/I2C) interrupt, the A/D converter interrupt, the UART interrupt and Smart Card interrupt. Interrupt Structure Rev. 1.00 79 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Interrupt Registers Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the INTC0, INTC1, INTC2, MFIC0 and MFIC1 registers, which are located in the Data Memory. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — EIF0 URF CRDF EEI0 URE CRDE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as ″0″ Bit 6EIF0: External interrupt 0 interrupt request flag 0: Inactive 1: Active Bit 5URF: UART interrupt request flag 0: Inactive 1: Active Bit 4CRDF: Smart Card interrupt request flag 0: Inactive 1: Active Bit 3EEI0: External interrupt 0 enable 0: Disable 1: Enable Bit 2URE: UART interrupt enable 0: Disable 1: Enable Bit 1CRDE: Smart Card interrupt enable 0: Disable 1: Enable Bit 0EMI: Master interrupt global enable 0: Disable 1: Enable Rev. 1.00 80 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces INTC1 Register Bit 7 6 5 4 3 2 1 0 Name SCIRF T1F T0F EIF1 CIRE ET1I ET0I EEI1 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7SCIRF: Smart Card Insertion/Removal interrupt request flag 0: Inactive 1: Active This bit is triggered by the CIRF bit of CSR register. Bit 6T1F: Timer/Event Counter 1 interrupt request flag 0: Inactive 1: Active Bit 5T0F: Timer/Event Counter 0 interrupt request flag 0: Inactive 1: Active Bit 4EIF1: External interrupt 1 request flag 0: Inactive 1: Active Bit 3CIRE: Smart Card Insertion/Removal interrupt enable 0: Disable 1: Enable Bit 2ET1I: Timer/Event Counter 1 interrupt enable 0: Disable 1: Enable Bit 1ET0I: Timer/Event Counter 0 interrupt enable 0: Disable 1: Enable Bit 0EEI1: External interrupt 1 interrupt enable 0: Disable 1: Enable Rev. 1.00 81 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces INTC2 Register Bit 7 6 5 4 3 2 1 0 Name — MF1F MF0F ADF — EMF1I EMF0I EADI R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as ″0″ Bit 6MF1F: Multi-Function 1 interrupt request flag 0: Inactive 1: Active Bit 5MF0F: Multi-function 0 interrupt request flag 0: Inactive 1: Active Bit 4ADF: A/D Converter interrupt request flag 0: Inactive 1: Active Bit 3 Unimplemented, read as ″0″ Bit 2EMF1I: Multi-Function 1 interrupt enable 0: Disable 1: Enable Bit 1EMF0I: Multi-Function 0 interrupt enable 0: Disable 1: Enable Bit 0EADI: A/D Converter interrupt enable 0: Disable 1: Enable Rev. 1.00 82 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces MFIC0 Register Bit 7 6 5 4 3 2 1 0 Name PEF TBF RTF SIM0F EPI ETBI ERTI ESIM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7PEF: External Peripheral interrupt request flag 0: Inactive 1: Active Bit 6TBF: Time Base interrupt request flag 0: Inactive 1: Active Bit 5RTF: Real Time Clock interrupt request flag 0: Inactive 1: Active Bit 4SIM0F: SIM 0 (SPI/I2C) interrupt request flag 0: Inactive 1: Active Bit 3EPI: External Peripheral interrupt enable 0: Disable 1: Enable Bit 2ETBI: Time Base interrupt enable 0: Disable 1: Enable Bit 1ERTI: Real Time Clock interrupt enable 0: Disable 1: Enable Bit 0ESIM0: SIM 0 (SPI/I2C) interrupt enable 0: Disable 1: Enable Rev. 1.00 83 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces MFIC1 Register Bit 7 6 5 4 3 2 1 0 Name — T3F T2F SIM1F — ET3I ET2I ESIM1 R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as ″0″ Bit 6T3F: Timer/Event Counter 3 interrupt request flag 0: Inactive 1: Active Bit 5T2F: Timer/Event Counter 2 interrupt request flag 0: Inactive 1: Active Bit 4SIM1F: SIM 1 (SPI/I2C) interrupt request flag 0: Inactive 1: Active Bit 3 Unimplemented, read as ″0″ Bit 2ET3I: Timer/Event Counter 3 interrupt enable 0: Disable 1: Enable Bit 1ET2I: Timer/Event Counter 2 interrupt enable 0: Disable 1: Enable Bit 0ESIM1: SIM 1 (SPI/I2C) interrupt enable 0: Disable 1: Enable Interrupt Operation A Timer/Event Counter overflow, Time Base, RTC overflow, SPI/I2C data transfer complete, an end of A/D conversion, UART event, Smart Card event, Smart Card insertion/removal or the external interrupt line being triggered will all generate an interrupt request by setting their corresponding request flag. When this happens and if their appropriate interrupt enable bit is set, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Rev. 1.00 84 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. Priority Vector Smart Card Interrupt Interrupt Source 1 04H UART Interrupt 2 08H External Interrupt 0 3 0CH External Interrupt 1 4 10H Timer/Event Counter 0 Overflow 5 14H Timer/Event Counter 1 Overflow 6 18H Smart Card Insertion/Removal Interrupt 7 1CH A/D Converter Interrupt 8 20H Multi-function 0 Interrupt 9 24H Multi-function 1 Interrupt 10 28H The SIM0 interrupt, Real Time clock interrupt, Time Base interrupt and External Peripheral interrupt share the same interrupt vector which is 24H while the SIM1 interrupt, Timer/Event Counter 2 overflow and Timer/Event Counter 3 overflow interrupt share the same interrupt vector which is 28H. Each of these interrupts has their own individual interrupt flag but also share the same multi-function interrupt flag named MF0F or MF1F respectively. The MF0F or MF1F flag will be cleared by hardware once the corresponding Multi-function interrupt is serviced. However the individual interrupts that have triggered the Multi-function interrupt need to be cleared by the application program. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bits, EEI0 and EEI1, must first be set. Additionally the correct interrupt edge type must be selected using the MISC0 register to enable the external interrupt function and to choose the trigger edge type. An actual external interrupt will take place when the external interrupt request flag, EIF0 or EIF1, is set, a situation that will occur when a transition, whose type is chosen by the edge select bit, appears on the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PA0 and PA1 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the INTC0 or INTC1 register has been set. The pin must also be setup as an input by setting the corresponding PAC.0 and PAC.1 bits in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 0CH or 10H, will take place. When the interrupt is serviced, the external interrupt request flags, EIF0 or EIF1, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. The MISC0 register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising, falling or both rising and falling edge types can be chosen to trigger an external interrupt. Note that the MISC0 register can also be used to disable the external interrupt function. The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal. As this internal filter circuit will consume a limited amount of power, the software control bits named INT0FLT and INT1FLT respectively in the RCFLT register are provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. Rev. 1.00 85 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces MISC0 Register Bit Name 7 6 CRDCKS1 CRDCKS0 5 4 3 2 1 0 SMF SMCEN INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6CRDCKS1~CRDCKS0: Smart Card interface clock source divided ratio selection Described elsewhere Bit 5SMF: Smart Card clock output CCLK frequency fCCLK selection Described elsewhere Bit 4SMCEN: Smart Card interface clock control Described elsewhere Bit 3~2INT1S1~INT1S0: External Interrupt 1 active edge selection 00: Disabled 01: Rising edge trigger 10: Falling edge trigger 11: Both rising and falling edges trigger Bit 1~0INT0S1~INT0S0: External Interrupt 0 active edge selection 00: Disabled 01: Rising edge trigger 10: Falling edge trigger 11: Both rising and falling edges trigger RC Filter Control Register – RCFLT Bit 7 6 5 4 3 2 1 0 Name — — INT1FLT INT0FLT TM3FLT TM2FLT TM1FLT TM0FLT R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as ″0″ Bit 5INT1FLT: External Interrupt 1 input RC Filter enable control 0: Disabled 1: Enable Bit 4INT0FLT: External Interrupt 0 input RC Filter enable control 0: Disabled 1: Enable Bit 3TM3FLT: Timer/Event Counter 3 input RC Filter enable control Described elsewhere. Bit 2TM2FLT: Timer/Event Counter 2 input RC Filter enable control Described elsewhere. Bit 1TM1FLT: Timer/Event Counter 1 input RC Filter enable control Described elsewhere. Bit 0TM0FLT: Timer/Event Counter 0 input RC Filter enable control Described elsewhere. Rev. 1.00 86 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function 0 interrupt. For an external peripheral interrupt to occur, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, EPI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An actual external peripheral interrupt will take place when the external interrupt request flag, PEF, is set, a situation that will occur when a negative transition, appears on the PINT pin. The external peripheral interrupt pin is pin-shared with one of the I/O pins, and is configured as a peripheral interrupt pin via the corresponding port control register bit. When the interrupt is enabled, the stack is not full and a negative transition type appears on the external peripheral interrupt pin, a subroutine call to the Multi-function interrupt vector at location 24H, will take place. When the external peripheral interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MF0F interrupt request flag will be reset. As the PEF flag will not be automatically reset, it has to be cleared by the application program. Timer/Event Counter Interrupt For a Timer/Event Counter 0 or Timer/Event Counter 1 interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, ET0I or ET1I must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, T0F or T1F is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 14H or 18H, will take place. When the interrupt is serviced, the timer interrupt request flag, T0F or T1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Timer Event Counter 0 and Timer/Event Counter 1 have their own individual interrupt vectors. However the interrupt vector for Timer/Event Counter 2 or Timer/Event counter 3 is contained within the Multi-function 1 Interrupt. For a Timer/Event Counter 2 or a Timer/Event counter 3 interrupt to occur, the global interrupt enable bit, EMI, Timer/Event Counter 2 or Timer/Event counter 3 interrupt enable bit, ET2I or ET3I, and Multi-function 1 interrupt enable bit, EMF1I, must first be set. An actual interrupt will take place when the Timer/Event Counter 2 or Timer/Event counter 3 request flag, T2F or T3F, is set, a situation that will occur when the Timer/Event Counter 2 or Timer/Event counter 3 overflows. When the interrupt is enabled, the stack is not full and the Timer/Event Counter 2 or Timer/Event counter 3 overflows, a subroutine call to the Multi-function interrupt vector at location 28H, will take place. When the Timer/Event 2 or Timer/Event counter 3 interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the Multi-function interrupt request flag will be reset. As the T2F or T3F flag will not be automatically reset, it has to be cleared by the application program. Rev. 1.00 87 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces A/D Interrupt For an A/D Interrupt to be generated, the global interrupt enable bit EMI and the A/D Interrupt enable bit EADI must first be set. An actual A/D Interrupt will take place when the A/D Interrupt request flag, ADF, is set, a situation that will occur when the A/D conversion process has finished. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D interrupt vector at location 20H, will take place. When the A/D Interrupt is serviced, the A/D interrupt request flag ADF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Smart Card Interrupt For a Smart Card Interrupt to be generated, the global interrupt enable bit EMI must first be set as well as one of the associated Smart Card event Interrupt enable bits. The Smart Card events that will generate an interrupt include situations such as a Card voltage error, a Card current overload, a waiting timer overflow, a parity error, a transmit buffer empty or an end of transmission or reception. Once one of the associated Smart Card event interrupt enable control bits is set, it will automatically set the CRDE bit to 1 to enable the related Smart Card interrupt. An actual Smart Card Interrupt will take place when the Smart Card Interrupt request flag, CRDF, is set, a situation that will occur when a Smart Card event has occurred. When the interrupt is enabled, the stack is not full and a Smart Card event has occurred, a subroutine call to the Smart Card interrupt vector at location 04H, will take place. When the Smart Card Interrupt is serviced, the Smart Card interrupt request flag CRDF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Smart Card Insertion/Removal Interrupt For a Smart Card Insertion/Removal Interrupt to be generated, the global interrupt enable bit EMI and the Smart Card Insertion/Removal interrupt enable bit CIRE must first be set. An actual Smart Card Insertion/Removal Interrupt will take place when the Smart Card Insertion/Removal Interrupt request flag, SCIRF, is set, a situation that will occur when the Smart Card has been inserted or removed. When the interrupt is enabled, the stack is not full and the Smart Card has been inserted or removed, a subroutine call to the Smart Card Insertion/Removal Interrupt vector at location 1CH, will take place. When the Smart Card Insertion/Removal Interrupt is serviced, the Smart Card Insertion/Removal interrupt request flag SCIRF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. SIM (SPI/I2C Interface) Interrupts The two SIM (SPI/I2C ) interrupts named SIM0 interrupt and SIM1 interrupt are contained within the Multi-function 0 Interrupt and Multi-function 1 Interrupt respectively. For an SIM (SPI/I2C interface) interrupt to occur, the global interrupt enable bit named EMI, the associated SIM interrupt enable control bit named ESIM0 or ESIM1 and the Multi-function interrupt enable bit named EMF0I or EMF1I must be first set. An actual SIM (SPI/I2C interface) interrupt will take place when the SIM (SPI/I2C interface) request flag, SIM0F or SIM1F, is set, a situation that will occur when a byte of data has been transmitted or received by the SPI/I2C interface or when an I2C address match occurs. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPI/I2C interface or an I2C address match occurs, a subroutine call to the SIM (SPI/I2C interface) interrupt vector at location 24H or 28H respectively, will take place. When SIM the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the MF0F or MF1F interrupt request flag will be reset. As the SIM request flag known as SIM0F or SIM1F will not be automatically reset, it has to be cleared by the application program. Rev. 1.00 88 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Multi-function Interrupt Two additional interrupts known as the Multi-function 0 interrupt and Multi-function 1 interrupt are provided. Unlike the other interrupts, the interrupt has no independent source, but rather is formed from several other existing interrupt sources. The Multi-function 0 interrupt contains the SIM0 interrupt, Time Base interrupt, Real Time Clock interrupt, External Peripheral interrupt while the Multi-function 1 interrupt contains the SIM1 interrupt, Timer 2 overflow interrupt and Timer 3 overflow interrupt. For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the Multi-function interrupt enable bit, EMF0I or EMF1I, must first be set. An actual Multi-function interrupt will take place when the Multi-function interrupt request flag, MF0F or MF1F, is set. This will occur when either a Time Base overflow, a Real Time Clock overflow, SIM0 or SIM 1 interrupt, an External Peripheral Interrupt, Timer 2 overflow interrupt or Timer 3 overflow interrupt is generated. When the interrupt is enabled and the stack is not full, and either one of the interrupts contained within the Multi-function interrupts occurs, a subroutine call to the Multi-function interrupt vector at location 24H or 28H respectively will take place. When the interrupt is serviced, the Multi-Function request flag, MF0F or MF1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that the request flags from the original source of the Multi-function interrupt, namely the Time-Base interrupt, Real Time Clock interrupt, SIM interrupts, External Peripheral interrupt, Timer 2 overflow interrupt or Timer 3 overflow interrupt will not be automatically reset and must be manually reset by the application program. Real Time Clock Interrupt The Real Time Clock Interrupt is contained within the Multi-function 0 Interrupt. For a Real Time Clock interrupt to be generated, the global interrupt enable bit, EMI, Real Time Clock interrupt enable bit, ERTI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An actual Real Time Clock interrupt will take place when the Real Time Clock request flag, RTF, is set, a situation that will occur when the Real Time Clock overflows. When the interrupt is enabled, the stack is not full and the Real Time Clock overflows, a subroutine call to the Multi-function 0 interrupt vector at location 24H, will take place. When the Real Time Clock interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MF0F interrupt request flag will be reset. As the RTF flag will not be automatically reset, it has to be cleared by the application program. Similar in operation to the Time Base interrupt, the purpose of the RTC interrupt is also to provide an interrupt signal at fixed time periods. The RTC interrupt clock source originates from the internal clock source fS. This fS input clock first passes through a divider, the division ratio of which is selected by programming the appropriate bits in the RTCC register to obtain longer RTC interrupt periods whose value ranges from 28/fS~215/fS. The clock source that generates fS, which in turn controls the RTC interrupt period, can originate from three different sources, the 32.768kHz oscillator (LXT), the internal 32kHz RC oscillator (LIRC) or the System oscillator divided by 4 (fSYS/4), the choice of which is determine by the fS clock source configuration option. Rev. 1.00 89 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces RTC Interrupt Note that the RTC interrupt period is controlled by both configuration options and an internal register RTCC. A configuration option selects the source clock for the internal clock fS, and the RTCC register bits RT2, RT1 and RT0 select the division ratio. Note that the actual division ratio can be programmed from 28 to 215. RTCC Register Bit 7 6 5 4 3 Name — — LVDO QOSC LVDC RT2 RT1 RT0 R/W — — R R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 2 1 0 Unimplemented, read as ″0″ Bit 5LVDO: Low Voltage Detector Output 0: Normal voltage 1: Low voltage detected Bit 4QOSC: RTC Oscillator Quick-start enable control 0: Enable 1: Disable Bit 3LVDC: Low Voltage Detector enable control 0: Disable 1: Enable Bit 2~0RT2~RT0: RTC Interrupt Period selection 000: 28/fS 001: 29/fS 010: 210/fS 011: 211/fS 100: 212/fS 101: 213/fS 110: 214/fS 111: 215/fS Rev. 1.00 90 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Time Base Interrupt The Time Base Interrupt is contained within the Multi-function 0 Interrupt. For a Time Base Interrupt to be generated, the global interrupt enable bit, EMI, Time Base Interrupt enable bit, ETBI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An actual Time Base Interrupt will take place when the Time Base Interrupt request flag, TBF, is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to the Multi-function 0 interrupt vector at location 24H, will take place. When the Time Base Interrupt is serviced, the EMI bit will be cleared to disable other interrupts, however only the MF0F interrupt request flag will be reset. As the TBF flag will not be automatically reset, it has to be cleared by the application program. The purpose of the Time Base function is to provide an interrupt signal at fixed time periods. The Time Base interrupt clock source originates from the Time Base interrupt clock source originates from the internal clock source fS. This fS input clock first passes through a divider, the division ratio of which is selected by configuration options to provide longer Time Base interrupt periods. The Time Base interrupt time-out period ranges from 212/fS~215/fS. The clock source that generates fS, which in turn controls the Time Base interrupt period, can originate from three different sources, the 32.768kHz oscillator (LXT), the internal 32kHz RC oscillator (LIRC) or the System oscillator divided by 4 (fSYS/4), the choice of which is determine by the fS clock source configuration option. Essentially operating as a programmable timer, when the Time Base overflows it will set a Time Base interrupt flag which will in turn generate an Interrupt request via the Multi-function 0 Interrupt vector. Time Base Interrupt Rev. 1.00 91 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC0, INTC1, INTC2, MFIC0 and MFIC1 registers until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the ″CALL″ instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the micro controller then its respective request flag should be first set high before entering the SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a ″RET″ or ″RETI″ instruction may be executed. The ″RETI″ instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The ″RET″ instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 92 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: • Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. Rev. 1.00 93 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Power-On Reset Timing Chart More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Note: "*" It is recommended that this component is added for added ESD protection "**" It is recommended that this component is added in environments where power line noise is significant External RES Circuit • RES Pin Reset This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point. RES Reset Timing Chart • Low Voltage Reset − LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function. One of a range of specified voltage values for VLVR can be selected using configuration options. The VLVR value will be selected as a pair in conjunction with a Low Voltage Detect value. Low Voltage Reset Timing Chart Rev. 1.00 94 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces • Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to ″1″. WDT Time-out Reset during Normal Operation Timing Chart • Watchdog Time-out Reset during Power Down The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to ″0″ and the TO flag will be set to ″1″. Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during Power Down Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 RES reset during power-on RESET Conditions u u RES or LVR reset during normal operation 1 u WDT time-out reset during normal operation 1 1 WDT time-out reset during Power Down Note: ″u″ stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Prescaler The Timer Counter Prescaler will be cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Rev. 1.00 95 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Reset (Power-On) RES Reset (Normal Oper.) WDT Time-out (Normal Oper.) WDT Time-out (HALT)* MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu BP --0- 0000 --0- 0000 --0- 0000 --u- uuuu Register ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP --xx xxxx --uu uuuu --uu uuuu --uu uuuu RTCC - - 0 0 0 111 - - 0 0 0 111 - - 0 0 0 111 --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu - - 11 u u u u MISC0 0000 0000 0000 0000 0000 0000 uuuu uuuu MISC1 0000 1010 0000 1010 0000 1010 uuuu uuuu CLKMOD 0 0 0 0 0 111 0 0 0 0 0 111 0 0 0 0 0 111 uuuu uuuu DC2DC ---- --00 ---- --00 ---- --00 ---- --uu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 -000 -000 -000 -000 -000 -000 -uuu -uuu MFIC0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFIC1 -000 -000 -000 -000 -000 -000 -uuu -uuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU -000 0000 -000 0000 -000 0000 -uuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 uuuu uuuu UCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TXR_RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM0L 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM0H 0000 0000 0000 0000 0000 0000 uuuu uuuu PWM1L 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM1H 0000 0000 0000 0000 0000 0000 uuuu uuuu PWM2L 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM2H 0000 0000 0000 0000 0000 0000 uuuu uuuu PWM3L 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM3H 0000 0000 0000 0000 0000 0000 uuuu uuuu TMR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- uuuu u--- Rev. 1.00 96 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Reset (Power-On) RES Reset (Normal Oper.) WDT Time-out (Normal Oper.) WDT Time-out (HALT)* TMR2 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR2C 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR3 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Register TMR3C 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu RCFLT --00 0000 --00 0000 --00 0000 --uu uuuu ADRL xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 01-- -000 01-- -000 01-- -000 uu-- -uuu ACSR 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 uuuu uuuu ADPCR 0000 0000 0000 0000 0000 0000 uuuu uuuu SIM0CTL0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu- SIM0CTL1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIM0DR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIM0AR/SIM0CTL2 0000 0000 0000 0000 0000 0000 uuuu uuuu SIM1CTL0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu- SIM1CTL1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIM1DR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIM1AR/SIM1CTL2 0000 0000 0000 0000 0000 0000 uuuu uuuu DAL xxxx ---- xxxx ---- xxxx ---- xxxx ---- DAH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx DACTRL xxx- ---0 xxx- ---0 xxx- ---0 uuu- ---u CCR 0000 0000 0000 0000 0000 0000 uuuu uuuu CSR 1000 0000 1000 0000 1000 0000 uuuu uuuu CCCR 00xx x0x0 00xx x0x0 00xx x0x0 uuxx xuxu CETU1 0--- -001 0--- -001 0--- -001 u--- -uuu CETU0 0 111 0 1 0 0 0 111 0 1 0 0 0 111 0 1 0 0 uuu uuuuu CGT1 ---- ---0 ---- ---0 ---- ---0 ---- ---u CGT0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 uuuu uuuu CWT2 0000 0000 0000 0000 0000 0000 uuuu uuuu CWT1 0010 0101 0010 0101 0010 0101 uuuu uuuu CWT0 1000 0000 1000 0000 1000 0000 uuuu uuuu CIER 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu CIPR 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu CTXB 0000 0000 0000 0000 0000 0000 uuuu uuuu CRXB 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ″u″ stands for unchanged ″x″ stands for unknown ″−″ stands for unimplemented Rev. 1.00 97 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. Five types of system clocks can be selected while various clock source options are provided for maximum flexibility. All oscillator options are selected through the configuration options. System Clock Configurations There are many ways of generating the system clock, three high speed oscillators and two low speed oscillators supplied clock. An external clock source can also be used as the system clock. The three high speed oscillators are the external crystal/ceramic oscillator (HXT), the external RC network (ERC) and the internal high speed RC oscillator (HIRC). The two low speed oscillators are the external 32.768kHz crystal oscillator (LXT) and the internal 32kHz RC oscillator (LIRC). Selecting whether the low frequency or high oscillator is used as the system oscillator is implemented using the HLCLK bit in the CLKMOD register. The source clock for the high speed oscillator is chosen via configuration options as well as the low speed oscillator. The frequency of the slow clock is also determined using the SLOWC0~SLOWC2 bits in the CLKMOD register. External Crystal/ Ceramic Oscillator − HXT After selecting the external crystal configuration option, the simple connection of a crystal across OSC1 and OSC2, is normally all that is required to create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer′s specification. In most applications, resistor R P1 is not required, however for those applications where the LVR function is not used, RP1 may be necessary to ensure the oscillator stops running when VDD falls below its operating range. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. An additional configuration option must be setup to configure the device according to whether the oscillator frequency is high, defined as equal to or above 1MHz, or low, which is defined as below 1MHz. More information regarding oscillator applications is located on the Holtek website. Crystal/Ceramic Oscillator Rev. 1.00 98 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 20MHz — — 12MHz — — 8MHz — — 4MHz — — 1MHz — — 455kHz (see Note 2) 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. XTAL mode configuration option: 455kHz. 3. RP1=5MΩ~10MΩ is recommended. Crystal Recommended Capacitor Values External RC Oscillator − ERC Using the ERC oscillator only requires that a resistor, with a value between 47kΩ and 1.5MΩ, is connected between OSC1 and VDD, and a 470pF capacitor is connected between OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 150kΩ resistor connected and with a 5V voltage power supply and temperature of 25°C degrees, the oscillator will have a frequency of 4MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O pin PA2, leaving pin PA3 free for use as a normal I/O pin. Note that an internal capacitor together with the external resistor, ROSC, are the components which determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation. This external capacitor should be added to improve oscillator stability if the open-drain OSC2 output is utilised in the application circuit. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pins. External RC Oscillator – ERC Rev. 1.00 99 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Internal High Speed RC Oscillator − HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PA2 and PA3 are free for use as normal I/O pins. Internal Low Speed Oscillator − LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the oscillation frequency of 32kHz will have a frequency range from 28.1kHz to 34.4kHz. Internal RC Oscillator – LIRC External 32.768kHz Oscillator − LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers′ specification. The external parallel feedback resistor, Rp, is required. Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. Rev. 1.00 100 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces LXT Oscillator C1 and C2 Values Crystal Frequency C3 C4 32768Hz 8pF 10pF Note: 1. C3 and C4 values are for guidance only. 2. RP2=5M~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values Crystal/Ceramic Oscillator LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the QOSC bit in the RTCC register. QOSC Bit LXT Mode 0 Quick Start 1 Low-power After power on, the QOSC bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the QOSC bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the QOSC bit high about 2 seconds after power-on. It should be noted that, no matter what condition the QOSC bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Lowpower mode. External Oscillator − EC The system clock can also be supplied by an externally supplied clock giving users a method of synchronizing their external hardware to the microcontroller operation. This is selected using a configuration option and supplying the clock on pin OSC1. Pin OSC2 can be used as a normal I/O pin if the external oscillator is used. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin. However, as the filter circuit consumes a certain amount of power, an oscillator configuration option exists to turn this filter off. Not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Rev. 1.00 101 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces System Operating Modes The device has the ability to operate in several different modes. This range of operating modes, known as Normal Mode, Slow Mode, Idle Mode and Sleep Mode, allow the device to run using a wide range of different slow and fast clock sources. The devices also possess the ability to dynamically switch between different clocks and operating modes. With this choice of operating functions users are provided with the flexibility to ensure they obtain optimal performance from the device according to their application specific requirements. Clock Sources In discussing the system clocks for the device, they can be seen as having a dual clock mode. These dual clocks are what are known as a High Oscillator and the other as a Low Oscillator. The High and Low Oscillator are the system clock sources and can be selected dynamically using the HLCLK bit in the CLKMOD register. The High Oscillator has the internal name fM whose source is selected using a configuration option from a choice of either an external crystal/resonator, external RC oscillator or external clock source. CLKMOD Register Bit Name 7 6 5 4 SLOWC2 SLOWC1 SLOWC0 SIMIDLE 3 2 1 0 LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 1 1 1 Bit 7~5SLOWC2~SLOWC0: Low speed clock frequency fSLOW selection 000: fSL 001: fSL 010: fM/64 011: fM/32 100: fM/16 101: fM/8 110: fM/4 111: fM/2 Bit 4SIMIDLE: SIMn (SPI/I2C) Continues Running in IDLE mode control 0: Disable 1: Enable Bit 3LTO: Low speed Oscillator ready flag 0: Not ready 1: Ready Bit 2HTO: High speed Oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. Bit 1IDLEN: Idle mode control 0: Disable (SLEEP mode) 1: Enable (IDLE mode) Bit 0HLCLK: System clock frequency fSYS selection 0: fM 1: fSLOW Rev. 1.00 102 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces The Low Oscillator clock source has the internal name fSL, whose source is also selected by configuration option from a choice of either an external 32.768kHz oscillator (LXT) or the internal 32kHz RC oscillator (LIRC). This internal fSL, fM clock, is further modified by the SLOWC0~ SLOWC2 bits in the CLKMOD register to provide the low frequency clock source fSLOW. An additional sub internal clock, with the internal name fSUB, is a 32kHz clock source which can be sourced from either the internal 32K_INT oscillator or an external 32768 Hz crystal, selected by configuration option. Together with fSYS/4, it is used as a clock source for certain internal functions such as the LCD driver, Watchdog Timer, Buzzer, RTC Interrupt and Time Base Interrupt. The LCD clock source is the fSUB clock source divided by 8, giving a frequency of 4kHz. The internal clock fS, is simply a choice of either fSUB or fSYS/4, using a configuration option. Dual Clock Mode Operation Rev. 1.00 103 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Dual Clock Mode Structure Rev. 1.00 104 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Operating Modes After the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the CLKMOD register. A combination of the HLCLK and IDLEN bits in the CLKMOD register and use of the HALT instruction determine in which mode the device will be run. The devices can operate in the following Modes. Normal mode fM on, fSLOW on, fSYS=fM, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. Slow Mode0 fM off, fSYS=fSLOW, fSLOW=fSL=fLIRC or fLXT, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. Slow Mode1 fM on, fSYS=fSLOW=fM/2~fM/64, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. IDLE mode fM, fSLOW, fSYS off, CPU off; fSUB on, fS on/off by selecting fSUB or fSYS /4, fWDT on/off depending upon the WDT configuration option and WDT control register. The IDLE mode is determined by the IDLE Mode Control bit named IDLEN in the CLKMOD register when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. SLEEP mode fM, fSLOW, fSYS, fS, CPU off; fSUB, fWDT on/off depending upon the WDT configuration option and WDT control register. The SLEEP mode is determined by setting the IDLE Mode Control bit named IDLEN to 0 when the HALT instruction is executed. Operation Mode Description CPU fSYS fSUB fS Normal Mode On fM On On Slow 0 Mode On fSLOW=fLIRC or fLXT On On Slow 1 Mode On fSLOW=fM/2~fM/64 On On IDLE Mode On On/Off (1) On On/Off (3) SLEEP Mode On Off On/Off (2) On/Off (3) Note: 1. In the IDLE Mode, the fSYS clock on/off function is determined by whether the SIMIDLE bit set to 1 or 0 respectively and can only be used for the master SPI operation or PCLK output for which the clock source comes from the fSYS clock. 2. In the SLEEP mode the fSUB clock on/off function is determined by whether the WDT is enabled or disabled respectively. 3. The fS clock on/off function in the IDLE or SLEEP mode is determined by whether the selected clock source of the WDT function is fSUB or the fSYS/4 clock. Rev. 1.00 105 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Power Down Mode and Wake-up Power Down Mode All of the Holtek microcontroller have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the ″HALT″ instruction in the application program. When this instruction is executed, the following will occur: • The system oscillator will stop running and the application program will stop at the ″HALT″ instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock. • The I/O ports will maintain their present condition. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator. Rev. 1.00 106 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the ″HALT″ instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ″HALT″ instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the ″HALT″ instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to ″1″ before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the ″HALT″ instruction, this will be executed immediately after the 1024 system clock period delay has ended. Rev. 1.00 107 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Low Voltage Detector − LVD The Low Voltage Detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the DC characteristics. LVD Operation The LVD function must be first enabled via a configuration option after which bits 3 and 5 of the RTCC register are used to control the overall function of the LVD. Bit 3 is the enable/disable control bit and is known as LVDC, when set low the overall function of the LVD will be disabled. Bit 5 is the LVD detector output bit and is known as LVDO. Under normal operation, and when the power supply voltage is above the specified VLVD value in the DC characteristic section, the LVDO bit will remain at a zero value. If the power supply voltage should fall below this VLVD value then the LVDO bit will change to a high value indicating a low voltage condition. Note that the LVDO bit is a read-only bit. By polling the LVDO bit in the RTCC register, the application program can therefore determine the presence of a low voltage condition. After power-on, or after a reset, the LVD will be switched off by clearing the LVDC bit in the RTCC register to zero. Note that if the LVD is enabled there will be some power consumption associated with its internal circuitry, however, by clearing the LVDC bit to zero the power can be minimised. It is important not to confuse the LVD with the LVR function. In the LVR function an automatic reset will be generated by the , whereas in the LVD function only the LVDO bit will be affected with no influence on other functions. There are a range of voltage values, selected using a configuration option, which can be chosen to activate the LVD. Rev. 1.00 108 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the Watchdog Timer counter overflows. Watchdog Timer Operation The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. Note that if the Watchdog Timer configuration option has been disabled, then any instruction relating to its operation will result in no operation. Most of the Watchdog Timer options, such as enable/disable, Watchdog Timer clock source and clear instruction type are selected using configuration options. In addition to a configuration option to enable the Watchdog Timer, there are four bits, WDTEN3~ WDTEN0, in the MISC1 register to offer an additional enable control of the Watchdog Timer. These bits must be set to a specific value of 1010 to disable the Watchdog Timer. Any other values for these bits will keep the Watchdog Timer enabled. After power on these bits will have the disabled value of 1010. One of the WDT clock sources is the internal fSUB, which can be sourced from either the internal 32kHz RC oscillator (LIRC) or the external 32.768kHz oscillator (LXT). The LIRC oscillator has an approximate period of 31.2ms at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32768Hz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. Whether the Watchdog Timer clock source is it′s the LIRC, the LXT oscillator or fSYS/4, it is divided by 213~216, using configuration option to obtain the required Watchdog Timer time-out period. The max time out period is when the 216 option is selected. This time-out period may vary with temperature, VDD and process variations. As the clear instruction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog Timer counter before the clear instruction is executed. Watchdog Timer Rev. 1.00 109 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces MISC1 Register Bit 7 6 5 4 Name ODE3 ODE2 ODE1 ODE0 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 1 0 1 0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Bit 7~4ODE3~ODE0: PA3~PA0 Open Drain control Described in Input/Output Port section Bit 3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable 1010: WDT disabled Other values: WDT enabled Recommended value is ″0101″ If the ″watchdog timer enable″ configuration option is selected, then the watchdog timer will al ways be enabled and the WDTEN3~WDTEN0 control bits will have no effect. The WDT is only disabled when both the WDT configuration option is disabled and when bits WDTEN3~WDTEN0=1010. The WDT is enabled when either the WDT configuration option is enabled or when bits WDTEN3~WDTEN0≠1010 If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the Power Down Mode, then the instruction clock is stopped and the Watchdog Timer will lose its protecting purposes. For systems that operate in noisy environments, using the LIRC oscillator is strongly recommended. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a ″HALT″ instruction. Clearing the Watchdog Timer There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single ″CLR WDT″ instruction while the second is to use the two commands ″CLR WDT1″ and ″CLR WDT2″. For the first option, a simple execution of ″CLR WDT″ will clear the WDT while for the second option, both ″CLR WDT1″ and ″CLR WDT2″ must both be executed to successfully clear the Watchdog Timer. Note that for this second option, if ″CLR WDT1″ is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a ″CLR WDT2″ instruction will clear the Watchdog Timer. Similarly after the ″CLR WDT2″ instruction has been executed, only a successive ″CLR WDT1″ instruction can clear the Watchdog Timer. Rev. 1.00 110 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces UART Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Separately enabled transmitter and receiver • 2-byte Deep FIFO Receive Data Buffer • Transmit and receive interrupts • Interrupts can be initialized by the following conditions: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect T r a n s m itte r S h ift R e g is te r M S B R e c e iv e r S h ift R e g is te r T X P in L S B R X P in C L K M S B L S B C L K T X R R e g is te r B a u d R a te G e n e ra to r M C U R X R R e g is te r B u ffe r D a ta B u s UART Data Transfer Scheme Rev. 1.00 111 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces UART External Interface To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O or other pin-shared functional pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins or other pinshared functional to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. UART Data Transfer Scheme The block diagram shows the overall data transfer structure arrangement for the UART interface. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR_ RXR data registers. TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bits Rev. 1.00 112 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only and further explanations are given below: Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a parity error has not been detected. When the flag is “1”, it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is “0”, it indicates no noise condition. When the flag is “1”, it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is “0”, it indicates that there is no framing error. When the flag is “1”, it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is “0”, it indicates that there is no overrun error. When the flag is “1”, it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1” indicating that the UART receiver is idle and the RX pin stays in logic high condition. Rev. 1.00 113 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is “0”, it indicates that the RXR read data register is empty. When the flag is “1”, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission status 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1” when the TXIF flag is “1” and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is “0”, it indicates that the character is not transferred to the transmitter shift register. When the flag is “1”, it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. Rev. 1.00 114 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces UCR1 Register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 “x”: unknown Bit 7UARTEN: UART function enable control 0: Disable UART. TX and RX pins are I/O or other pin-shared functions 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART will be disabled and the RX pin as well as the TX pin will be set as I/O or other pin-shared functions. When the bit is equal to “1”, the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This bit is the parity function enable bit. When this bit is equal to 1, the parity function will be enabled. If the bit is equal to 0, then the parity function will be disabled. Bit 4PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will be selected. If the bit is equal to 0, then even parity type will be selected. Bit 3STOPS: Number of stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to “1”, two stop bits format are used. If the bit is equal to “0”, then only one stop bit format is used. Rev. 1.00 115 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 2TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is equal to “0”, there are no break characters and the TX pin operats normally. When the bit is equal to “1”, there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to “1”, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TXEN: UART Transmitter enable control 0: UART Transmitter is disabled 1: UART Transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to “1” and the UARTEN bit is also equal to 1, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be used as an I/O or other pin-shared functional pin. Bit 6RXEN: UART Receiver enable control 0: UART Receiver is disabled 1: UART Receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to “0”, the receiver will be disabled with any pending data receptions being aborted. In addition the receiver buffers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to “1” and the UARTEN bit is also equal to 1, the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be used as an I/O or other pin-shared functional pin. Rev. 1.00 116 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register, BRG, controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of “1”, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th bit of the received word is “0” with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and the device is in IDLE or SLEEP mode, a falling edge on the RX pin will wake up the device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the receiver overrun flag OERR or received data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the TXIF flag. Rev. 1.00 117 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS/[64(N+1)] fSYS/[16(N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown Bit 7~0BRG7~BRG0: Baud Rate values By programming the BRGH bit in the UCR2 register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Rev. 1.00 118 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. fSYS From the above table the desired baud rate BR = [64(N+1)] fSYS Re-arranging this equation gives N = −1 BR×64 Giving a value for N = 4000000 4800×64 −1 = 12.0208 To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR = 4000000 = 4808 64(12+1) 4808−4800 = 0.16% 4800 The following tables show the actual values of baud rate and error values for the two value of BRGH. Therefore the error is equal to Baud Rate K/bps Baud Rates for BRGH=0 fSYS=4MHz BRG fSYS=3.579545MHz Kbaud Error(%) BRG Kbaud Error(%) fSYS=7.159MHz BRG Kbaud Error(%) 0.3 207 0.300 0.16 185 0.300 0.00 — — — 1.2 51 1.202 0.16 46 1.190 -0.83 92 1.203 0.23 2.4 25 2.404 0.16 22 2.432 1.32 46 2.380 -0.83 4.8 12 4.808 0.16 11 4.661 -2.90 22 4.863 1.32 9.6 6 8.929 -6.99 5 9.321 -2.90 11 9.322 -2.90 19.2 2 20.833 8.51 2 18.643 -2.90 5 18.643 -2.90 38.4 — — — — — — 2 32.286 -2.90 57.6 0 62.500 8.51 0 55.930 -2.90 1 55.930 -2.90 115.2 — — — — — — 0 111.859 -2.90 Baud Rates and Error Values for BRGH=0 Baud Rate K/bps Baud Rates for BRGH=1 fSYS=4MHz BRG fSYS=3.579545MHz Kbaud Error(%) BRG Kbaud Error(%) fSYS=7.159MHz BRG Kbaud Error(%) 0.3 — — — — — — — — 1.2 207 1.202 0.16 185 1.203 0.23 — — — — 2.4 103 2.404 0.16 92 2.406 0.23 185 2.406 0.23 4.8 51 4.808 0.16 46 4.76 -0.83 92 4.811 0.23 9.6 25 9.615 0.16 22 9.727 1.32 46 9.520 -0.83 19.2 12 19.231 0.16 11 18.643 -2.90 22 19.454 1.32 38.4 6 35.714 -6.99 5 37.286 -2.90 11 37.286 -2.90 57.6 3 62.5 8.51 3 55.930 -2.90 7 55.930 -2.90 115.2 1 125 8.51 1 111.86 -2.90 3 111.86 -2.90 250 0 250 0 — — — — — — Baud Rates and Error Values for BRGH=1 Rev. 1.00 119 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity is supported by the UART hardware and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be used as an I/O or other pin-shared functional pin. When the UART function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Rev. 1.00 120 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address detect mode control bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. 8-Bit Data Format 9-Bit Data Format UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O or other pin-shared function. Rev. 1.00 121 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: • A USR register access • A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: • A USR register access • A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN “0” bits, where N=1, 2, etc. if a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. Rev. 1.00 122 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a two bytes deep FIFO data buffer, where two bytes can be held in the FIFO while the third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise the third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: • The RXIF bit in the USR register will be set then RXR register has data available, at least three more character can be read. • When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. • If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: • A USR register access • A RXR register read execution Rev. 1.00 123 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Receiving Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Rev. 1.00 124 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The RXR register is composed of a two bytes deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before the third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Noise Error – NF Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame, the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared in any reset. Parity Error – PERR The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. Rev. 1.00 125 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. UART Interrupt Scheme Rev. 1.00 126 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. ADDEN 0 1 Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function UART Power Down Mode and Wake-up When the MCU is in the Power Down Mode, the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be paused. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the Power Down mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake up the MCU from the Power Down Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Rev. 1.00 127 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Digital to Analog Converter − DAC The device includes a 12-bit Digital to Analog Converter function. This function allows digital data contained in the device to generate audio signals. Operation The data to be converted is stored in two registers DAL and DAH. The DAH register stores the highest 8-bits, DA11~DA4, while DAL stores the lowest 4-bits, DA3~DA0. An additional control register, DACTRL, provides overall DAC on/off control in addition to a 3-bit 8-level volume control. The DAC output is channeled to pin AUD which is pin-shared with I/O pin PC0. When the DAC is enabled by setting the DACEN bit high, then the original I/O function will be disabled, along with any pull-high resistor options. The DAC output reference voltage is the power supply voltage VDD. DAH Register Bit 7 6 5 4 3 2 1 0 Name DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0DA11~DA4: Audio Output DAC high byte data. DAL Register Bit 7 6 5 4 3 2 1 0 Name DA3 DA2 DA1 DA0 — — — — R/W R/W R/W R/W R/W — — — — POR 0 0 0 0 — — — — Bit 7~4DA3~DA0: Audio Output DAC low byte data. Bit 3~0 Unimplemented, read as ″0″ DACTRL Register Bit 7 6 5 4 3 2 1 0 Name VOL2 VOL1 VOL0 — — — — DACEN R/W R/W R/W R/W — — — — R/W POR 0 0 0 — — — — 0 Bit 7~5VOL2~VOL0: Audio Output Volume control. The audio output is at maximum volume if these bits are set to 111B while the audio output is at minimum volume if these bits are set to 000B. Bit 4~1 Unimplemented, read as ″0″ Bit 0DACEN: DAC enable Control 0: DAC is disabled 1: DAC is enabled Rev. 1.00 128 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces DC/DC Converter and LDO The device contains a DC/DC Converter and an LDO to provide the power supply for the Smart Card interface pins and the external Smart Card. The DC/DC Converter is a PFM step-up DC/DC converter with high efficiency and low ripple. It requires only three external components to provide an output voltage of either 3.8V or 5.5V selected by the DC/DC output voltage selection bit VSEL in the DC2DC register. The DC/DC voltage output is connected to an external pin, VO, and then must externally be connected to the LDO input, LDOIN. It also contains an enable control bit, DCEN, in the DC2DC register to reduce power consumption when in the power down mode. If the Smart Card voltage output is switched to 0V by clearing the selection bits VC [1:0] in the CCR register, the DC/DC converter will automatically be turned off even if the enable control bit DCEN is set to 1. The LDO is a three-terminal high current low voltage dropout regulator with over current protection. It supports three output voltages of 1.8V, 3.0V or 5.0V selected by the Smart Card Voltage selection bits VC1 and VC0 in the CCR register. It can deliver a maximum output current of 35mA, 55mA and 60mA when the LDO output voltage is 1.8V, 3.0V and 5.0V respectively. 100uH/2Ω BEAD 22uF VDD SELF 10pF VO LDOVSS LDOIN CRDVCC DC/DC Converter CVSS DCEN LDO VSEL 4.7uF VC1 VC0 VSS CRST Smart Card Interface pins CC8 VDD CDET DC/DC Converter Block Diagram DC2DC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — DCEN VSEL R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as ″0″ Bit 1DCEN: DC/DC enable control 0: DC/DC converter disabled 1: DC/DC converter enabled This bit is used to control the DC/DC converter function. If this bit is set to ″1″, the DC/DC output voltage is selected by the VSEL selection bit. If this bit is cleared to 0, the DC/DC converter function is disabled and the output voltage is equal to the value of (VDD− VDIODE). Bit 0VSEL: DC/DC output voltage selection 0: DC/DC output voltage is 3.8V 1: DC/DC output voltage is 5.5V Rev. 1.00 129 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Smart Card Interface The device contains a Smart Card Interface compatible with the ISO 7816-3 standard. This interface includes the Card Insertion/Removal detection, UART interface control logic and data buffers, Power control circuits, internal Timer Counters and control logic circuits to perform the required Smart Card operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication with the external Smart Card. The overall functions of the Smart Card interface is control by a series of registers including control and status registers. As the complexity of ISO7816-3 standard data protocol does not permit comprehensive specifications to be provided in this datasheet, the reader should therefore consult other external information for a detailed understanding of this standard. fCCLK S�CEN Elementa�y Time Unit (ETU) fETU Gua�d Time Counte� (GTC) Powe� Cont�ol Waiting Time Counte� (WTC) Clo�k Cont�ol CRDVCC CRST fETU UART TX/RX buffe�s fGTC fWTC Cont�ol Registe�s UART �ont�ol �i��uits CCLK CRDVCC CIO I/O Cont�ol CC� Inte��upt Registe�s CC8 VDD Ca�d Dete�tion Inte��upt to �CU CDET Interface Pins To communicate with an external Smart Card, the internal Smart Card interface has a series of external pins known as CRDVCC, CRST, CCLK, CIO, CC4, CC8 and CDET. The CRDVCC pin is the power supply pin of of the external Smart Card and the Smart Card interface pins described above except the CDET pin. It can output several voltage levels as selected by the VC1 and VC0 selection bits. The CRST pin is the reset output signal which is used to reset the external Smart Card. Together with the internal CRST control bit the MCU can control the CRST pin level by writing specific data to the CRST bit and obtain the CRST pin status by reading the CRST bit. The CCLK pin is the clock output signal used to communicate with the external Smart Card together with the serial data pin, CIO. The operation of CCLK and CIO can be selected as the UART mode automatically driven by the UART control circuits, or the Manual mode controlled by configuring the internal CCLK and CIO bits respectively by the application program. The CDET pin is the external Smart Card detection input pin. When the external Smart Card is inserted or removed, it can be detected and generate an interrupt signal which is sent to MCU if the corresponding interrupt control bit is enabled. The CC4 and CC8 pins are used as I/O pins and are controlled by the corresponding CC4 and CC8 bits. Rev. 1.00 130 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Card Detection If an external Smart Card is inserted, the internal card detector can detect this insertion operation and generate a Card insertion interrupt. When the Card is present and detected, the power-on sequence for the external Smart Card should be activated by the application programs to supply power for the external Smart Card. Similarly if the Card is removed, the internal card detector can also detect the removal and consequently generate a Card removal interrupt. Like the Card insertion operation, the Card Removal deactivation procedure defined in the ISO 7816-3 standard should be activated by the application programs. The card detector can support two kinds of card detect switch mechanisms. One is a normally open switch mechanism when the card is not present and the other is a normally closed switch mechanism. After noting which card detect switch mechanism type is used, the card switch selection should be configured by setting the selection bit CDET in the CCR Register to correctly detect the Card presence. No matter what type of the card switch is selected by configuring the CDET bit, the Card Insertion/Removal Flag, CIRF, in the CSR register will be set to ″1″ when the card is actually present on the CDET pin, and clear to "0" by the application program. Note that there is no hardware de-bounce circuits in the card detector. Any change of the CDET pin level will cause the CIRF bit to change. The required de-bounce time should be handled by the application program. There is a pull high resistor integrated in the card detector. A configuration option can determine whether the pull high resistor is internally connected to the CDET pin. Internal Time Counter − ETU, GTC, WTC For proper data transfer, some timing purposed setting procedures must be executed before the Smart Card Interface can begin to communicate with the external card. There are three internal counters named Elementary Time Unit (ETU), Guard Time Counter (GTC) and Waiting Time Counter (WTC) which are used for the timing related functions in the Smart Card interface operation. Elementary Time Unit − ETU The Elementary Time Unit (ETU) is an 11-bit up-counting counter and generates the clock, denoted as fETU to be used as the operating frequency for the UART transmission and reception in the Smart Card interface. The clock source of the ETU named as fCCLK comes from the fCRD clock and the frequency of fCCLK can be fCRD or fCRD/2 which is selected using the SMF bit in the MISC0 register. The fCRD clock is derived from the high speed clock, fM, and the fCRD frequency can be equal to the frequency of fM, fM/2, fM/3 or fM/4 selected by the Smart Card clock source selection bits, CRDCKS1 and CRDCKS0 The data transfer of the UART interface is a character frame based protocol, which is basically consists of a Start bit, 8-bit data and a Parity bit. The time period tETU (1/fETU), generated by the ETU, is the time unit for UART character bit. There are two registers related to the ETU known as the low byte ETU register CETU0 and the high byte ETU register CETU1, which store the expected contents of the ETU. Each time the high byte ETU register CETU1 is written, the ETU will reload the new written value and restart counting. The elementary time unit tETU is obtained from the following formula. tETU = (F/D)×(1/f) F: clock rate conversion integer D: baud rate adjustment integer f: clock rate of Smart Card Rev. 1.00 131 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces The values of F and D, as they appear in the above formula, will be obtained from the Answerto-Reset packet sent from the external Smart Card to the Smart Card interface, the first time the external Smart Card is inserted. When the Smart Card interface receives this information, the values which should be written into the CETU0 and CETU1 can be calculated by F/D. As the value of the ETU registers is obtained by the above formula, the calculation results of the value may not be an integer. If the calculation result is not an integer and is less than the integer n but greater than the integer (n-1), either the integer n or (n-1) should be written into the CETU0 and CETU1 registers depending upon whether the result is closer to n or (n-1). The integer n mentioned here is a decimal. If the calculation result is close to the value of (n-0.5), the compensation mode should be enabled by setting the compensation enable control bit COMP in the CETU1 register to 1 for successful data transfer. When the result is close to the value of (n-0.5) and the compensation mode is enabled, the value written into the CETU0 and CETU1 registers should be n and then the ETU will generate the time unit sequence with n clock cycles and next (n-1) clock cycles alternately and so on. This results in an average time unit of (n-0.5) clock cycles and allows the time granularity down to a half clock cycle. Note that the ETU will reload the ETU registers value and restart counting at the time when the Start bit appears in the UART mode. Sta�t bit Pa�ity bit Data bits CIO P tETU C�a�a�te� n n n n n n n n n n CO�P=0 (CETU=n) (1 tETU=n �lo�ks) CO�P=1 n n-1 n n-1 n n-1 n n-1 n n-1 Character Frame and Compensation Mode Guard Time Counter − GTC The Guard Time Counter (GTC) is a 9-bit up-counting counter and generates the minimum time duration known as a character frame denoted as tGTC between two successive characters in a UART transmission. The clock source of the GTC comes from the ETU named fETU. The character transmission rate of the UART interface is controlled by tGTC generated by the GTC. There are two registers related to the GTC known as the low byte GTC register, CGT0, and the high byte GTC register, CGT1, which store the expected value of the GTC. The GTC value will be reloaded at the end of the current guard time period. Note that the guard time between the last character received from the Smart Card and the next character transmitted by the Smart Card interface (Smart Card reader) should be managed by the application program. Rev. 1.00 132 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Waiting Time Counter − WTC The Waiting Time Counter (WTC) is a 24-bit down-counting counter and generates a maximum time duration denoted as tWTC for the data transmission. The clock source of the WTC comes from the ETU named fETU. The data transfer is categorized into 2 types. One is the Character transfer which means each data transmission or reception is one character while the other is the Blocks transfer which means each data transmission or reception is more than one character. The information related to the data transfer type or the number of the characters to be transferred is contained in the Answerto-Reset packet. There are three data registers for the WTC known as the low byte WTC register CWT0, the middle byte WTC register CWT1 and the high byte WTC register CWT2, which store the expected WTC values. The WTC can be used in both UART mode and Manual mode and can reload the value at specific conditions. The function of the WTC is controlled by the WTEN bit in the CCR register or by a configuration option. When the UART interface is set to be operated in the UART mode and the WTC is enabled, the updated CWT value will be loaded into the WTC as the Start bit is detected. If the UART interface is set to be operated in the Manual mode and the WTC is enabled, the updated CWT value will be loaded into the WTC. Regardless of whether it is in the UART mode or Manual mode, if the WTEN bit is cleared to ″0″, the updated CWT value will not be loaded into the WTC until the WTEN bit is again set to 1 and the WTC underflows from the current loaded value. When the transfer type is configured as a Character transfer, the WTC will generate the maximum timeout period of the Character Waiting Time (CWT). If the transfer type is configured as a Block transfer, the WTC will generate the Character Waiting Time (CWT) except for the last character. The Block Waiting Time (BWT) should be loaded into the WTC data registers before the Start bit of the last transmitted character occurs. As the Start bit of the last transmitted character occurs, the BWT value will be load into the WTC. Then the Smart Card may be expected to transmit data to the Smart Card interface in the BWT duration. If the Smart Card does not transmit any data characters, the WTC will underflow. When the WTC underflows, the corresponding request flag, WTF, in the CSR register will be set. The Waiting Time Underflow pending flag, WTP, in the CIPR register, will also be set if the interrupt enable control bit, WTE, in the CIER register is set. Then an interrupt will be generated to notify the MCU that the Smart Card has not responded to the Smart Card reader. Note that if the WTC value is set to zero, the WFT bit will be equal to ″1″. Sta�t bit P�og�am t�e BWT Sma�t Ca�d Inte�fa�e C�a� 0 C�a� 1 P�og�am t�e CWT C�a� n Sma�t Ca�d C�a� 0 BWT C�a� 1 CWT WTC is �eloaded on Sta�t bit Sta�t bit Rev. 1.00 133 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Smart Card UART Mode Data transfer with the external Smart Card is implemented into two operating modes. One is the UART mode while the other is the Manual mode. The data transfer mode is selected by the UART mode selection bit, UMOD, in the CCR register. When the UMOD bit is set to ″1″, the UART mode is enabled and data transfer operates in the UART mode. Otherwise, data transfer operates in the Manual mode if the UMOD bit is set to ″0″. The UART interface is a half-duplex interface and communicates with the external Smart Card via the CCLK and CIO pins. The CIO pin can be selected to be connected to a pull high resistor by a configuration option. After a reset condition the UART interface is in the reception mode but the UART mode is disabled. When the UART mode is selected, data transfer is driven by the UART circuits automatically through the CCLK and CIO pins. There are two data registers related to data transmission and reception, CTXB and CRXB, which store the data to be transmitted and received respectively. If a character is written into the CTXB register in the UART mode, the UART interface will automatically switch to the transmission mode from the reception mode after a reset. When the UART transmission or reception has finished, the corresponding request flag named TXCF or RXCF is set to ″1″. If the transmit buffer is empty, the transmit buffer empty flag, TXBEF, will be set to ″1″. The UART interface supports a parity generator and a parity check function. As the parity error occurs during a data transfer, the corresponding request flag named, PARF, in the CSR register will be set to ″1″. Once the PARF bit is set to ″1″, the Parity error pending flag PARP in the CIPR register will be set to ″1″ if the relevant interrupt control bit is enabled. Then an interrupt signal will be generated and sent to the MCU. There is a Character Repetition function supported by the UART interface when a parity error occurs. The Character repetition function is enabled by setting the CREP bit to 1 and then the repetition function is activated when the parity error occurs during data transfers. The repetition times can be selected to be 4 or 5 times by a configuration option. When the CREP bit is set to 1 and the repetition times is set to 4 times, the UART interface, if in the transmission mode, will transmit the data repeatedly for 4 times at most when an error signal occurs. If the data transmitted by the UART interface is received by the Smart Card receiver without a parity error during these 4 transmissions, the transmission request flag, TXCF, of the UART interface will be set to 1 and the PARF bit will be cleared to 0. If the UART interface is informed that there is still an error signal during the 4 transmissions, the parity error flag PARF of the UART interface will be set to 1 at the end of the 4th transmission but the transmission request flag TXCF will not be set. If the UART interface is in the reception mode together with the CREP bit being set to 1, it will inform the external Smart Card transmitter that there is a parity error for at most 4 times. If the data transmitted by the external Smart Card transmitter is received by the UART interface without a parity error during the 4 receptions, the reception request flag, RXCF, of the UART interface will be set to 1 and the PARF bit will be cleared to 0. If there is still a parity error during the 4 data receptions, the UART interface will inform the external Smart Card and the parity error flag, PARF, of the UART interface will be set to 1 at the end of the 4th reception as well as the reception request flag, RXCF. If the CREP bit is set to ″0″ and the UART interface is in the reception mode, both the PARF and RXCF bits will be set to ″1″ when the data with parity error has been received but the character repetition will not be activated. If the UART interface is in the transmission mode and the CREP bit is set to ″0″, it acts as a normal transmitter and the TXCF bit is set to ″1″ after the data has been transmitted. It has no effect on PARF bit. Rev. 1.00 134 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces When data is selected to be transferred in the Manual mode by setting the UMOD bit to 0, the data is controlled by the control bit, CIO, in the CCCR register. The value of the CIO bit will be reflected immediately on the CIO pin in the Manual mode. Note that in the Manual mode the character repetition function is not available as well as the related flags and all the data transfer is handled by the application program. The clock used to drive the external Smart Card that appears on the CCLK pin can be the fCCLK clock which is derived from the internal clock source named as the fCRD clock or the control bit, CCLK, in CCCR register and selected by the Smart Card selection bit, CLKSEL, in the CCCR register. When CLKSEL is set to 1 to select the clock source for the Smart Card to be fCCLK, a software control bit, SMF, can determine whether the clock output on the CCLK pin, which comes from the fCRD clock, is moreover to be divided by 2 or not. If users wish to handle the CCLK clock manually, the CLKSEL bit should first be set to 0 and then the value of the CCLK bit will be present on the CCLK pin When the Smart Card is first inserted, the data direction convention is sent first in the Answer-toReset packet to inform the Smart Card interface whether the MSB of the data is sent first or the LSB is sent first. If the direction convention used by the Smart Card is the same as the convention used by the Smart Card interface, the UART interface will generate a reception interrupt if the reception interrupt is enabled without a parity error flag. Otherwise, the UART interface will generate a reception interrupt and the parity error flag will be asserted. By checking the parity error flag the Smart Card interface can know if the data direction convention is correct or not. Power Control When the Smart Card is first inserted and detected, the power-on sequence for the external Smart Card should be activated by the application programs to supply power to the external Smart Card. All the information necessary for the Smart Card interface to communicate with the external Card is contained in the Answer-to-Reset packet including the data transfer type (Character or Blocks), the data direction convention (MSB or LSB first), the clock rate information (ETU, GTC or WTC), etc. The voltage level supplied to the Smart Card is also defined in the Answer-to-Reset packet. The Smart Card power supply voltage level is generated by the LDO and selected by the Smart Card Power Supply voltage selection bits VC1 and VC0 in the CCR register. When the external Smart Card is inserted, the application program should set the CRDVCC pin to the expected voltage level defined in the Answer-to-Reset packet. Similarly, the power deactivation procedure defined in the ISO 7816-3 standard should also be properly arranged by the application programs when the external Smart Card is removed. After the external Smart Card is removed, the Smart Card Interface Circuitry enable control bit, CVCC, in the CCCR Register will be automatically cleared to zero to prevent the Smart Card Interface module from being re-modified. The CRDVCC pin voltage level and the related Smart Card interface register contents will remain unchanged but the relevant Smart Card Interface pins including CRST, CCLK, CIO, CC4 and CC8 pins will be kept at a low level when the external Card is removed. The Power Control circuitry provides the Card voltage and current indicators to avoid malfunctions. When the Card voltage is within its specified range, the Card Voltage flag VCOK will be set to ″1″. If the Card is not in the specified range, the VCOK flag will be cleared to ″0″ to indicate that the Card voltage is not within the specified range. As the VCOK bit changes from 1 to 0, the corresponding pending flag named VCP in CIPR register will be set to ″1″ if the Card Voltage error interrupt control VCE in the CIER register is enabled. Rev. 1.00 135 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces When the current consumed by the external Smart Card is within the range specified in the ISO 7816-3 standard, the Card Current Overload flag IOVF will remain at a ″0″ value. If the Card current is not within the specified range, the IOVF flag will be set to ″1″ to indicate that the Card Current is too high. As the IOVF bit is set to 1, the relevant pending flag, IOVFP, in the CIPR register will also be set to 1 if the Card Current Overload interrupt control enable bit, IOVFE, in the CIER register is enabled. Smart Card Interrupt Structure There are several conditions for the Smart Card that to generate a Smart Card interrupt. When these conditions exist, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are a Smart Card Insertion/Removal, a Smart Card Voltage error, a Smart Card Current Overload, a Waiting Time Counter Underflow, a Parity error, an end of a Character Transmission or Reception and an empty Transmit buffer. When a Smart Card interrupt is generated by any of these conditions, then if the corresponding interrupt enable control bit in the host MCU is enabled and the stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program. For Smart Card interrupt events, except for Card Insertion/Removal events, there are corresponding pending flags which can be masked by the corresponding interrupt enable control bits. When the related interrupt enable control is disabled, the corresponding interrupt pending flag will not be affected by the request flag and no interrupt will be generated. If the related interrupt enable control is enabled, the relevant interrupt pending flag will be affected by the request flag and then the interrupt will be generated. The pending flag register CIPR is read only and once the pending flag is read by the application program, it will be automatically cleared while the related request flag should be cleared by the application program manually. When a Smart Card Insertion/Removal event occurs, the Card Insertion/Removal request flag, CIRF, will be set or clear depends on the presence of a card, and a Smart Card Insertion/Removal interrupt will be directly generated without any associated Smart Card interrupt control being enabled. For a Smart Card interrupt occurred to be serviced, in addition to the bits for the corresponding interrupt enable control in the Smart Card interface being set, the global interrupt enable control and the related interrupt enable control bits in the host MCU must also be set. If these bits are not set, then no interrupt will be serviced. Rev. 1.00 136 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Ca�d Inse�tion/Removal Request flag CIRF T�ansmit Buffe� Empty �equest flag TXBEF End of T�ansmission Request flag TXCF End of Re�eption Request flag RXCF Inte��upt Signal to �CU 0 TXBEE 0 TXCE RXCE End of Re�eption pending flag RXCP 1 0 PARE WTC Unde�flow Request flag WTF WTE Ca�d Cu��ent Ove�load Request flag IOVF IOVFE CSR Registe� End of T�ansmission pending flag TXCP 1 0 Pa�ity E��o� Request flag PARF Ca�d Voltage Status Request flag VCOK T�ansmit Buffe� Empty pending flag TXBEP 1 Pa�ity E��o� pending flag PARP 1 0 WTC Unde�flow pending flag WTP 1 0 Ca�d Cu��ent Ove�load pending flag IOVFP 1 0 VCE Inte��upt Signal to �CU Ca�d Voltage E��o� pending flag VCP 1 CIER Registe� CIPR Registe� Smart Card Interrupt Structure Programming Considerations Since the whole Smart Card interface is driven by the clock fCRD which is derived from the high speed oscillator clock f M, the Smart Card interface will not operate, even interface registers read/write operations, if the high speed oscillator clock fM is stopped. For example, if the MCU clock source is switched to the low speed clock fSL which comes from the low speed oscillator LXT or LIRC, then all operations related to the Smart Card interface are not performed. Rev. 1.00 137 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Smart Card Interface Status and Control Registers There are several registers associated with the Smart Card function. Some of the registers control the overall function of the Smart Card interface as well as the interrupts, while some of the registers contain the status bits which indicate the Smart Card data transfer situations, error conditions and power supply conditions. Also there are two registers for the UART transmission and reception respectively to store the data received from or to be transmitted to the external Smart Card. Address Name POR State Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 50H CCR 0000 0000 RSTCRD CDET VC1 VC0 UMOD 51H CSR 1000 0000 TXBEF CIRF IOVF VCOK WTF TXCF RXCF 52H CCCR 0-xx x0x0 CLKSEL — CC8 CC4 CIO CCLK CRST CVCC 53H CETU1 0000 0001 COMP — — — — 54H CETU0 0111 0100 ETU7 ETU6 ETU5 ETU4 ETU3 ---- ---0 WTEB CREP CONV PARF ETU10 ETU9 ETU8 ETU2 ETU1 ETU0 GT8 55H CGT1 — — — — — — — 56H CGT0 0000 1100 GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 57H CWT2 0000 0000 WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16 58H CWT1 0010 0101 WT15 WT14 WT13 WT12 WT11 WT10 WT9 WT8 59H CWT0 1000 0000 WT7 WT6 WT5 WT4 WT3 WT2 WT1 WT0 5AH CIER 0-00 0000 TXBEE — IOVFE VCE WTE TXCE RXCE PARE 5BH CIPR 0-00 0000 TXBEP — IOVFP VCP WTP TXCP RXCP PARP 5CH CTXB 0000 0000 Smart Card Transmission Buffer (TB7~TB0) 5DH CRXB 0000 0000 Smart Card Reception Buffer (RB7~RB0) Smart Card Interface Register Summary Rev. 1.00 138 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CCR Register The CCR register contains the control bits for the Smart Card interface. Further explanation on each bit is given below: Bit 7 6 5 4 3 2 1 0 Name RSTCRD CDET VC1 VC0 UMOD WTEN CREP CONV R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7RSTCRD: Reset control for the Smart Card interface 0: No Smart Card interface reset 1: Reset the Smart Card interface (except RSTC bit) This bit is used to reset the whole Smart Card interface except the RSTCRD bit. It is set and cleared by application program. Bit 6CDET: Card switch type selection 0: Switch is normally opened if no card is present 1: Switch is normally closed if no card is present This bit is set and cleared by application program to configure the switch type of the card detector. Bit 5~4VC1~VC0: Card voltage selection 00: Card voltage is equal to 0V 01: Card voltage is equal to 1.8V 10: Card voltage is equal to 3V 11: Card voltage is equal to 5V These bits are set and cleared by application program to select the voltage level for the external Smart Card. Bit 3UMOD: UART mode selection 0: Data transfer in Manual mode. 1: Data transfer in UART mode. This bit is set and cleared by application program to configure the data transfer type. If it is cleared to 0, the CIO pin status is the same as the value of the CIO bit in the CCCR register. If it is set to 1, the CIO pin is driven by the internal UART control circuitry. Before the data transfer type is switched from Manual mode to UART mode, the CIO bit must be set to 1 to avoid a UART malfunction. Bit 2WTEN: Waiting Time Counter (WTC) counting control 0: WTC stops counting. 1: WTC starts to count. The WTEN bit is set and cleared by application program. When the WTEN bit is cleared to 0, a write access to the CWT2 register will load the value held in the CWT2~CWT0 registers into the WTC. If it is set to 1, the WTC is enabled and automatically reloaded with the value in CWT2~CWT0 at each start bit occurrence. Bit 1CREP: Character Repetition enable control at parity error condition 0: No retry on parity error 1: Automatically retry on parity error The CREP bit is set and cleared by application program. When the CREP bit is cleared to 0, both the RXCF and PARF flags will be set on parity error in reception mode after the data is received while the PARF is set but the TXCF is cleared in the transmission mode. If the CREP bit is set to 1, the character retry will automatically be activated on parity error for 4 or 5 times depending upon the configuration option. In the transmission mode the character will be re-transmitted if the transmitted data is refused and then the parity error flag PARF will be set at the end of the 4th or 5th transmission but TXCF will not be set. In the reception mode if the received data has a parity error during the 4 or 5 data transfer, the receiver will inform the transmitter for 4 or 5 times and then the PARF and RXCF flags will both be set at the end of the 4th or 5th reception. Rev. 1.00 139 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 0CONV: Data direction convention 0: LSB is transferred first. Sets up the direct convention: state H encodes value 1 and conveys the least significant bit first. 1: MSB is transferred first. Sets up the inverse convention: state L encodes value 1 and conveys the most significant bit first. This bit is set and cleared by the application program to select if the data is LSB transferred first or MSB transferred first. When the direction convention is the same as the direction specified by the external Smart Card, only RXCF will be set to 1 without parity error. Otherwise, both RXCF and PARF will be set to 1 after the data is received. CSR Register The CSR register contains the status bits for the Smart Card interface. Further explanation on each bit is given below: Bit 7 6 5 4 3 2 1 0 Name TXBEF CIRF IOVF VCOK WTF TXCF RXCF PARF R/W R R R R R R/W R R/W POR 1 0 0 0 0 0 0 0 Bit 7TXBEF: Transmission buffer empty request flag 0: Transmission buffer is not empty 1: Transmission buffer is empty This bit is used to indicate if the transmit buffer is empty and is set or cleared by hardware automatically. Bit 6CIRF: Card Insertion/Removal request flag 0: No card is present. 1: A Card is present This bit is used to indicate if a card is present and is set or cleared by hardware automatically. This bit will trigger SCIRF bit synchronously. Bit 5IOVF: Card Current Overload request flag 0: No Card Current overload 1: Card Current overload The bit is set or cleared by hardware automatically and indicates whether the card current is overloaded. Bit 4VCOK: Card Voltage status flag 0: Card Voltage is not in the specified range 1: Card Voltage is in the specified range The bit is set or cleared by hardware automatically and indicates whether the card voltage is in the specified range. Bit 3WTF: Waiting Time Counter (WTC) underflow request flag 0: The WTC does not underflow. 1: The WTC underflows. This bit is set by hardware automatically and indicates if the WTC underflows, and cleared by application program, which steps: clr WTEN, access CWT2, set WTEN. Bit 2TXCF: Character transmission request flag 0: No character transmitted request 1: A character has been transmitted The TXCF bit is set by hardware and cleared by application program. If the bit is set to 1, it indicates that the character has been transmitted. Rev. 1.00 140 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 1RXCF: Character Repetition request flag 0: No character received request 1: A character has been received The RXCF bit is set by hardware automatically and cleared after a read access to the CRXB register by the application program. The RXCF bit will always be set to 1 when a character is received regardless of the result of the parity check. When the character has been received, the received data stored in the CRXB register should be moved to the data memory specified by users. If the contents of the CRXB register are not read before the end of the next character shifted in, the data stored in the CRXB register will be overwritten. Bit 0PARF: Parity error request flag 0: No parity error request 1: Parity error has been occurred This bit is set by hardware automatically and cleared by the application program. When a character is received, the parity check circuits will check that the parity is correct or not. If the result of the parity check is not correct, the parity error request flag, PARF, will be set to 1. Otherwise, the PARF bit will remain at zero. CCCR Register The CCCR register contains the control bits of the Smart Card interface pins. Further explanation on each bit is given below: Bit 7 6 5 4 3 2 1 0 Name CLKSEL — CC8 CC4 CIO CCLK CRST CVCC R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — x x x 0 x 0 "x": unknown Bit 7CLKSEL: Smart Card Clock selection 0: The content of the CCLK bit is present on the external CCLK pin 1: The clock output on the external CCLK pin comes from the fCCLK clock This bit is used to select which clock source is present on the external CCLK pin. It is set and cleared by application program. It is recommended that to activate the clock at a known level a certain value should be programmed into the CCLK bit before the CLKSEL bit is switched from 1 to 0. For detailed fCCLK selections, refer to the MISC0 register in this datasheet. Bit 6 Unimplemented, read as ″0″ Bit 5CC8: CC8 pin control 0: The status of the external CC8 pin is 0 1: The status of the external CC8 pin is 1 The bit is set and cleared by application program to control the external CC8 pin status. The value written into this bit will be present on the external CC8 pin. Reading this bit will return the status present on the CC8 pin. Bit 4CC4: CC4 pin control 0: The status of the external CC4 pin is 0 1: The status of the external CC4 pin is 1 The bit is set and cleared by application program to control the external CC4 pin status. The value written into this bit will be present on the external CC4 pin. Reading this bit will return the status present on the CC4 pin. Rev. 1.00 141 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 3CIO: CIO pin control 0: The status of the external CIO pin is 0 1: The external CIO pin remains at an open drain condition This bit is available only if the UMOD bit in the CCR register is cleared to 0 (Manual mode). It is set and cleared by application program to control the external CIO pin status in Manual mode. Reading this bit will return the status present on the CIO pin. A pull high resistor can be connected to the CIO pin determined by a configuration option. Bit 2CCLK: CCLK pin control 0: The status of the external CCLK pin is 0 1: The status of the external CCLK pin is 1 This bit is available only if the UMOD bit in the CCR register is cleared to 0 (Manual mode). The bit is set and cleared by application program to control the external CCLK pin status in Manual mode. Reading this bit will return the current value in the register instead of the status present on the CCLK pin. Bit 1CRST: CRST pin control 0: The status of the external CRST pin is 0 1: The status of the external CRST pin is 1 This bit is set and cleared by application program to control the external CRST pin status to be used to reset the external Smart Card. Reading this bit will return the present status of the CRST pin. Bit 0CVCC: Smart Card Interface Circuitry enable control 0: Smart card interface circuitry is disabled 1: Smart card interface circuitry is enabled. This bit is set and cleared by application program to control the Smart card interface module is switched on or off when the external Card is present. If the external Card is not present on the CDET pin, this bit is not available to control the Smart card interface circuitry and will automatically be cleared to 0 by hardware. Rev. 1.00 142 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces MISC0 Register Bit Name 7 6 CRDCKS1 CRDCKS0 5 4 3 2 1 0 SMF SMCEN INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6CRDCKS1~CRDCKS0: Smart Card interface clock source fCRD divided ratio selection Described in the table below. Bit 5SMF: Smart Card interface and clock output frequency fCCLK selection Described in the table below. Bit 4SMCEN: Smart Card interface clock control 0: fCCLK is disabled 1: fCCLK is enabled This bit is used to control the Smart Card interface clock source. If this bit is cleared to disable the clock, the relevant registers in the Smart Card interface module can not be accessed. When the Smart Card interface clock is disabled, it has no effect on the Card insertion or removal detections. Bit 3~2INT1S1~INT1S0: External Interrupt 1 active edge selection Described elsewhere. Bit 1~0INT0S1~INT0S0: External Interrupt 0 active edge selection Described elsewhere. Rev. 1.00 SMF CRDCKS1 CRDCKS0 fCCLK 0 0 0 fM/2 0 0 1 fM/3 0 1 0 fM/1 0 1 1 fM/4 1 0 0 fM/4 1 0 1 fM/6 1 1 0 fM/2 1 1 1 fM/8 143 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CETU Registers The CETU registers, CETU1 and CETU0, contain the specific values determined by the formula described in the ETU section. It also includes a control bit of the Compensation function for the ETU time granularity. Note that the value of the ETU must be in the range of 001H to 7FFH. To obtain the maximum ETU decimal value of 2048, a 000H value should be written into the ETU10~ETU0 bits. Further explanation on each bit is given below: • CETU1 Register Bit 7 6 5 4 3 2 1 0 Name COMP — — — — ETU10 ETU9 ETU8 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 1 Bit 7COMP: Compensation function enable control 0: Compensation function is disabled 1: Compensation function is enabled This bit is set and cleared by application program used to control the Compensation function. The Compensation function has been described and more details can be obtained in the ETU section. Bit 6~3 Unimplemented, read as ″0″ Bit 2~0ETU10~ETU8: bit 10~8 of the ETU value The bits are set and cleared by application program to modify the ETU values. Writing to the CETU1 register will reload the updated value into the ETU counter. • CETU0 Register Bit 7 6 5 4 3 2 1 0 Name ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 0 1 0 0 Bit 7~0ETU7~ETU0: bit 7~0 of the ETU value The bits are set and cleared by application program to modify the ETU values. Rev. 1.00 144 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CGT Registers The CGT registers named CGT1 and CGT0 store the specific GTC values obtained from the Answer-to-Reset packet described in the GTC section. Note that the GTC values must be in the range from 00CH to 1FFH. Further explanation on each bit is given below: • CGT1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — GT8 R/W — — — — — — — R/W POR — — — — — — — 0 4 3 2 1 0 Bit 7~1 Unimplemented, read as ″0″ Bit 0GT8: bit 8 of the GTC value • CGT0 Register Bit 7 6 5 Name GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 1 1 0 0 Bit 7~0GT7~GT0: bit 7~0 of the GTC value The bits GT8~GT0 are set and cleared by application program to modify the GTC values. The updated GTC value will be loaded into the GTC counter at the end of the current guard time period. CWT Registers The CWT registers, CWT2, CWT1 and CWT0, store the specific WTC value obtained from the Answer-to-Reset packet described in the WTC section. Note that the WTC value must be in the range from 0x002580H to 0xFFFFFFH. • CWT2 Register Bit 7 6 5 4 3 2 1 0 Name WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0WT23~WT16: bit 23~16 of the value • CWT1 Register Bit 7 6 5 4 3 2 1 0 Name WT15 WT14 WT13 WT12 WT11 WT10 WT9 WT8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 0 1 0 1 Bit 7~0WT15~WT8: bit 15~8 of the WTC value • CWT0 Register Bit 7 6 5 4 3 2 1 0 Name WT7 WT6 WT5 WT4 WT3 WT2 WT1 WT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 0 0 0 0 0 0 0 Bit 7~0WT7~WT0: bit 7~0 of the WTC value The bits WT23~WT0 are set and cleared by application program to modify the WTC values. The reload conditions of the updated WTC value are described in the WTC section. Users can refer to the WTC section for more details. Rev. 1.00 145 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CIER Register The CIER register contains the interrupt enable control bits for all of the interrupt events in the Smart Card interface. Further explanation on each bit is given below: Bit 7 6 5 4 3 2 1 0 Name TXBEE — IOVFE VCE WTE TXCE RXCE PARE R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7TXBEE: Transmit Buffer Empty interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program used to control the Transmit Buffer Empty interrupt. If this bit is set to 1, the Transmit Buffer Empty interrupt will be generated when the Transmit Buffer is empty. Bit 6 Unimplemented, read as ″0″ Bit 5IOVFE: Card Current Overload interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program and is used to control the Card Current Overload interrupt. If this bit is set to 1, the Card Current Overload interrupt will be generated when the Card Current is overloaded. Bit 4VCE: Card Voltage Error interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program and is used to control the Card Voltage Error interrupt. If this bit is set to 1, the Card Voltage Error interrupt will be generated when the Card Voltage is not in the specified range. Bit 3WTE: Waiting Time Counter Underflow interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program and is used to control the Waiting Time Counter Underflow interrupt. If this bit is set to 1, the Waiting Time Counter Underflow interrupt will be generated when the WTC underflows. Bit 2TXCE: Character Transmission Completion interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program and is used to control the Character Transmission Completion interrupt. If this bit is set to 1, the Character Transmission Completion interrupt will be generated at the end of the character transmission. Bit 1RXCE: Character Reception Completion interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program and is used to control the Character Reception Completion interrupt. If this bit is set to 1, the Character Reception Completion interrupt will be generated at the end of the character reception. Bit 0PARE: Parity Error interrupt enable control 0: Disable 1: Enable This bit is set and cleared by application program and is used to control the Parity Error interrupt. If this bit is set to 1, the Parity Error interrupt will be generated when a parity error occurs. Rev. 1.00 146 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CIPR Register The CIPR register contains the interrupt pending flags for all of the interrupt events in the Smart Card interface. These pending flags can be masked by the corresponding interrupt enable control bits. Further explanation on each bit is given below: Bit 7 6 5 4 3 2 1 0 Name TXBEP — IOVFP VCP WTP TXCP RXCP PARP R/W R — R R R R R R POR 0 — 0 0 0 0 0 0 Bit 7TXBEP: Transmit Buffer Empty interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Transmit Buffer Empty interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and the Transmit Buffer is empty, this bit will be set to 1 to indicate that the Transmit Buffer Empty interrupt is pending. Bit 6 Unimplemented, read as "0" Bit 5IOVFP: Card Current Overload interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Card Current Overload interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and the Card Current is overloaded, this bit will be set to 1 to indicate that the Card Current Overload interrupt is pending. Bit 4VCP: Card Voltage Error interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Card Voltage Error interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and the Card Voltage is not in the specified range, this bit will be set to 1 to indicate that the Card Voltage Error interrupt is pending. Bit 3WTP: Waiting Time Counter Underflow interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Waiting Time Counter Underflow interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and the WTC underflows, this bit will be set to 1 to indicate that the Waiting Time Counter Underflow interrupt is pending. Bit 2TXCP: Character Transmission Completion interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Character Transmission Completion interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and a character has been transmitted, this bit will be set to 1 to indicate that the Character Transmission Completion interrupt is pending. Rev. 1.00 147 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Bit 1RXCP: Character Reception Completion interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Character Reception Completion interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and a character has been received, this bit will be set to 1 to indicate that the Character Reception Completion interrupt is pending. Bit 0PARP: Parity Error interrupt pending flag 0: No interrupt pending 1: Interrupt pending This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Parity Error interrupt pending or not. If the corresponding interrupt enable control bit is set to 1 and the parity error occurs, this bit will be set to 1 to indicate that the Parity Error interrupt is pending. CTXB Register The CTXB register is used to store the data to be transmitted. Bit 7 6 5 4 3 2 1 0 Name TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TB7~TB0: data bits 7~0 to be transmitted CRXB Register The CRXB register is used to store the received data. As the character has been received completely, the value in CRXB register should be read to avoid the next character being overwritten. Bit 7 6 5 4 3 2 1 0 Name RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0RB7~RB0: bits 7~0 of the received data Rev. 1.00 148 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Options 1 High speed System oscillator selection - fM External XTAL oscillator (HXT), External RC oscillator (ERC), Internal RC oscillator (HIRC) or External Oscillator (EC) 2 External oscillator (EC) clock filter control: enable or disable 3 Internal RC oscillator (HIRC) frequency selection: 4MHz, 8MHz or 12MHz 4 Low speed System oscillator selection - fSL External 32.768kHz XTAL oscillator (LXT) or Internal 32kHz RC oscillator (LIRC) 5 Oscillator selection for fSUB External 32.768kHz XTAL oscillator (LXT) or Internal 32kHz RC oscillator (LIRC) 6 WDT Clock selection for fS fSUB or fSYS/4 Watchdog Options 7 Watchdog Timer function: enable or disable 8 CLRWDT instructions: 1 or 2 instructions 9 WDT time-out period: 212/fS, 213/fS, 214/fS or 215/fS Time Base Option 10 Time base time-out period selection: 212/fS, 213/fS, 214/fS or 215/fS Buzzer Options 11 I/O or Buzzer output selection: PA0, PA1; BZ, PA1 or BZ, BZ 12 Buzzer output frequency selection: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28 or fS/29 PFD Options 13 I/O or PFD output selection: PC1 or PFD 14 PFD source selection: PFD0 (from Timer/event counter 0) or PFD1 (from Timer/event counter 1) RES Pin Option 15 I/O or RES pin selection: PC7 or RES LVD/LVR Options 16 LVD function: enable or disable 17 LVR function: enable or disable 18 LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V or 4.2V/4.4V Smart Card Interface Options 19 CDET pin pull high function: enable or disable 20 CIO pin pull high function: enable or disable 21 Waiting Time Counter (WTC) function: enable or disable 22 Character transfer repetition times selection: 4 times or 5 times Rev. 1.00 149 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces No. Options SIM Option 23 Serial Interface Module 0 (SIM0) function: enable or disable 24 SPI0 WCOL bit function: enable or disable 25 SPI0 CSEN bit function: enable or disable 26 I2C0 clock debounce time selection: Disable, 1 system clock or 2 system clocks 27 Serial Interface Module 1 (SIM1) function: enable or disable 28 SPI1 WCOL bit function: enable or disable 29 SPI1 CSEN bit function: enable or disable 30 I2C1 clock debounce time selection: disable, 1 system clock or 2 system clocks Application Circuits Note: "*" Recommended component for added ESD protection. "**" Recommended component in environments where power line noise is significant. Rev. 1.00 150 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 151 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 152 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 153 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 154 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 155 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.00 156 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 157 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.00 158 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.00 159 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.00 160 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.00 161 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 162 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces TABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 163 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 164 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces 28-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.390 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol A Rev. 1.00 Dimensions in mm Min. Nom. Max. — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 9.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 165 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.472 BSC — B — 0.394 BSC — C — 0.472 BSC — D — 0.394 BSC — E — 0.032 BSC — F 0.012 0.015 0.018 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — 12.00 BSC — B — 10.00 BSC — C — 12.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.45 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 166 March 30, 2014 HT56RU25 TinyPowerTM A/D Type Smart Card OTP MCU with DAC, ISO 7816 and UART Interfaces Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 167 March 30, 2014